spi: sh-msiof: Avoid writing to registers from spi_master.setup()
[muen/linux.git] / drivers / spi / spi-sh-msiof.c
index 81a9144f5442cdb4827f2174281776a498f7cf9b..2704abb11ea41fd0561a23d6531b536f3cfc2db2 100644 (file)
@@ -55,6 +55,8 @@ struct sh_msiof_spi_priv {
        void *rx_dma_page;
        dma_addr_t tx_dma_addr;
        dma_addr_t rx_dma_addr;
+       bool native_cs_inited;
+       bool native_cs_high;
        bool slave_aborted;
 };
 
@@ -528,8 +530,7 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
 {
        struct device_node      *np = spi->master->dev.of_node;
        struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
-
-       pm_runtime_get_sync(&p->pdev->dev);
+       u32 clr, set, tmp;
 
        if (!np) {
                /*
@@ -539,19 +540,31 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
                spi->cs_gpio = (uintptr_t)spi->controller_data;
        }
 
-       /* Configure pins before deasserting CS */
-       sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
-                                 !!(spi->mode & SPI_CPHA),
-                                 !!(spi->mode & SPI_3WIRE),
-                                 !!(spi->mode & SPI_LSB_FIRST),
-                                 !!(spi->mode & SPI_CS_HIGH));
-
-       if (spi->cs_gpio >= 0)
+       if (spi->cs_gpio >= 0) {
                gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
+               return 0;
+       }
 
+       if (spi_controller_is_slave(p->master))
+               return 0;
 
-       pm_runtime_put(&p->pdev->dev);
+       if (p->native_cs_inited &&
+           (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
+               return 0;
 
+       /* Configure native chip select mode/polarity early */
+       clr = MDR1_SYNCMD_MASK;
+       set = MDR1_TRMD | TMDR1_PCON | MDR1_SYNCMD_SPI;
+       if (spi->mode & SPI_CS_HIGH)
+               clr |= BIT(MDR1_SYNCAC_SHIFT);
+       else
+               set |= BIT(MDR1_SYNCAC_SHIFT);
+       pm_runtime_get_sync(&p->pdev->dev);
+       tmp = sh_msiof_read(p, TMDR1) & ~clr;
+       sh_msiof_write(p, TMDR1, tmp | set);
+       pm_runtime_put(&p->pdev->dev);
+       p->native_cs_high = spi->mode & SPI_CS_HIGH;
+       p->native_cs_inited = true;
        return 0;
 }