Merge tag 'for-linus-unmerged' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma...
[muen/linux.git] / include / linux / mlx5 / mlx5_ifc.h
index fa6f134..1aad455 100644 (file)
@@ -145,6 +145,7 @@ enum {
        MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
        MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
        MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
+       MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
        MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
        MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
        MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
@@ -315,7 +316,10 @@ struct mlx5_ifc_flow_table_prop_layout_bits {
        u8         flow_table_modify[0x1];
        u8         encap[0x1];
        u8         decap[0x1];
-       u8         reserved_at_9[0x17];
+       u8         reserved_at_9[0x1];
+       u8         pop_vlan[0x1];
+       u8         push_vlan[0x1];
+       u8         reserved_at_c[0x14];
 
        u8         reserved_at_20[0x2];
        u8         log_max_ft_size[0x6];
@@ -598,6 +602,16 @@ struct mlx5_ifc_qos_cap_bits {
        u8         reserved_at_100[0x700];
 };
 
+struct mlx5_ifc_debug_cap_bits {
+       u8         reserved_at_0[0x20];
+
+       u8         reserved_at_20[0x2];
+       u8         stall_detect[0x1];
+       u8         reserved_at_23[0x1d];
+
+       u8         reserved_at_40[0x7c0];
+};
+
 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
        u8         csum_cap[0x1];
        u8         vlan_cap[0x1];
@@ -878,7 +892,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         out_of_seq_cnt[0x1];
        u8         vport_counters[0x1];
        u8         retransmission_q_counters[0x1];
-       u8         reserved_at_183[0x1];
+       u8         debug[0x1];
        u8         modify_rq_counter_set_id[0x1];
        u8         rq_delay_drop[0x1];
        u8         max_qp_cnt[0xa];
@@ -888,7 +902,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         vhca_group_manager[0x1];
        u8         ib_virt[0x1];
        u8         eth_virt[0x1];
-       u8         reserved_at_1a4[0x1];
+       u8         vnic_env_queue_counters[0x1];
        u8         ets[0x1];
        u8         nic_flow_table[0x1];
        u8         eswitch_flow_table[0x1];
@@ -1024,7 +1038,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         reserved_at_330[0xb];
        u8         log_max_xrcd[0x5];
 
-       u8         reserved_at_340[0x8];
+       u8         nic_receive_steering_discard[0x1];
+       u8         receive_discard_vport_down[0x1];
+       u8         transmit_discard_vport_down[0x1];
+       u8         reserved_at_343[0x5];
        u8         log_max_flow_counter_bulk[0x8];
        u8         max_flow_counter_15_0[0x10];
 
@@ -1048,7 +1065,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         reserved_at_398[0x3];
        u8         log_max_tis_per_sq[0x5];
 
-       u8         reserved_at_3a0[0x3];
+       u8         ext_stride_num_range[0x1];
+       u8         reserved_at_3a1[0x2];
        u8         log_max_stride_sz_rq[0x5];
        u8         reserved_at_3a8[0x3];
        u8         log_min_stride_sz_rq[0x5];
@@ -1215,9 +1233,9 @@ struct mlx5_ifc_wq_bits {
        u8         log_hairpin_num_packets[0x5];
        u8         reserved_at_128[0x3];
        u8         log_hairpin_data_sz[0x5];
-       u8         reserved_at_130[0x5];
 
-       u8         log_wqe_num_of_strides[0x3];
+       u8         reserved_at_130[0x4];
+       u8         log_wqe_num_of_strides[0x4];
        u8         two_byte_shift_en[0x1];
        u8         reserved_at_139[0x4];
        u8         log_wqe_stride_size[0x3];
@@ -1599,7 +1617,17 @@ struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
 
        u8         rx_pause_transition_low[0x20];
 
-       u8         reserved_at_3c0[0x400];
+       u8         reserved_at_3c0[0x40];
+
+       u8         device_stall_minor_watermark_cnt_high[0x20];
+
+       u8         device_stall_minor_watermark_cnt_low[0x20];
+
+       u8         device_stall_critical_watermark_cnt_high[0x20];
+
+       u8         device_stall_critical_watermark_cnt_low[0x20];
+
+       u8         reserved_at_480[0x340];
 };
 
 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
@@ -2314,10 +2342,19 @@ enum {
        MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
        MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
        MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
+       MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
+       MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
+};
+
+struct mlx5_ifc_vlan_bits {
+       u8         ethtype[0x10];
+       u8         prio[0x3];
+       u8         cfi[0x1];
+       u8         vid[0xc];
 };
 
 struct mlx5_ifc_flow_context_bits {
-       u8         reserved_at_0[0x20];
+       struct mlx5_ifc_vlan_bits push_vlan;
 
        u8         group_id[0x20];
 
@@ -2393,6 +2430,24 @@ struct mlx5_ifc_xrc_srqc_bits {
        u8         reserved_at_180[0x80];
 };
 
+struct mlx5_ifc_vnic_diagnostic_statistics_bits {
+       u8         counter_error_queues[0x20];
+
+       u8         total_error_queues[0x20];
+
+       u8         send_queue_priority_update_flow[0x20];
+
+       u8         reserved_at_60[0x20];
+
+       u8         nic_receive_steering_discard[0x40];
+
+       u8         receive_discard_vport_down[0x40];
+
+       u8         transmit_discard_vport_down[0x40];
+
+       u8         reserved_at_140[0xec0];
+};
+
 struct mlx5_ifc_traffic_counter_bits {
        u8         packets[0x40];
 
@@ -3673,6 +3728,35 @@ struct mlx5_ifc_query_vport_state_in_bits {
        u8         reserved_at_60[0x20];
 };
 
+struct mlx5_ifc_query_vnic_env_out_bits {
+       u8         status[0x8];
+       u8         reserved_at_8[0x18];
+
+       u8         syndrome[0x20];
+
+       u8         reserved_at_40[0x40];
+
+       struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
+};
+
+enum {
+       MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
+};
+
+struct mlx5_ifc_query_vnic_env_in_bits {
+       u8         opcode[0x10];
+       u8         reserved_at_10[0x10];
+
+       u8         reserved_at_20[0x10];
+       u8         op_mod[0x10];
+
+       u8         other_vport[0x1];
+       u8         reserved_at_41[0xf];
+       u8         vport_number[0x10];
+
+       u8         reserved_at_60[0x20];
+};
+
 struct mlx5_ifc_query_vport_counter_out_bits {
        u8         status[0x8];
        u8         reserved_at_8[0x18];
@@ -7850,7 +7934,11 @@ struct mlx5_ifc_pifr_reg_bits {
 struct mlx5_ifc_pfcc_reg_bits {
        u8         reserved_at_0[0x8];
        u8         local_port[0x8];
-       u8         reserved_at_10[0x10];
+       u8         reserved_at_10[0xb];
+       u8         ppan_mask_n[0x1];
+       u8         minor_stall_mask[0x1];
+       u8         critical_stall_mask[0x1];
+       u8         reserved_at_1e[0x2];
 
        u8         ppan[0x4];
        u8         reserved_at_24[0x4];
@@ -7860,17 +7948,22 @@ struct mlx5_ifc_pfcc_reg_bits {
 
        u8         pptx[0x1];
        u8         aptx[0x1];
-       u8         reserved_at_42[0x6];
+       u8         pptx_mask_n[0x1];
+       u8         reserved_at_43[0x5];
        u8         pfctx[0x8];
        u8         reserved_at_50[0x10];
 
        u8         pprx[0x1];
        u8         aprx[0x1];
-       u8         reserved_at_62[0x6];
+       u8         pprx_mask_n[0x1];
+       u8         reserved_at_63[0x5];
        u8         pfcrx[0x8];
        u8         reserved_at_70[0x10];
 
-       u8         reserved_at_80[0x80];
+       u8         device_stall_minor_watermark[0x10];
+       u8         device_stall_critical_watermark[0x10];
+
+       u8         reserved_at_a0[0x60];
 };
 
 struct mlx5_ifc_pelc_reg_bits {
@@ -7911,8 +8004,10 @@ struct mlx5_ifc_peir_reg_bits {
 };
 
 struct mlx5_ifc_pcam_enhanced_features_bits {
-       u8         reserved_at_0[0x7b];
+       u8         reserved_at_0[0x76];
 
+       u8         pfcc_mask[0x1];
+       u8         reserved_at_77[0x4];
        u8         rx_buffer_fullness_counters[0x1];
        u8         ptys_connector_type[0x1];
        u8         reserved_at_7d[0x1];