drm/amdgpu: add uvd enc registers in header
authorJames Zhu <James.Zhu@amd.com>
Mon, 2 Oct 2017 00:00:07 +0000 (20:00 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 6 Oct 2017 21:43:53 +0000 (17:43 -0400)
commitd0e62855fa7aea4736297abcbe4f0777f1332883
treef87f9e4e4412e3a96bfc6a28c6a2b080b5507fb5
parent4b6aca2f59dca3228a370ddefc94f3a44e57c772
drm/amdgpu: add uvd enc registers in header

Add UVD encode write/read/size/base registers definition for uvd6.3 HEVC ecoding

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian K├Ânig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h