Merge airlied/drm-next into drm-intel-next-queued
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 10 Aug 2017 16:12:01 +0000 (18:12 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 10 Aug 2017 16:12:01 +0000 (18:12 +0200)
Ben Widawsky/Daniel Stone need the extended modifier support from
drm-misc to be able to merge CCS support for i915.ko

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
74 files changed:
Documentation/gpu/i915.rst
drivers/gpu/drm/drm_atomic_helper.c
drivers/gpu/drm/i915/gvt/display.c
drivers/gpu/drm/i915/gvt/handlers.c
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_clflush.c
drivers/gpu/drm/i915/i915_gem_clflush.h
drivers/gpu/drm/i915/i915_gem_context.c
drivers/gpu/drm/i915/i915_gem_context.h
drivers/gpu/drm/i915/i915_gem_execbuffer.c
drivers/gpu/drm/i915/i915_gem_render_state.c
drivers/gpu/drm/i915/i915_gem_request.c
drivers/gpu/drm/i915/i915_gem_shrinker.c
drivers/gpu/drm/i915/i915_gem_stolen.c
drivers/gpu/drm/i915/i915_gpu_error.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_oa_bdw.c
drivers/gpu/drm/i915/i915_oa_bdw.h
drivers/gpu/drm/i915/i915_oa_bxt.c
drivers/gpu/drm/i915/i915_oa_bxt.h
drivers/gpu/drm/i915/i915_oa_chv.c
drivers/gpu/drm/i915/i915_oa_chv.h
drivers/gpu/drm/i915/i915_oa_glk.c
drivers/gpu/drm/i915/i915_oa_glk.h
drivers/gpu/drm/i915/i915_oa_hsw.c
drivers/gpu/drm/i915/i915_oa_hsw.h
drivers/gpu/drm/i915/i915_oa_kblgt2.c
drivers/gpu/drm/i915/i915_oa_kblgt2.h
drivers/gpu/drm/i915/i915_oa_kblgt3.c
drivers/gpu/drm/i915/i915_oa_kblgt3.h
drivers/gpu/drm/i915/i915_oa_sklgt2.c
drivers/gpu/drm/i915/i915_oa_sklgt2.h
drivers/gpu/drm/i915/i915_oa_sklgt3.c
drivers/gpu/drm/i915/i915_oa_sklgt3.h
drivers/gpu/drm/i915/i915_oa_sklgt4.c
drivers/gpu/drm/i915/i915_oa_sklgt4.h
drivers/gpu/drm/i915/i915_params.c
drivers/gpu/drm/i915/i915_params.h
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/i915_perf.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/i915_sysfs.c
drivers/gpu/drm/i915/i915_vma.h
drivers/gpu/drm/i915/intel_color.c
drivers/gpu/drm/i915/intel_ddi.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp_aux_backlight.c
drivers/gpu/drm/i915/intel_dp_link_training.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_engine_cs.c
drivers/gpu/drm/i915/intel_fbdev.c
drivers/gpu/drm/i915/intel_fifo_underrun.c
drivers/gpu/drm/i915/intel_hangcheck.c
drivers/gpu/drm/i915/intel_hdmi.c
drivers/gpu/drm/i915/intel_i2c.c
drivers/gpu/drm/i915/intel_lrc.c
drivers/gpu/drm/i915/intel_lrc.h
drivers/gpu/drm/i915/intel_panel.c
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_psr.c
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_runtime_pm.c
drivers/gpu/drm/i915/intel_sdvo.c
drivers/gpu/drm/i915/intel_sprite.c
drivers/gpu/drm/i915/selftests/intel_hangcheck.c
drivers/gpu/drm/i915/selftests/mock_context.c
drivers/gpu/drm/i915/selftests/mock_context.h
drivers/gpu/drm/i915/selftests/mock_engine.c
drivers/gpu/drm/i915/selftests/mock_engine.h
drivers/gpu/drm/i915/selftests/mock_gem_device.c
include/uapi/drm/i915_drm.h

index 9c7ed3e..46875c2 100644 (file)
@@ -417,6 +417,10 @@ integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.
    :functions: i915_perf_open_ioctl
 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
    :functions: i915_perf_release
+.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
+   :functions: i915_perf_add_config_ioctl
+.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
+   :functions: i915_perf_remove_config_ioctl
 
 i915 Perf Stream
 ----------------
index 1bc32cd..4e53aae 100644 (file)
@@ -2716,6 +2716,7 @@ int drm_atomic_helper_disable_all(struct drm_device *dev,
        struct drm_plane *plane;
        struct drm_crtc_state *crtc_state;
        struct drm_crtc *crtc;
+       unsigned plane_mask = 0;
        int ret, i;
 
        state = drm_atomic_state_alloc(dev);
@@ -2758,10 +2759,14 @@ int drm_atomic_helper_disable_all(struct drm_device *dev,
                        goto free;
 
                drm_atomic_set_fb_for_plane(plane_state, NULL);
+               plane_mask |= BIT(drm_plane_index(plane));
+               plane->old_fb = plane->fb;
        }
 
        ret = drm_atomic_commit(state);
 free:
+       if (plane_mask)
+               drm_atomic_clean_old_fb(dev, plane_mask, ret);
        drm_atomic_state_put(state);
        return ret;
 }
@@ -2892,11 +2897,16 @@ int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state,
        struct drm_connector_state *new_conn_state;
        struct drm_crtc *crtc;
        struct drm_crtc_state *new_crtc_state;
+       unsigned plane_mask = 0;
+       struct drm_device *dev = state->dev;
+       int ret;
 
        state->acquire_ctx = ctx;
 
-       for_each_new_plane_in_state(state, plane, new_plane_state, i)
+       for_each_new_plane_in_state(state, plane, new_plane_state, i) {
+               plane_mask |= BIT(drm_plane_index(plane));
                state->planes[i].old_state = plane->state;
+       }
 
        for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
                state->crtcs[i].old_state = crtc->state;
@@ -2904,7 +2914,11 @@ int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state,
        for_each_new_connector_in_state(state, connector, new_conn_state, i)
                state->connectors[i].old_state = connector->state;
 
-       return drm_atomic_commit(state);
+       ret = drm_atomic_commit(state);
+       if (plane_mask)
+               drm_atomic_clean_old_fb(dev, plane_mask, ret);
+
+       return ret;
 }
 EXPORT_SYMBOL(drm_atomic_helper_commit_duplicated_state);
 
index 2deb05f..24cc4b0 100644 (file)
@@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
                                SDE_PORTE_HOTPLUG_SPT);
                vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
                                SKL_FUSE_DOWNLOAD_STATUS |
-                               SKL_FUSE_PG0_DIST_STATUS |
-                               SKL_FUSE_PG1_DIST_STATUS |
-                               SKL_FUSE_PG2_DIST_STATUS;
+                               SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
+                               SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
+                               SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
                vgpu_vreg(vgpu, LCPLL1_CTL) |=
                                LCPLL_PLL_ENABLE |
                                LCPLL_PLL_LOCK;
index 17febe8..aeecf31 100644 (file)
@@ -1222,10 +1222,12 @@ static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
 {
        write_vreg(vgpu, offset, p_data, bytes);
 
-       if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST)
-               vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED;
+       if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL))
+               vgpu_vreg(vgpu, offset) |=
+                       HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
        else
-               vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED;
+               vgpu_vreg(vgpu, offset) &=
+                       ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
        return 0;
 }
 
index 2ef75c1..6480897 100644 (file)
@@ -543,75 +543,6 @@ static int i915_gem_gtt_info(struct seq_file *m, void *data)
        return 0;
 }
 
-static int i915_gem_pageflip_info(struct seq_file *m, void *data)
-{
-       struct drm_i915_private *dev_priv = node_to_i915(m->private);
-       struct drm_device *dev = &dev_priv->drm;
-       struct intel_crtc *crtc;
-       int ret;
-
-       ret = mutex_lock_interruptible(&dev->struct_mutex);
-       if (ret)
-               return ret;
-
-       for_each_intel_crtc(dev, crtc) {
-               const char pipe = pipe_name(crtc->pipe);
-               const char plane = plane_name(crtc->plane);
-               struct intel_flip_work *work;
-
-               spin_lock_irq(&dev->event_lock);
-               work = crtc->flip_work;
-               if (work == NULL) {
-                       seq_printf(m, "No flip due on pipe %c (plane %c)\n",
-                                  pipe, plane);
-               } else {
-                       u32 pending;
-                       u32 addr;
-
-                       pending = atomic_read(&work->pending);
-                       if (pending) {
-                               seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
-                                          pipe, plane);
-                       } else {
-                               seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
-                                          pipe, plane);
-                       }
-                       if (work->flip_queued_req) {
-                               struct intel_engine_cs *engine = work->flip_queued_req->engine;
-
-                               seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n",
-                                          engine->name,
-                                          work->flip_queued_req->global_seqno,
-                                          intel_engine_last_submit(engine),
-                                          intel_engine_get_seqno(engine),
-                                          i915_gem_request_completed(work->flip_queued_req));
-                       } else
-                               seq_printf(m, "Flip not associated with any ring\n");
-                       seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
-                                  work->flip_queued_vblank,
-                                  work->flip_ready_vblank,
-                                  intel_crtc_get_vblank_counter(crtc));
-                       seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
-
-                       if (INTEL_GEN(dev_priv) >= 4)
-                               addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
-                       else
-                               addr = I915_READ(DSPADDR(crtc->plane));
-                       seq_printf(m, "Current scanout address 0x%08x\n", addr);
-
-                       if (work->pending_flip_obj) {
-                               seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
-                               seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
-                       }
-               }
-               spin_unlock_irq(&dev->event_lock);
-       }
-
-       mutex_unlock(&dev->struct_mutex);
-
-       return 0;
-}
-
 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -2852,7 +2783,7 @@ out:
 static int i915_energy_uJ(struct seq_file *m, void *data)
 {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
-       u64 power;
+       unsigned long long power;
        u32 units;
 
        if (INTEL_GEN(dev_priv) < 6)
@@ -2860,15 +2791,18 @@ static int i915_energy_uJ(struct seq_file *m, void *data)
 
        intel_runtime_pm_get(dev_priv);
 
-       rdmsrl(MSR_RAPL_POWER_UNIT, power);
-       power = (power & 0x1f00) >> 8;
-       units = 1000000 / (1 << power); /* convert to uJ */
+       if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
+               intel_runtime_pm_put(dev_priv);
+               return -ENODEV;
+       }
+
+       units = (power & 0x1f00) >> 8;
        power = I915_READ(MCH_SECP_NRG_STTS);
-       power *= units;
+       power = (1000000 * power) >> units; /* convert to uJ */
 
        intel_runtime_pm_put(dev_priv);
 
-       seq_printf(m, "%llu", (long long unsigned)power);
+       seq_printf(m, "%llu", power);
 
        return 0;
 }
@@ -3394,8 +3328,10 @@ static int i915_engine_info(struct seq_file *m, void *unused)
                        ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
                        read = GEN8_CSB_READ_PTR(ptr);
                        write = GEN8_CSB_WRITE_PTR(ptr);
-                       seq_printf(m, "\tExeclist CSB read %d, write %d\n",
-                                  read, write);
+                       seq_printf(m, "\tExeclist CSB read %d, write %d, interrupt posted? %s\n",
+                                  read, write,
+                                  yesno(test_bit(ENGINE_IRQ_EXECLIST,
+                                                 &engine->irq_posted)));
                        if (read >= GEN8_CSB_ENTRIES)
                                read = 0;
                        if (write >= GEN8_CSB_ENTRIES)
@@ -4854,7 +4790,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
        {"i915_gem_gtt", i915_gem_gtt_info, 0},
        {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
        {"i915_gem_stolen", i915_gem_stolen_list_info },
-       {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
        {"i915_gem_request", i915_gem_request_info, 0},
        {"i915_gem_seqno", i915_gem_seqno_info, 0},
        {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
index 4c96a72..25de4a9 100644 (file)
@@ -237,17 +237,17 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
                                        !IS_KABYLAKE(dev_priv));
                        } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
                                dev_priv->pch_type = PCH_KBP;
-                               DRM_DEBUG_KMS("Found KabyPoint PCH\n");
+                               DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
                                WARN_ON(!IS_SKYLAKE(dev_priv) &&
                                        !IS_KABYLAKE(dev_priv));
                        } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
                                dev_priv->pch_type = PCH_CNP;
-                               DRM_DEBUG_KMS("Found CannonPoint PCH\n");
+                               DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
                                WARN_ON(!IS_CANNONLAKE(dev_priv) &&
                                        !IS_COFFEELAKE(dev_priv));
                        } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
                                dev_priv->pch_type = PCH_CNP;
-                               DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
+                               DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
                                WARN_ON(!IS_CANNONLAKE(dev_priv) &&
                                        !IS_COFFEELAKE(dev_priv));
                        } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
@@ -596,7 +596,8 @@ static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 
 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 {
-       flush_workqueue(dev_priv->wq);
+       /* Flush any outstanding unpin_work. */
+       i915_gem_drain_workqueue(dev_priv);
 
        mutex_lock(&dev_priv->drm.struct_mutex);
        intel_uc_fini_hw(dev_priv);
@@ -875,7 +876,6 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
        spin_lock_init(&dev_priv->uncore.lock);
 
        spin_lock_init(&dev_priv->mm.object_stat_lock);
-       spin_lock_init(&dev_priv->mmio_flip_lock);
        mutex_init(&dev_priv->sb_lock);
        mutex_init(&dev_priv->modeset_restore_lock);
        mutex_init(&dev_priv->av_mutex);
@@ -1240,6 +1240,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
  */
 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 {
+       intel_fbdev_unregister(dev_priv);
        intel_audio_deinit(dev_priv);
 
        intel_gpu_ips_teardown();
@@ -1371,7 +1372,7 @@ void i915_driver_unload(struct drm_device *dev)
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct pci_dev *pdev = dev_priv->drm.pdev;
 
-       intel_fbdev_fini(dev);
+       i915_driver_unregister(dev_priv);
 
        if (i915_gem_suspend(dev_priv))
                DRM_ERROR("failed to idle hardware; continuing to unload!\n");
@@ -1382,8 +1383,6 @@ void i915_driver_unload(struct drm_device *dev)
 
        intel_gvt_cleanup(dev_priv);
 
-       i915_driver_unregister(dev_priv);
-
        intel_modeset_cleanup(dev);
 
        /*
@@ -1409,9 +1408,6 @@ void i915_driver_unload(struct drm_device *dev)
        cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
        i915_reset_error_state(dev_priv);
 
-       /* Flush any outstanding unpin_work. */
-       drain_workqueue(dev_priv->wq);
-
        i915_gem_fini(dev_priv);
        intel_uc_fini_fw(dev_priv);
        intel_fbc_cleanup_cfb(dev_priv);
@@ -1835,7 +1831,8 @@ static int i915_resume_switcheroo(struct drm_device *dev)
 
 /**
  * i915_reset - reset chip after a hang
- * @dev_priv: device private to reset
+ * @i915: #drm_i915_private to reset
+ * @flags: Instructions
  *
  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
  * on failure.
@@ -1850,33 +1847,34 @@ static int i915_resume_switcheroo(struct drm_device *dev)
  *   - re-init interrupt state
  *   - re-init display
  */
-void i915_reset(struct drm_i915_private *dev_priv)
+void i915_reset(struct drm_i915_private *i915, unsigned int flags)
 {
-       struct i915_gpu_error *error = &dev_priv->gpu_error;
+       struct i915_gpu_error *error = &i915->gpu_error;
        int ret;
 
-       lockdep_assert_held(&dev_priv->drm.struct_mutex);
+       lockdep_assert_held(&i915->drm.struct_mutex);
        GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
 
        if (!test_bit(I915_RESET_HANDOFF, &error->flags))
                return;
 
        /* Clear any previous failed attempts at recovery. Time to try again. */
-       if (!i915_gem_unset_wedged(dev_priv))
+       if (!i915_gem_unset_wedged(i915))
                goto wakeup;
 
+       if (!(flags & I915_RESET_QUIET))
+               dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
        error->reset_count++;
 
-       pr_notice("drm/i915: Resetting chip after gpu hang\n");
-       disable_irq(dev_priv->drm.irq);
-       ret = i915_gem_reset_prepare(dev_priv);
+       disable_irq(i915->drm.irq);
+       ret = i915_gem_reset_prepare(i915);
        if (ret) {
                DRM_ERROR("GPU recovery failed\n");
-               intel_gpu_reset(dev_priv, ALL_ENGINES);
+               intel_gpu_reset(i915, ALL_ENGINES);
                goto error;
        }
 
-       ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
+       ret = intel_gpu_reset(i915, ALL_ENGINES);
        if (ret) {
                if (ret != -ENODEV)
                        DRM_ERROR("Failed to reset chip: %i\n", ret);
@@ -1885,8 +1883,8 @@ void i915_reset(struct drm_i915_private *dev_priv)
                goto error;
        }
 
-       i915_gem_reset(dev_priv);
-       intel_overlay_reset(dev_priv);
+       i915_gem_reset(i915);
+       intel_overlay_reset(i915);
 
        /* Ok, now get things going again... */
 
@@ -1902,17 +1900,17 @@ void i915_reset(struct drm_i915_private *dev_priv)
         * was running at the time of the reset (i.e. we weren't VT
         * switched away).
         */
-       ret = i915_gem_init_hw(dev_priv);
+       ret = i915_gem_init_hw(i915);
        if (ret) {
                DRM_ERROR("Failed hw init on reset %d\n", ret);
                goto error;
        }
 
-       i915_queue_hangcheck(dev_priv);
+       i915_queue_hangcheck(i915);
 
 finish:
-       i915_gem_reset_finish(dev_priv);
-       enable_irq(dev_priv->drm.irq);
+       i915_gem_reset_finish(i915);
+       enable_irq(i915->drm.irq);
 
 wakeup:
        clear_bit(I915_RESET_HANDOFF, &error->flags);
@@ -1920,14 +1918,15 @@ wakeup:
        return;
 
 error:
-       i915_gem_set_wedged(dev_priv);
-       i915_gem_retire_requests(dev_priv);
+       i915_gem_set_wedged(i915);
+       i915_gem_retire_requests(i915);
        goto finish;
 }
 
 /**
  * i915_reset_engine - reset GPU engine to recover from a hang
  * @engine: engine to reset
+ * @flags: options
  *
  * Reset a specific GPU engine. Useful if a hang is detected.
  * Returns zero on successful reset or otherwise an error code.
@@ -1937,7 +1936,7 @@ error:
  *  - reset engine (which will force the engine to idle)
  *  - re-init/configure engine
  */
-int i915_reset_engine(struct intel_engine_cs *engine)
+int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
 {
        struct i915_gpu_error *error = &engine->i915->gpu_error;
        struct drm_i915_gem_request *active_request;
@@ -1945,7 +1944,11 @@ int i915_reset_engine(struct intel_engine_cs *engine)
 
        GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
 
-       DRM_DEBUG_DRIVER("resetting %s\n", engine->name);
+       if (!(flags & I915_RESET_QUIET)) {
+               dev_notice(engine->i915->drm.dev,
+                          "Resetting %s after gpu hang\n", engine->name);
+       }
+       error->reset_engine_count[engine->id]++;
 
        active_request = i915_gem_reset_prepare_engine(engine);
        if (IS_ERR(active_request)) {
@@ -1954,18 +1957,7 @@ int i915_reset_engine(struct intel_engine_cs *engine)
                goto out;
        }
 
-       /*
-        * The request that caused the hang is stuck on elsp, we know the
-        * active request and can drop it, adjust head to skip the offending
-        * request to resume executing remaining requests in the queue.
-        */
-       i915_gem_reset_engine(engine, active_request);
-
-       /* Finally, reset just this engine. */
        ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine));
-
-       i915_gem_reset_finish_engine(engine);
-
        if (ret) {
                /* If we fail here, we expect to fallback to a global reset */
                DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
@@ -1973,6 +1965,13 @@ int i915_reset_engine(struct intel_engine_cs *engine)
                goto out;
        }
 
+       /*
+        * The request that caused the hang is stuck on elsp, we know the
+        * active request and can drop it, adjust head to skip the offending
+        * request to resume executing remaining requests in the queue.
+        */
+       i915_gem_reset_engine(engine, active_request);
+
        /*
         * The engine and its registers (and workarounds in case of render)
         * have been reset to their default values. Follow the init_ring
@@ -1982,8 +1981,8 @@ int i915_reset_engine(struct intel_engine_cs *engine)
        if (ret)
                goto out;
 
-       error->reset_engine_count[engine->id]++;
 out:
+       i915_gem_reset_finish_engine(engine);
        return ret;
 }
 
@@ -2730,6 +2729,8 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
        DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
        DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
        DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
+       DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+       DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
 };
 
 static struct drm_driver driver = {
index 7c6fab0..907603c 100644 (file)
@@ -80,8 +80,8 @@
 
 #define DRIVER_NAME            "i915"
 #define DRIVER_DESC            "Intel Graphics"
-#define DRIVER_DATE            "20170717"
-#define DRIVER_TIMESTAMP       1500275179
+#define DRIVER_DATE            "20170731"
+#define DRIVER_TIMESTAMP       1501488491
 
 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
@@ -602,7 +602,7 @@ struct drm_i915_file_private {
  * to limit the badly behaving clients access to gpu.
  */
 #define I915_MAX_CLIENT_CONTEXT_BANS 3
-       int context_bans;
+       atomic_t context_bans;
 };
 
 /* Used by dp and fdi links */
@@ -715,11 +715,6 @@ struct drm_i915_display_funcs {
        void (*fdi_link_train)(struct intel_crtc *crtc,
                               const struct intel_crtc_state *crtc_state);
        void (*init_clock_gating)(struct drm_i915_private *dev_priv);
-       int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
-                         struct drm_framebuffer *fb,
-                         struct drm_i915_gem_object *obj,
-                         struct drm_i915_gem_request *req,
-                         uint32_t flags);
        void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
        /* clock updates for mode set */
        /* cursor updates */
@@ -1063,6 +1058,11 @@ struct intel_fbc {
        bool underrun_detected;
        struct work_struct underrun_work;
 
+       /*
+        * Due to the atomic rules we can't access some structures without the
+        * appropriate locking, so we cache information here in order to avoid
+        * these problems.
+        */
        struct intel_fbc_state_cache {
                struct i915_vma *vma;
 
@@ -1084,6 +1084,13 @@ struct intel_fbc {
                } fb;
        } state_cache;
 
+       /*
+        * This structure contains everything that's relevant to program the
+        * hardware registers. When we want to figure out if we need to disable
+        * and re-enable FBC for a new configuration we just check if there's
+        * something different in the struct. The genx_fbc_activate functions
+        * are supposed to read from it in order to program the registers.
+        */
        struct intel_fbc_reg_params {
                struct i915_vma *vma;
 
@@ -1159,8 +1166,8 @@ enum intel_pch {
        PCH_CPT,        /* Cougarpoint/Pantherpoint PCH */
        PCH_LPT,        /* Lynxpoint/Wildcatpoint PCH */
        PCH_SPT,        /* Sunrisepoint PCH */
-       PCH_KBP,        /* Kabypoint PCH */
-       PCH_CNP,        /* Cannonpoint PCH */
+       PCH_KBP,        /* Kaby Lake PCH */
+       PCH_CNP,        /* Cannon Lake PCH */
        PCH_NOP,
 };
 
@@ -1388,12 +1395,23 @@ struct i915_power_well {
        bool hw_enabled;
        u64 domains;
        /* unique identifier for this power well */
-       unsigned long id;
+       enum i915_power_well_id id;
        /*
         * Arbitraty data associated with this power well. Platform and power
         * well specific.
         */
-       unsigned long data;
+       union {
+               struct {
+                       enum dpio_phy phy;
+               } bxt;
+               struct {
+                       /* Mask of pipes whose IRQ logic is backed by the pw */
+                       u8 irq_pipe_mask;
+                       /* The pw is backing the VGA functionality */
+                       bool has_vga:1;
+                       bool has_fuses:1;
+               } hsw;
+       };
        const struct i915_power_well_ops *ops;
 };
 
@@ -1903,6 +1921,24 @@ struct i915_oa_reg {
        u32 value;
 };
 
+struct i915_oa_config {
+       char uuid[UUID_STRING_LEN + 1];
+       int id;
+
+       const struct i915_oa_reg *mux_regs;
+       u32 mux_regs_len;
+       const struct i915_oa_reg *b_counter_regs;
+       u32 b_counter_regs_len;
+       const struct i915_oa_reg *flex_regs;
+       u32 flex_regs_len;
+
+       struct attribute_group sysfs_metric;
+       struct attribute *attrs[2];
+       struct device_attribute sysfs_metric_id;
+
+       atomic_t ref_count;
+};
+
 struct i915_perf_stream;
 
 /**
@@ -2015,12 +2051,36 @@ struct i915_perf_stream {
         * type of configured stream.
         */
        const struct i915_perf_stream_ops *ops;
+
+       /**
+        * @oa_config: The OA configuration used by the stream.
+        */
+       struct i915_oa_config *oa_config;
 };
 
 /**
  * struct i915_oa_ops - Gen specific implementation of an OA unit stream
  */
 struct i915_oa_ops {
+       /**
+        * @is_valid_b_counter_reg: Validates register's address for
+        * programming boolean counters for a particular platform.
+        */
+       bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
+                                      u32 addr);
+
+       /**
+        * @is_valid_mux_reg: Validates register's address for programming mux
+        * for a particular platform.
+        */
+       bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
+
+       /**
+        * @is_valid_flex_reg: Validates register's address for programming
+        * flex EU filtering for a particular platform.
+        */
+       bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
+
        /**
         * @init_oa_buffer: Resets the head and tail pointers of the
         * circular buffer for periodic OA reports.
@@ -2038,21 +2098,14 @@ struct i915_oa_ops {
         */
        void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
 
-       /**
-        * @select_metric_set: The auto generated code that checks whether a
-        * requested OA config is applicable to the system and if so sets up
-        * the mux, oa and flex eu register config pointers according to the
-        * current dev_priv->perf.oa.metrics_set.
-        */
-       int (*select_metric_set)(struct drm_i915_private *dev_priv);
-
        /**
         * @enable_metric_set: Selects and applies any MUX configuration to set
         * up the Boolean and Custom (B/C) counters that are part of the
         * counter reports being sampled. May apply system constraints such as
         * disabling EU clock gating as required.
         */
-       int (*enable_metric_set)(struct drm_i915_private *dev_priv);
+       int (*enable_metric_set)(struct drm_i915_private *dev_priv,
+                                const struct i915_oa_config *oa_config);
 
        /**
         * @disable_metric_set: Remove system constraints associated with using
@@ -2148,9 +2201,6 @@ struct drm_i915_private {
        /* protects the irq masks */
        spinlock_t irq_lock;
 
-       /* protects the mmio flip data */
-       spinlock_t mmio_flip_lock;
-
        bool display_irqs_enabled;
 
        /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
@@ -2255,7 +2305,6 @@ struct drm_i915_private {
 
        struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
        struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
-       wait_queue_head_t pending_flip_queue;
 
 #ifdef CONFIG_DEBUG_FS
        struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
@@ -2416,10 +2465,32 @@ struct drm_i915_private {
                struct kobject *metrics_kobj;
                struct ctl_table_header *sysctl_header;
 
+               /*
+                * Lock associated with adding/modifying/removing OA configs
+                * in dev_priv->perf.metrics_idr.
+                */
+               struct mutex metrics_lock;
+
+               /*
+                * List of dynamic configurations, you need to hold
+                * dev_priv->perf.metrics_lock to access it.
+                */
+               struct idr metrics_idr;
+
+               /*
+                * Lock associated with anything below within this structure
+                * except exclusive_stream.
+                */
                struct mutex lock;
                struct list_head streams;
 
                struct {
+                       /*
+                        * The stream currently using the OA unit. If accessed
+                        * outside a syscall associated to its file
+                        * descriptor, you need to hold
+                        * dev_priv->drm.struct_mutex.
+                        */
                        struct i915_perf_stream *exclusive_stream;
 
                        u32 specific_ctx_id;
@@ -2438,16 +2509,7 @@ struct drm_i915_private {
                        int period_exponent;
                        int timestamp_frequency;
 
-                       int metrics_set;
-
-                       const struct i915_oa_reg *mux_regs[6];
-                       int mux_regs_lens[6];
-                       int n_mux_configs;
-
-                       const struct i915_oa_reg *b_counter_regs;
-                       int b_counter_regs_len;
-                       const struct i915_oa_reg *flex_regs;
-                       int flex_regs_len;
+                       struct i915_oa_config test_config;
 
                        struct {
                                struct i915_vma *vma;
@@ -2534,7 +2596,6 @@ struct drm_i915_private {
 
                        struct i915_oa_ops ops;
                        const struct i915_oa_format *oa_formats;
-                       int n_builtin_sets;
                } oa;
        } perf;
 
@@ -3108,8 +3169,12 @@ extern int i915_driver_load(struct pci_dev *pdev,
 extern void i915_driver_unload(struct drm_device *dev);
 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
-extern void i915_reset(struct drm_i915_private *dev_priv);
-extern int i915_reset_engine(struct intel_engine_cs *engine);
+
+#define I915_RESET_QUIET BIT(0)
+extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
+extern int i915_reset_engine(struct intel_engine_cs *engine,
+                            unsigned int flags);
+
 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
@@ -3298,6 +3363,26 @@ static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
        } while (flush_work(&i915->mm.free_work));
 }
 
+static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
+{
+       /*
+        * Similar to objects above (see i915_gem_drain_freed-objects), in
+        * general we have workers that are armed by RCU and then rearm
+        * themselves in their callbacks. To be paranoid, we need to
+        * drain the workqueue a second time after waiting for the RCU
+        * grace period so that we catch work queued via RCU from the first
+        * pass. As neither drain_workqueue() nor flush_workqueue() report
+        * a result, we make an assumption that we only don't require more
+        * than 2 passes to catch all recursive RCU delayed work.
+        *
+        */
+       int pass = 2;
+       do {
+               rcu_barrier();
+               drain_workqueue(i915->wq);
+       } while (--pass);
+}
+
 struct i915_vma * __must_check
 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
                         const struct i915_ggtt_view *view,
@@ -3595,6 +3680,10 @@ i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
 
 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
                         struct drm_file *file);
+int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
+                              struct drm_file *file);
+int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
+                                 struct drm_file *file);
 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
                            struct i915_gem_context *ctx,
                            uint32_t *reg_state);
index d6f9b4c..000a764 100644 (file)
@@ -561,46 +561,6 @@ static struct intel_rps_client *to_rps_client(struct drm_file *file)
        return &fpriv->rps;
 }
 
-int
-i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
-                           int align)
-{
-       int ret;
-
-       if (align > obj->base.size)
-               return -EINVAL;
-
-       if (obj->ops == &i915_gem_phys_ops)
-               return 0;
-
-       if (obj->mm.madv != I915_MADV_WILLNEED)
-               return -EFAULT;
-
-       if (obj->base.filp == NULL)
-               return -EINVAL;
-
-       ret = i915_gem_object_unbind(obj);
-       if (ret)
-               return ret;
-
-       __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
-       if (obj->mm.pages)
-               return -EBUSY;
-
-       GEM_BUG_ON(obj->ops != &i915_gem_object_ops);
-       obj->ops = &i915_gem_phys_ops;
-
-       ret = i915_gem_object_pin_pages(obj);
-       if (ret)
-               goto err_xfer;
-
-       return 0;
-
-err_xfer:
-       obj->ops = &i915_gem_object_ops;
-       return ret;
-}
-
 static int
 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
                     struct drm_i915_gem_pwrite *args,
@@ -2740,34 +2700,38 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj,
        return 0;
 }
 
-static bool ban_context(const struct i915_gem_context *ctx)
+static bool ban_context(const struct i915_gem_context *ctx,
+                       unsigned int score)
 {
        return (i915_gem_context_is_bannable(ctx) &&
-               ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD);
+               score >= CONTEXT_SCORE_BAN_THRESHOLD);
 }
 
 static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
 {
-       ctx->guilty_count++;
-       ctx->ban_score += CONTEXT_SCORE_GUILTY;
-       if (ban_context(ctx))
-               i915_gem_context_set_banned(ctx);
+       unsigned int score;
+       bool banned;
 
-       DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
-                        ctx->name, ctx->ban_score,
-                        yesno(i915_gem_context_is_banned(ctx)));
+       atomic_inc(&ctx->guilty_count);
 
-       if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv))
+       score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score);
+       banned = ban_context(ctx, score);
+       DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
+                        ctx->name, score, yesno(banned));
+       if (!banned)
                return;
 
-       ctx->file_priv->context_bans++;
-       DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
-                        ctx->name, ctx->file_priv->context_bans);
+       i915_gem_context_set_banned(ctx);
+       if (!IS_ERR_OR_NULL(ctx->file_priv)) {
+               atomic_inc(&ctx->file_priv->context_bans);
+               DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
+                                ctx->name, atomic_read(&ctx->file_priv->context_bans));
+       }
 }
 
 static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx)
 {
-       ctx->active_count++;
+       atomic_inc(&ctx->active_count);
 }
 
 struct drm_i915_gem_request *
@@ -2850,11 +2814,9 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
        if (engine->irq_seqno_barrier)
                engine->irq_seqno_barrier(engine);
 
-       if (engine_stalled(engine)) {
-               request = i915_gem_find_active_request(engine);
-               if (request && request->fence.error == -EIO)
-                       request = ERR_PTR(-EIO); /* Previous reset failed! */
-       }
+       request = i915_gem_find_active_request(engine);
+       if (request && request->fence.error == -EIO)
+               request = ERR_PTR(-EIO); /* Previous reset failed! */
 
        return request;
 }
@@ -2923,12 +2885,11 @@ static void engine_skip_context(struct drm_i915_gem_request *request)
        spin_unlock_irqrestore(&engine->timeline->lock, flags);
 }
 
-/* Returns true if the request was guilty of hang */
-static bool i915_gem_reset_request(struct drm_i915_gem_request *request)
+/* Returns the request if it was guilty of the hang */
+static struct drm_i915_gem_request *
+i915_gem_reset_request(struct intel_engine_cs *engine,
+                      struct drm_i915_gem_request *request)
 {
-       /* Read once and return the resolution */
-       const bool guilty = !i915_gem_request_completed(request);
-
        /* The guilty request will get skipped on a hung engine.
         *
         * Users of client default contexts do not rely on logical
@@ -2950,27 +2911,47 @@ static bool i915_gem_reset_request(struct drm_i915_gem_request *request)
         * subsequent hangs.
         */
 
-       if (guilty) {
+       if (engine_stalled(engine)) {
                i915_gem_context_mark_guilty(request->ctx);
                skip_request(request);
+
+               /* If this context is now banned, skip all pending requests. */
+               if (i915_gem_context_is_banned(request->ctx))
+                       engine_skip_context(request);
        } else {
-               i915_gem_context_mark_innocent(request->ctx);
-               dma_fence_set_error(&request->fence, -EAGAIN);
+               /*
+                * Since this is not the hung engine, it may have advanced
+                * since the hang declaration. Double check by refinding
+                * the active request at the time of the reset.
+                */
+               request = i915_gem_find_active_request(engine);
+               if (request) {
+                       i915_gem_context_mark_innocent(request->ctx);
+                       dma_fence_set_error(&request->fence, -EAGAIN);
+
+                       /* Rewind the engine to replay the incomplete rq */
+                       spin_lock_irq(&engine->timeline->lock);
+                       request = list_prev_entry(request, link);
+                       if (&request->link == &engine->timeline->requests)
+                               request = NULL;
+                       spin_unlock_irq(&engine->timeline->lock);
+               }
        }
 
-       return guilty;
+       return request;
 }
 
 void i915_gem_reset_engine(struct intel_engine_cs *engine,
                           struct drm_i915_gem_request *request)
 {
-       if (request && i915_gem_reset_request(request)) {
+       engine->irq_posted = 0;
+
+       if (request)
+               request = i915_gem_reset_request(engine, request);
+
+       if (request) {
                DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
                                 engine->name, request->global_seqno);
-
-               /* If this context is now banned, skip all pending requests. */
-               if (i915_gem_context_is_banned(request->ctx))
-                       engine_skip_context(request);
        }
 
        /* Setup the CS to resume from the breadcrumb of the hung request */
@@ -3026,6 +3007,7 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
 
 static void nop_submit_request(struct drm_i915_gem_request *request)
 {
+       GEM_BUG_ON(!i915_terminally_wedged(&request->i915->gpu_error));
        dma_fence_set_error(&request->fence, -EIO);
        i915_gem_request_submit(request);
        intel_engine_init_global_seqno(request->engine, request->global_seqno);
@@ -3051,13 +3033,6 @@ static void engine_set_wedged(struct intel_engine_cs *engine)
                        dma_fence_set_error(&request->fence, -EIO);
        spin_unlock_irqrestore(&engine->timeline->lock, flags);
 
-       /* Mark all pending requests as complete so that any concurrent
-        * (lockless) lookup doesn't try and wait upon the request as we
-        * reset it.
-        */
-       intel_engine_init_global_seqno(engine,
-                                      intel_engine_last_submit(engine));
-
        /*
         * Clear the execlists queue up before freeing the requests, as those
         * are the ones that keep the context and ringbuffer backing objects
@@ -3086,6 +3061,13 @@ static void engine_set_wedged(struct intel_engine_cs *engine)
                 */
                clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
        }
+
+       /* Mark all pending requests as complete so that any concurrent
+        * (lockless) lookup doesn't try and wait upon the request as we
+        * reset it.
+        */
+       intel_engine_init_global_seqno(engine,
+                                      intel_engine_last_submit(engine));
 }
 
 static int __i915_gem_set_wedged_BKL(void *data)
@@ -3094,10 +3076,12 @@ static int __i915_gem_set_wedged_BKL(void *data)
        struct intel_engine_cs *engine;
        enum intel_engine_id id;
 
-       set_bit(I915_WEDGED, &i915->gpu_error.flags);
        for_each_engine(engine, i915, id)
                engine_set_wedged(engine);
 
+       set_bit(I915_WEDGED, &i915->gpu_error.flags);
+       wake_up_all(&i915->gpu_error.reset_queue);
+
        return 0;
 }
 
@@ -4936,8 +4920,6 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
        init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
        init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
 
-       init_waitqueue_head(&dev_priv->pending_flip_queue);
-
        atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
 
        spin_lock_init(&dev_priv->fb_tracking.lock);
@@ -5304,6 +5286,64 @@ i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
        return sg_dma_address(sg) + (offset << PAGE_SHIFT);
 }
 
+int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
+{
+       struct sg_table *pages;
+       int err;
+
+       if (align > obj->base.size)
+               return -EINVAL;
+
+       if (obj->ops == &i915_gem_phys_ops)
+               return 0;
+
+       if (obj->ops != &i915_gem_object_ops)
+               return -EINVAL;
+
+       err = i915_gem_object_unbind(obj);
+       if (err)
+               return err;
+
+       mutex_lock(&obj->mm.lock);
+
+       if (obj->mm.madv != I915_MADV_WILLNEED) {
+               err = -EFAULT;
+               goto err_unlock;
+       }
+
+       if (obj->mm.quirked) {
+               err = -EFAULT;
+               goto err_unlock;
+       }
+
+       if (obj->mm.mapping) {
+               err = -EBUSY;
+               goto err_unlock;
+       }
+
+       pages = obj->mm.pages;
+       obj->ops = &i915_gem_phys_ops;
+
+       err = ____i915_gem_object_get_pages(obj);
+       if (err)
+               goto err_xfer;
+
+       /* Perma-pin (until release) the physical set of pages */
+       __i915_gem_object_pin_pages(obj);
+
+       if (!IS_ERR_OR_NULL(pages))
+               i915_gem_object_ops.put_pages(obj, pages);
+       mutex_unlock(&obj->mm.lock);
+       return 0;
+
+err_xfer:
+       obj->ops = &i915_gem_object_ops;
+       obj->mm.pages = pages;
+err_unlock:
+       mutex_unlock(&obj->mm.lock);
+       return err;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/scatterlist.c"
 #include "selftests/mock_gem_device.c"
index 152f16c..348b29a 100644 (file)
@@ -114,7 +114,7 @@ i915_clflush_notify(struct i915_sw_fence *fence,
        return NOTIFY_DONE;
 }
 
-void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
+bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
                             unsigned int flags)
 {
        struct clflush *clflush;
@@ -128,7 +128,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
         */
        if (!i915_gem_object_has_struct_page(obj)) {
                obj->cache_dirty = false;
-               return;
+               return false;
        }
 
        /* If the GPU is snooping the contents of the CPU cache,
@@ -140,7 +140,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
         * tracking.
         */
        if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent)
-               return;
+               return false;
 
        trace_i915_gem_object_clflush(obj);
 
@@ -179,4 +179,5 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
        }
 
        obj->cache_dirty = false;
+       return true;
 }
index 2455a78..f390247 100644 (file)
@@ -28,7 +28,7 @@
 struct drm_i915_private;
 struct drm_i915_gem_object;
 
-void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
+bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
                             unsigned int flags);
 #define I915_CLFLUSH_FORCE BIT(0)
 #define I915_CLFLUSH_SYNC BIT(1)
index 1a87d04..ed91ac8 100644 (file)
@@ -977,7 +977,7 @@ int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
 
 static bool client_is_banned(struct drm_i915_file_private *file_priv)
 {
-       return file_priv->context_bans > I915_MAX_CLIENT_CONTEXT_BANS;
+       return atomic_read(&file_priv->context_bans) > I915_MAX_CLIENT_CONTEXT_BANS;
 }
 
 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
@@ -1179,8 +1179,8 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
        else
                args->reset_count = 0;
 
-       args->batch_active = READ_ONCE(ctx->guilty_count);
-       args->batch_pending = READ_ONCE(ctx->active_count);
+       args->batch_active = atomic_read(&ctx->guilty_count);
+       args->batch_pending = atomic_read(&ctx->active_count);
 
        ret = 0;
 out:
index 04320f8..2d02918 100644 (file)
@@ -191,17 +191,17 @@ struct i915_gem_context {
        u32 desc_template;
 
        /** guilty_count: How many times this context has caused a GPU hang. */
-       unsigned int guilty_count;
+       atomic_t guilty_count;
        /**
         * @active_count: How many times this context was active during a GPU
         * hang, but did not cause it.
         */
-       unsigned int active_count;
+       atomic_t active_count;
 
 #define CONTEXT_SCORE_GUILTY           10
 #define CONTEXT_SCORE_BAN_THRESHOLD    40
        /** ban_score: Accumulated score of all hangs caused by this context. */
-       int ban_score;
+       atomic_t ban_score;
 
        /** remap_slice: Bitmask of cache lines that need remapping */
        u8 remap_slice;
index 929f275..5fa4476 100644 (file)
@@ -560,9 +560,6 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb,
                eb->args->flags |= __EXEC_HAS_RELOC;
        }
 
-       entry->flags |= __EXEC_OBJECT_HAS_PIN;
-       GEM_BUG_ON(eb_vma_misplaced(entry, vma));
-
        if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) {
                err = i915_vma_get_fence(vma);
                if (unlikely(err)) {
@@ -574,6 +571,9 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb,
                        entry->flags |= __EXEC_OBJECT_HAS_FENCE;
        }
 
+       entry->flags |= __EXEC_OBJECT_HAS_PIN;
+       GEM_BUG_ON(eb_vma_misplaced(entry, vma));
+
        return 0;
 }
 
@@ -1459,7 +1459,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
         * to read. However, if the array is not writable the user loses
         * the updated relocation values.
         */
-       if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(urelocs))))
+       if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(*urelocs))))
                return -EFAULT;
 
        do {
@@ -1776,7 +1776,7 @@ out:
                }
        }
 
-       return err ?: have_copy;
+       return err;
 }
 
 static int eb_relocate(struct i915_execbuffer *eb)
@@ -1826,7 +1826,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
        int err;
 
        for (i = 0; i < count; i++) {
-               const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
+               struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
                struct i915_vma *vma = exec_to_vma(entry);
                struct drm_i915_gem_object *obj = vma->obj;
 
@@ -1842,12 +1842,14 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
                        eb->request->capture_list = capture;
                }
 
+               if (unlikely(obj->cache_dirty && !obj->cache_coherent)) {
+                       if (i915_gem_clflush_object(obj, 0))
+                               entry->flags &= ~EXEC_OBJECT_ASYNC;
+               }
+
                if (entry->flags & EXEC_OBJECT_ASYNC)
                        goto skip_flushes;
 
-               if (unlikely(obj->cache_dirty && !obj->cache_coherent))
-                       i915_gem_clflush_object(obj, 0);
-
                err = i915_gem_request_await_object
                        (eb->request, obj, entry->flags & EXEC_OBJECT_WRITE);
                if (err)
@@ -2210,7 +2212,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
                goto err_rpm;
 
        err = eb_relocate(&eb);
-       if (err)
+       if (err) {
                /*
                 * If the user expects the execobject.offset and
                 * reloc.presumed_offset to be an exact match,
@@ -2219,8 +2221,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
                 * relocation.
                 */
                args->flags &= ~__EXEC_HAS_RELOC;
-       if (err < 0)
                goto err_vma;
+       }
 
        if (unlikely(eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE)) {
                DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
index 7032c54..4dd4c21 100644 (file)
@@ -242,6 +242,10 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request *req)
                        goto err_unpin;
        }
 
+       ret = req->engine->emit_flush(req, EMIT_INVALIDATE);
+       if (ret)
+               goto err_unpin;
+
        ret = req->engine->emit_bb_start(req,
                                         so->batch_offset, so->batch_size,
                                         I915_DISPATCH_SECURE);
index 483af89..9eedd33 100644 (file)
@@ -213,6 +213,10 @@ static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno)
                                cond_resched();
                }
 
+               /* Check we are idle before we fiddle with hw state! */
+               GEM_BUG_ON(!intel_engine_is_idle(engine));
+               GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request));
+
                /* Finally reset hw state */
                intel_engine_init_global_seqno(engine, seqno);
                tl->seqno = seqno;
@@ -370,8 +374,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
        i915_gem_request_remove_from_client(request);
 
        /* Retirement decays the ban score as it is a sign of ctx progress */
-       if (request->ctx->ban_score > 0)
-               request->ctx->ban_score--;
+       atomic_dec_if_positive(&request->ctx->ban_score);
 
        /* The backing object for the context is done after switching to the
         * *next* context. Therefore we cannot retire the previous context until
@@ -1068,7 +1071,7 @@ static bool __i915_wait_request_check_and_reset(struct drm_i915_gem_request *req
                return false;
 
        __set_current_state(TASK_RUNNING);
-       i915_reset(request->i915);
+       i915_reset(request->i915, 0);
        return true;
 }
 
index 1032f98..77fb398 100644 (file)
@@ -43,16 +43,21 @@ static bool shrinker_lock(struct drm_i915_private *dev_priv, bool *unlock)
                return true;
 
        case MUTEX_TRYLOCK_FAILED:
+               *unlock = false;
+               preempt_disable();
                do {
                        cpu_relax();
                        if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
-       case MUTEX_TRYLOCK_SUCCESS:
                                *unlock = true;
-                               return true;
+                               break;
                        }
                } while (!need_resched());
+               preempt_enable();
+               return *unlock;
 
-               return false;
+       case MUTEX_TRYLOCK_SUCCESS:
+               *unlock = true;
+               return true;
        }
 
        BUG();
index a817b3e..c11c915 100644 (file)
@@ -254,9 +254,10 @@ static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv)
                 * This is a BIOS w/a: Some BIOS wrap stolen in the root
                 * PCI bus, but have an off-by-one error. Hence retry the
                 * reservation starting from 1 instead of 0.
+                * There's also BIOS with off-by-one on the other end.
                 */
                r = devm_request_mem_region(dev_priv->drm.dev, base + 1,
-                                           ggtt->stolen_size - 1,
+                                           ggtt->stolen_size - 2,
                                            "Graphics Stolen Memory");
                /*
                 * GEN3 firmware likes to smash pci bridges into the stolen
index ae70283..ed5a1eb 100644 (file)
@@ -1266,7 +1266,7 @@ static void record_request(struct drm_i915_gem_request *request,
                           struct drm_i915_error_request *erq)
 {
        erq->context = request->ctx->hw_id;
-       erq->ban_score = request->ctx->ban_score;
+       erq->ban_score = atomic_read(&request->ctx->ban_score);
        erq->seqno = request->global_seqno;
        erq->jiffies = request->emitted_jiffies;
        erq->head = request->head;
@@ -1357,9 +1357,9 @@ static void record_context(struct drm_i915_error_context *e,
 
        e->handle = ctx->user_handle;
        e->hw_id = ctx->hw_id;
-       e->ban_score = ctx->ban_score;
-       e->guilty = ctx->guilty_count;
-       e->active = ctx->active_count;
+       e->ban_score = atomic_read(&ctx->ban_score);
+       e->guilty = atomic_read(&ctx->guilty_count);
+       e->active = atomic_read(&ctx->active_count);
 }
 
 static void request_record_user_bo(struct drm_i915_gem_request *request,
index eb4f1dc..196caa4 100644 (file)
@@ -275,17 +275,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 
 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 {
-       return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
+       return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 }
 
 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 {
-       return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
+       return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 }
 
 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 {
-       return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
+       return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 }
 
 /**
@@ -1661,7 +1661,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
                spin_unlock(&dev_priv->irq_lock);
        }
 
-       if (INTEL_INFO(dev_priv)->gen >= 8)
+       if (INTEL_GEN(dev_priv) >= 8)
                return;
 
        if (HAS_VEBOX(dev_priv)) {
@@ -1708,18 +1708,6 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
        }
 }
 
-static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
-                                    enum pipe pipe)
-{
-       bool ret;
-
-       ret = drm_handle_vblank(&dev_priv->drm, pipe);
-       if (ret)
-               intel_finish_page_flip_mmio(dev_priv, pipe);
-
-       return ret;
-}
-
 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
                                        u32 iir, u32 pipe_stats[I915_MAX_PIPES])
 {
@@ -1784,12 +1772,8 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
        enum pipe pipe;
 
        for_each_pipe(dev_priv, pipe) {
-               if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
-                   intel_pipe_handle_vblank(dev_priv, pipe))
-                       intel_check_page_flip(dev_priv, pipe);
-
-               if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
-                       intel_finish_page_flip_cs(dev_priv, pipe);
+               if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
+                       drm_handle_vblank(&dev_priv->drm, pipe);
 
                if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
                        i9xx_pipe_crc_irq_handler(dev_priv, pipe);
@@ -2086,10 +2070,10 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
                DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 
        if (pch_iir & SDE_TRANSA_FIFO_UNDER)
-               intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
+               intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
 
        if (pch_iir & SDE_TRANSB_FIFO_UNDER)
-               intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
+               intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
 }
 
 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
@@ -2123,13 +2107,13 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
                DRM_ERROR("PCH poison interrupt\n");
 
        if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
-               intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
+               intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
 
        if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
-               intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
+               intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
 
        if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
-               intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
+               intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C);
 
        I915_WRITE(SERR_INT, serr_int);
 }
@@ -2241,19 +2225,14 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
                DRM_ERROR("Poison interrupt\n");
 
        for_each_pipe(dev_priv, pipe) {
-               if (de_iir & DE_PIPE_VBLANK(pipe) &&
-                   intel_pipe_handle_vblank(dev_priv, pipe))
-                       intel_check_page_flip(dev_priv, pipe);
+               if (de_iir & DE_PIPE_VBLANK(pipe))
+                       drm_handle_vblank(&dev_priv->drm, pipe);
 
                if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
                        intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
 
                if (de_iir & DE_PIPE_CRC_DONE(pipe))
                        i9xx_pipe_crc_irq_handler(dev_priv, pipe);
-
-               /* plane/pipes map 1:1 on ilk+ */
-               if (de_iir & DE_PLANE_FLIP_DONE(pipe))
-                       intel_finish_page_flip_cs(dev_priv, pipe);
        }
 
        /* check event from PCH */
@@ -2292,13 +2271,8 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
                intel_opregion_asle_intr(dev_priv);
 
        for_each_pipe(dev_priv, pipe) {
-               if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
-                   intel_pipe_handle_vblank(dev_priv, pipe))
-                       intel_check_page_flip(dev_priv, pipe);
-
-               /* plane/pipes map 1:1 on ilk+ */
-               if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
-                       intel_finish_page_flip_cs(dev_priv, pipe);
+               if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
+                       drm_handle_vblank(&dev_priv->drm, pipe);
        }
 
        /* check event from PCH */
@@ -2440,7 +2414,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
                        ret = IRQ_HANDLED;
 
                        tmp_mask = GEN8_AUX_CHANNEL_A;
-                       if (INTEL_INFO(dev_priv)->gen >= 9)
+                       if (INTEL_GEN(dev_priv) >= 9)
                                tmp_mask |= GEN9_AUX_CHANNEL_B |
                                            GEN9_AUX_CHANNEL_C |
                                            GEN9_AUX_CHANNEL_D;
@@ -2479,7 +2453,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
        }
 
        for_each_pipe(dev_priv, pipe) {
-               u32 flip_done, fault_errors;
+               u32 fault_errors;
 
                if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
                        continue;
@@ -2493,18 +2467,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
                ret = IRQ_HANDLED;
                I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
 
-               if (iir & GEN8_PIPE_VBLANK &&
-                   intel_pipe_handle_vblank(dev_priv, pipe))
-                       intel_check_page_flip(dev_priv, pipe);
-
-               flip_done = iir;
-               if (INTEL_INFO(dev_priv)->gen >= 9)
-                       flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
-               else
-                       flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
-
-               if (flip_done)
-                       intel_finish_page_flip_cs(dev_priv, pipe);
+               if (iir & GEN8_PIPE_VBLANK)
+                       drm_handle_vblank(&dev_priv->drm, pipe);
 
                if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
                        hsw_pipe_crc_irq_handler(dev_priv, pipe);
@@ -2513,7 +2477,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
                        intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
 
                fault_errors = iir;
-               if (INTEL_INFO(dev_priv)->gen >= 9)
+               if (INTEL_GEN(dev_priv) >= 9)
                        fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
                else
                        fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
@@ -2660,7 +2624,7 @@ static void i915_reset_device(struct drm_i915_private *dev_priv)
                 */
                do {
                        if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
-                               i915_reset(dev_priv);
+                               i915_reset(dev_priv, 0);
                                mutex_unlock(&dev_priv->drm.struct_mutex);
                        }
                } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
@@ -2676,32 +2640,6 @@ static void i915_reset_device(struct drm_i915_private *dev_priv)
                                   KOBJ_CHANGE, reset_done_event);
 }
 
-static inline void
-i915_err_print_instdone(struct drm_i915_private *dev_priv,
-                       struct intel_instdone *instdone)
-{
-       int slice;
-       int subslice;
-
-       pr_err("  INSTDONE: 0x%08x\n", instdone->instdone);
-
-       if (INTEL_GEN(dev_priv) <= 3)
-               return;
-
-       pr_err("  SC_INSTDONE: 0x%08x\n", instdone->slice_common);
-
-       if (INTEL_GEN(dev_priv) <= 6)
-               return;
-
-       for_each_instdone_slice_subslice(dev_priv, slice, subslice)
-               pr_err("  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
-                      slice, subslice, instdone->sampler[slice][subslice]);
-
-       for_each_instdone_slice_subslice(dev_priv, slice, subslice)
-               pr_err("  ROW_INSTDONE[%d][%d]: 0x%08x\n",
-                      slice, subslice, instdone->row[slice][subslice]);
-}
-
 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
 {
        u32 eir;
@@ -2775,7 +2713,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
                                             &dev_priv->gpu_error.flags))
                                continue;
 
-                       if (i915_reset_engine(engine) == 0)
+                       if (i915_reset_engine(engine, 0) == 0)
                                engine_mask &= ~intel_engine_flag(engine);
 
                        clear_bit(I915_RESET_ENGINE + engine->id,
@@ -3074,7 +3012,7 @@ static void gen8_irq_reset(struct drm_device *dev)
 }
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
-                                    unsigned int pipe_mask)
+                                    u8 pipe_mask)
 {
        uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
        enum pipe pipe;
@@ -3088,7 +3026,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 }
 
 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
-                                    unsigned int pipe_mask)
+                                    u8 pipe_mask)
 {
        enum pipe pipe;
 
@@ -3492,7 +3430,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
        u32 de_misc_masked = GEN8_DE_MISC_GSE;
        enum pipe pipe;
 
-       if (INTEL_INFO(dev_priv)->gen >= 9) {
+       if (INTEL_GEN(dev_priv) >= 9) {
                de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
                                  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
                de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
@@ -3675,34 +3613,6 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
 /*
  * Returns true when a page flip has completed.
  */
-static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
-                              int plane, int pipe, u32 iir)
-{
-       u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
-
-       if (!intel_pipe_handle_vblank(dev_priv, pipe))
-               return false;
-
-       if ((iir & flip_pending) == 0)
-               goto check_page_flip;
-
-       /* We detect FlipDone by looking for the change in PendingFlip from '1'
-        * to '0' on the following vblank, i.e. IIR has the Pendingflip
-        * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
-        * the flip is completed (no longer pending). Since this doesn't raise
-        * an interrupt per se, we watch for the change at vblank.
-        */
-       if (I915_READ16(ISR) & flip_pending)
-               goto check_page_flip;
-
-       intel_finish_page_flip_cs(dev_priv, pipe);
-       return true;
-
-check_page_flip:
-       intel_check_page_flip(dev_priv, pipe);
-       return false;
-}
-
 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
 {
        struct drm_device *dev = arg;
@@ -3710,9 +3620,6 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
        u16 iir, new_iir;
        u32 pipe_stats[2];
        int pipe;
-       u16 flip_mask =
-               I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
-               I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
        irqreturn_t ret;
 
        if (!intel_irqs_enabled(dev_priv))
@@ -3726,7 +3633,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
        if (iir == 0)
                goto out;
 
-       while (iir & ~flip_mask) {
+       while (iir) {
                /* Can't rely on pipestat interrupt bit in iir as it might
                 * have been cleared after the pipestat interrupt was received.
                 * It doesn't set the bit in iir again, but it still produces
@@ -3748,7 +3655,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
                }
                spin_unlock(&dev_priv->irq_lock);
 
-               I915_WRITE16(IIR, iir & ~flip_mask);
+               I915_WRITE16(IIR, iir);
                new_iir = I915_READ16(IIR); /* Flush posted writes */
 
                if (iir & I915_USER_INTERRUPT)
@@ -3759,9 +3666,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
                        if (HAS_FBC(dev_priv))
                                plane = !plane;
 
-                       if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
-                           i8xx_handle_vblank(dev_priv, plane, pipe, iir))
-                               flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
+                       if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
+                               drm_handle_vblank(&dev_priv->drm, pipe);
 
                        if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
                                i9xx_pipe_crc_irq_handler(dev_priv, pipe);
@@ -3861,45 +3767,11 @@ static int i915_irq_postinstall(struct drm_device *dev)
        return 0;
 }
 
-/*
- * Returns true when a page flip has completed.
- */
-static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
-                              int plane, int pipe, u32 iir)
-{
-       u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
-
-       if (!intel_pipe_handle_vblank(dev_priv, pipe))
-               return false;
-
-       if ((iir & flip_pending) == 0)
-               goto check_page_flip;
-
-       /* We detect FlipDone by looking for the change in PendingFlip from '1'
-        * to '0' on the following vblank, i.e. IIR has the Pendingflip
-        * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
-        * the flip is completed (no longer pending). Since this doesn't raise
-        * an interrupt per se, we watch for the change at vblank.
-        */
-       if (I915_READ(ISR) & flip_pending)
-               goto check_page_flip;
-
-       intel_finish_page_flip_cs(dev_priv, pipe);
-       return true;
-
-check_page_flip:
-       intel_check_page_flip(dev_priv, pipe);
-       return false;
-}
-
 static irqreturn_t i915_irq_handler(int irq, void *arg)
 {
        struct drm_device *dev = arg;
        struct drm_i915_private *dev_priv = to_i915(dev);
        u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
-       u32 flip_mask =
-               I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
-               I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
        int pipe, ret = IRQ_NONE;
 
        if (!intel_irqs_enabled(dev_priv))
@@ -3910,7 +3782,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 
        iir = I915_READ(IIR);
        do {
-               bool irq_received = (iir & ~flip_mask) != 0;
+               bool irq_received = (iir) != 0;
                bool blc_event = false;
 
                /* Can't rely on pipestat interrupt bit in iir as it might
@@ -3945,7 +3817,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
                                i9xx_hpd_irq_handler(dev_priv, hotplug_status);
                }
 
-               I915_WRITE(IIR, iir & ~flip_mask);
+               I915_WRITE(IIR, iir);
                new_iir = I915_READ(IIR); /* Flush posted writes */
 
                if (iir & I915_USER_INTERRUPT)
@@ -3956,9 +3828,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
                        if (HAS_FBC(dev_priv))
                                plane = !plane;
 
-                       if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
-                           i915_handle_vblank(dev_priv, plane, pipe, iir))
-                               flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
+                       if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
+                               drm_handle_vblank(&dev_priv->drm, pipe);
 
                        if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
                                blc_event = true;
@@ -3991,7 +3862,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
                 */
                ret = IRQ_HANDLED;
                iir = new_iir;
-       } while (iir & ~flip_mask);
+       } while (iir);
 
        enable_rpm_wakeref_asserts(dev_priv);
 
@@ -4126,9 +3997,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
        u32 iir, new_iir;
        u32 pipe_stats[I915_MAX_PIPES];
        int ret = IRQ_NONE, pipe;
-       u32 flip_mask =
-               I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
-               I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
 
        if (!intel_irqs_enabled(dev_priv))
                return IRQ_NONE;
@@ -4139,7 +4007,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
        iir = I915_READ(IIR);
 
        for (;;) {
-               bool irq_received = (iir & ~flip_mask) != 0;
+               bool irq_received = (iir) != 0;
                bool blc_event = false;
 
                /* Can't rely on pipestat interrupt bit in iir as it might
@@ -4177,7 +4045,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
                                i9xx_hpd_irq_handler(dev_priv, hotplug_status);
                }
 
-               I915_WRITE(IIR, iir & ~flip_mask);
+               I915_WRITE(IIR, iir);
                new_iir = I915_READ(IIR); /* Flush posted writes */
 
                if (iir & I915_USER_INTERRUPT)
@@ -4186,9 +4054,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
                        notify_ring(dev_priv->engine[VCS]);
 
                for_each_pipe(dev_priv, pipe) {
-                       if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
-                           i915_handle_vblank(dev_priv, pipe, pipe, iir))
-                               flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
+                       if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
+                               drm_handle_vblank(&dev_priv->drm, pipe);
 
                        if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
                                blc_event = true;
@@ -4290,16 +4157,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
         *
         * TODO: verify if this can be reproduced on VLV,CHV.
         */
-       if (INTEL_INFO(dev_priv)->gen <= 7)
+       if (INTEL_GEN(dev_priv) <= 7)
                dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
 
-       if (INTEL_INFO(dev_priv)->gen >= 8)
+       if (INTEL_GEN(dev_priv) >= 8)
                dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 
        if (IS_GEN2(dev_priv)) {
                /* Gen2 doesn't have a hardware frame counter */
                dev->max_vblank_count = 0;
-       } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
+       } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
                dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
                dev->driver->get_vblank_counter = g4x_get_vblank_counter;
        } else {
@@ -4346,7 +4213,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
                dev->driver->enable_vblank = i965_enable_vblank;
                dev->driver->disable_vblank = i965_disable_vblank;
                dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
-       } else if (INTEL_INFO(dev_priv)->gen >= 8) {
+       } else if (INTEL_GEN(dev_priv) >= 8) {
                dev->driver->irq_handler = gen8_irq_handler;
                dev->driver->irq_preinstall = gen8_irq_reset;
                dev->driver->irq_postinstall = gen8_irq_postinstall;
index d4462c2..abdf4d0 100644 (file)
 #include "i915_drv.h"
 #include "i915_oa_bdw.h"
 
-enum metric_set_id {
-       METRIC_SET_ID_RENDER_BASIC = 1,
-       METRIC_SET_ID_COMPUTE_BASIC,
-       METRIC_SET_ID_RENDER_PIPE_PROFILE,
-       METRIC_SET_ID_MEMORY_READS,
-       METRIC_SET_ID_MEMORY_WRITES,
-       METRIC_SET_ID_COMPUTE_EXTENDED,
-       METRIC_SET_ID_COMPUTE_L3_CACHE,
-       METRIC_SET_ID_DATA_PORT_READS_COALESCING,
-       METRIC_SET_ID_DATA_PORT_WRITES_COALESCING,
-       METRIC_SET_ID_HDC_AND_SF,
-       METRIC_SET_ID_L3_1,
-       METRIC_SET_ID_L3_2,
-       METRIC_SET_ID_L3_3,
-       METRIC_SET_ID_L3_4,
-       METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
-       METRIC_SET_ID_SAMPLER_1,
-       METRIC_SET_ID_SAMPLER_2,
-       METRIC_SET_ID_TDL_1,
-       METRIC_SET_ID_TDL_2,
-       METRIC_SET_ID_COMPUTE_EXTRA,
-       METRIC_SET_ID_VME_PIPE,
-       METRIC_SET_ID_TEST_OA,
-};
-
-int i915_oa_n_builtin_metric_sets_bdw = 22;
-
-static const struct i915_oa_reg b_counter_config_render_basic[] = {
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0x00800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x00800000 },
-       { _MMIO(0x2740), 0x00000000 },
-};
-
-static const struct i915_oa_reg flex_eu_config_render_basic[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_render_basic_0_slices_0x01[] = {
-       { _MMIO(0x9888), 0x143f000f },
-       { _MMIO(0x9888), 0x14110014 },
-       { _MMIO(0x9888), 0x14310014 },
-       { _MMIO(0x9888), 0x14bf000f },
-       { _MMIO(0x9888), 0x118a0317 },
-       { _MMIO(0x9888), 0x13837be0 },
-       { _MMIO(0x9888), 0x3b800060 },
-       { _MMIO(0x9888), 0x3d800005 },
-       { _MMIO(0x9888), 0x005c4000 },
-       { _MMIO(0x9888), 0x065c8000 },
-       { _MMIO(0x9888), 0x085cc000 },
-       { _MMIO(0x9888), 0x003d8000 },
-       { _MMIO(0x9888), 0x183d0800 },
-       { _MMIO(0x9888), 0x0a3f0023 },
-       { _MMIO(0x9888), 0x103f0000 },
-       { _MMIO(0x9888), 0x00584000 },
-       { _MMIO(0x9888), 0x08584000 },
-       { _MMIO(0x9888), 0x0a5a4000 },
-       { _MMIO(0x9888), 0x005b4000 },
-       { _MMIO(0x9888), 0x0e5b8000 },
-       { _MMIO(0x9888), 0x185b2400 },
-       { _MMIO(0x9888), 0x0a1d4000 },
-       { _MMIO(0x9888), 0x0c1f0800 },
-       { _MMIO(0x9888), 0x0e1faa00 },
-       { _MMIO(0x9888), 0x00384000 },
-       { _MMIO(0x9888), 0x0e384000 },
-       { _MMIO(0x9888), 0x16384000 },
-       { _MMIO(0x9888), 0x18380001 },
-       { _MMIO(0x9888), 0x00392000 },
-       { _MMIO(0x9888), 0x06398000 },
-       { _MMIO(0x9888), 0x0839a000 },
-       { _MMIO(0x9888), 0x0a391000 },
-       { _MMIO(0x9888), 0x00104000 },
-       { _MMIO(0x9888), 0x08104000 },
-       { _MMIO(0x9888), 0x00110030 },
-       { _MMIO(0x9888), 0x08110031 },
-       { _MMIO(0x9888), 0x10110000 },
-       { _MMIO(0x9888), 0x00134000 },
-       { _MMIO(0x9888), 0x16130020 },
-       { _MMIO(0x9888), 0x06308000 },
-       { _MMIO(0x9888), 0x08308000 },
-       { _MMIO(0x9888), 0x06311800 },
-       { _MMIO(0x9888), 0x08311880 },
-       { _MMIO(0x9888), 0x10310000 },
-       { _MMIO(0x9888), 0x0e334000 },
-       { _MMIO(0x9888), 0x16330080 },
-       { _MMIO(0x9888), 0x0abf1180 },
-       { _MMIO(0x9888), 0x10bf0000 },
-       { _MMIO(0x9888), 0x0ada8000 },
-       { _MMIO(0x9888), 0x0a9d8000 },
-       { _MMIO(0x9888), 0x109f0002 },
-       { _MMIO(0x9888), 0x0ab94000 },
-       { _MMIO(0x9888), 0x0d888000 },
-       { _MMIO(0x9888), 0x038a0380 },
-       { _MMIO(0x9888), 0x058a000e },
-       { _MMIO(0x9888), 0x018a8000 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x198a8000 },
-       { _MMIO(0x9888), 0x1b8a00a0 },
-       { _MMIO(0x9888), 0x078a0000 },
-       { _MMIO(0x9888), 0x098a0000 },
-       { _MMIO(0x9888), 0x238b2820 },
-       { _MMIO(0x9888), 0x258b2550 },
-       { _MMIO(0x9888), 0x198c1000 },
-       { _MMIO(0x9888), 0x0b8d8000 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaa0 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x0d831021 },
-       { _MMIO(0x9888), 0x0f83572f },
-       { _MMIO(0x9888), 0x01835680 },
-       { _MMIO(0x9888), 0x0383002c },
-       { _MMIO(0x9888), 0x11830000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830001 },
-       { _MMIO(0x9888), 0x05830000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x05844000 },
-       { _MMIO(0x9888), 0x1b80c137 },
-       { _MMIO(0x9888), 0x1d80c147 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x17808000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x15804000 },
-       { _MMIO(0x9888), 0x4d801110 },
-       { _MMIO(0x9888), 0x4f800331 },
-       { _MMIO(0x9888), 0x43800802 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45801465 },
-       { _MMIO(0x9888), 0x53801111 },
-       { _MMIO(0x9888), 0x478014a5 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800ca5 },
-       { _MMIO(0x9888), 0x41800003 },
-};
-
-static const struct i915_oa_reg mux_config_render_basic_1_slices_0x02[] = {
-       { _MMIO(0x9888), 0x143f000f },
-       { _MMIO(0x9888), 0x14bf000f },
-       { _MMIO(0x9888), 0x14910014 },
-       { _MMIO(0x9888), 0x14b10014 },
-       { _MMIO(0x9888), 0x118a0317 },
-       { _MMIO(0x9888), 0x13837be0 },
-       { _MMIO(0x9888), 0x3b800060 },
-       { _MMIO(0x9888), 0x3d800005 },
-       { _MMIO(0x9888), 0x0a3f0023 },
-       { _MMIO(0x9888), 0x103f0000 },
-       { _MMIO(0x9888), 0x0a5a4000 },
-       { _MMIO(0x9888), 0x0a1d4000 },
-       { _MMIO(0x9888), 0x0e1f8000 },
-       { _MMIO(0x9888), 0x0a391000 },
-       { _MMIO(0x9888), 0x00dc4000 },
-       { _MMIO(0x9888), 0x06dc8000 },
-       { _MMIO(0x9888), 0x08dcc000 },
-       { _MMIO(0x9888), 0x00bd8000 },
-       { _MMIO(0x9888), 0x18bd0800 },
-       { _MMIO(0x9888), 0x0abf1180 },
-       { _MMIO(0x9888), 0x10bf0000 },
-       { _MMIO(0x9888), 0x00d84000 },
-       { _MMIO(0x9888), 0x08d84000 },
-       { _MMIO(0x9888), 0x0ada8000 },
-       { _MMIO(0x9888), 0x00db4000 },
-       { _MMIO(0x9888), 0x0edb8000 },
-       { _MMIO(0x9888), 0x18db2400 },
-       { _MMIO(0x9888), 0x0a9d8000 },
-       { _MMIO(0x9888), 0x0c9f0800 },
-       { _MMIO(0x9888), 0x0e9f2a00 },
-       { _MMIO(0x9888), 0x109f0002 },
-       { _MMIO(0x9888), 0x00b84000 },
-       { _MMIO(0x9888), 0x0eb84000 },
-       { _MMIO(0x9888), 0x16b84000 },
-       { _MMIO(0x9888), 0x18b80001 },
-       { _MMIO(0x9888), 0x00b92000 },
-       { _MMIO(0x9888), 0x06b98000 },
-       { _MMIO(0x9888), 0x08b9a000 },
-       { _MMIO(0x9888), 0x0ab94000 },
-       { _MMIO(0x9888), 0x00904000 },
-       { _MMIO(0x9888), 0x08904000 },
-       { _MMIO(0x9888), 0x00910030 },
-       { _MMIO(0x9888), 0x08910031 },
-       { _MMIO(0x9888), 0x10910000 },
-       { _MMIO(0x9888), 0x00934000 },
-       { _MMIO(0x9888), 0x16930020 },
-       { _MMIO(0x9888), 0x06b08000 },
-       { _MMIO(0x9888), 0x08b08000 },
-       { _MMIO(0x9888), 0x06b11800 },
-       { _MMIO(0x9888), 0x08b11880 },
-       { _MMIO(0x9888), 0x10b10000 },
-       { _MMIO(0x9888), 0x0eb34000 },
-       { _MMIO(0x9888), 0x16b30080 },
-       { _MMIO(0x9888), 0x01888000 },
-       { _MMIO(0x9888), 0x0d88b800 },
-       { _MMIO(0x9888), 0x038a0380 },
-       { _MMIO(0x9888), 0x058a000e },
-       { _MMIO(0x9888), 0x1b8a0080 },
-       { _MMIO(0x9888), 0x078a0000 },
-       { _MMIO(0x9888), 0x098a0000 },
-       { _MMIO(0x9888), 0x238b2840 },
-       { _MMIO(0x9888), 0x258b26a0 },
-       { _MMIO(0x9888), 0x018c4000 },
-       { _MMIO(0x9888), 0x0f8c4000 },
-       { _MMIO(0x9888), 0x178c2000 },
-       { _MMIO(0x9888), 0x198c1100 },
-       { _MMIO(0x9888), 0x018d2000 },
-       { _MMIO(0x9888), 0x078d8000 },
-       { _MMIO(0x9888), 0x098da000 },
-       { _MMIO(0x9888), 0x0b8d8000 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaa0 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x0d831021 },
-       { _MMIO(0x9888), 0x0f83572f },
-       { _MMIO(0x9888), 0x01835680 },
-       { _MMIO(0x9888), 0x0383002c },
-       { _MMIO(0x9888), 0x11830000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830001 },
-       { _MMIO(0x9888), 0x05830000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x05844000 },
-       { _MMIO(0x9888), 0x1b80c137 },
-       { _MMIO(0x9888), 0x1d80c147 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x17808000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x15804000 },
-       { _MMIO(0x9888), 0x4d801550 },
-       { _MMIO(0x9888), 0x4f800331 },
-       { _MMIO(0x9888), 0x43800802 },
-       { _MMIO(0x9888), 0x51800400 },
-       { _MMIO(0x9888), 0x458004a1 },
-       { _MMIO(0x9888), 0x53805555 },
-       { _MMIO(0x9888), 0x47800421 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f801421 },
-       { _MMIO(0x9888), 0x41800845 },
-};
-
-static int
-get_render_basic_mux_config(struct drm_i915_private *dev_priv,
-                           const struct i915_oa_reg **regs,
-                           int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2);
-
-       if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) {
-               regs[n] = mux_config_render_basic_0_slices_0x01;
-               lens[n] = ARRAY_SIZE(mux_config_render_basic_0_slices_0x01);
-               n++;
-       }
-       if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) {
-               regs[n] = mux_config_render_basic_1_slices_0x02;
-               lens[n] = ARRAY_SIZE(mux_config_render_basic_1_slices_0x02);
-               n++;
-       }
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_compute_basic[] = {
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0x00800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x00800000 },
-       { _MMIO(0x2740), 0x00000000 },
-};
-
-static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00000003 },
-       { _MMIO(0xe658), 0x00002001 },
-       { _MMIO(0xe758), 0x00778008 },
-       { _MMIO(0xe45c), 0x00088078 },
-       { _MMIO(0xe55c), 0x00808708 },
-       { _MMIO(0xe65c), 0x00a08908 },
-};
-
-static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01[] = {
-       { _MMIO(0x9888), 0x105c00e0 },
-       { _MMIO(0x9888), 0x105800e0 },
-       { _MMIO(0x9888), 0x103800e0 },
-       { _MMIO(0x9888), 0x3580001a },
-       { _MMIO(0x9888), 0x3b800060 },
-       { _MMIO(0x9888), 0x3d800005 },
-       { _MMIO(0x9888), 0x065c2100 },
-       { _MMIO(0x9888), 0x0a5c0041 },
-       { _MMIO(0x9888), 0x0c5c6600 },
-       { _MMIO(0x9888), 0x005c6580 },
-       { _MMIO(0x9888), 0x085c8000 },
-       { _MMIO(0x9888), 0x0e5c8000 },
-       { _MMIO(0x9888), 0x00580042 },
-       { _MMIO(0x9888), 0x08582080 },
-       { _MMIO(0x9888), 0x0c58004c },
-       { _MMIO(0x9888), 0x0e582580 },
-       { _MMIO(0x9888), 0x005b4000 },
-       { _MMIO(0x9888), 0x185b1000 },
-       { _MMIO(0x9888), 0x1a5b0104 },
-       { _MMIO(0x9888), 0x0c1fa800 },
-       { _MMIO(0x9888), 0x0e1faa00 },
-       { _MMIO(0x9888), 0x101f02aa },
-       { _MMIO(0x9888), 0x08380042 },
-       { _MMIO(0x9888), 0x0a382080 },
-       { _MMIO(0x9888), 0x0e38404c },
-       { _MMIO(0x9888), 0x0238404b },
-       { _MMIO(0x9888), 0x00384000 },
-       { _MMIO(0x9888), 0x16380000 },
-       { _MMIO(0x9888), 0x18381145 },
-       { _MMIO(0x9888), 0x04380000 },
-       { _MMIO(0x9888), 0x0039a000 },
-       { _MMIO(0x9888), 0x06398000 },
-       { _MMIO(0x9888), 0x0839a000 },
-       { _MMIO(0x9888), 0x0a39a000 },
-       { _MMIO(0x9888), 0x0c39a000 },
-       { _MMIO(0x9888), 0x0e39a000 },
-       { _MMIO(0x9888), 0x02392000 },
-       { _MMIO(0x9888), 0x018a8000 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x198a8000 },
-       { _MMIO(0x9888), 0x1b8aaaa0 },
-       { _MMIO(0x9888), 0x1d8a0002 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x238b02a0 },
-       { _MMIO(0x9888), 0x258b5550 },
-       { _MMIO(0x9888), 0x278b0015 },
-       { _MMIO(0x9888), 0x1f850a80 },
-       { _MMIO(0x9888), 0x2185aaa0 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x03844000 },
-       { _MMIO(0x9888), 0x17808137 },
-       { _MMIO(0x9888), 0x1980c147 },
-       { _MMIO(0x9888), 0x1b80c0e5 },
-       { _MMIO(0x9888), 0x1d80c0e3 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x13804000 },
-       { _MMIO(0x9888), 0x15800000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d801000 },
-       { _MMIO(0x9888), 0x4f800111 },
-       { _MMIO(0x9888), 0x43800062 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800062 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800062 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f801062 },
-       { _MMIO(0x9888), 0x41801084 },
-};
-
-static const struct i915_oa_reg mux_config_compute_basic_2_slices_0x02[] = {
-       { _MMIO(0x9888), 0x10dc00e0 },
-       { _MMIO(0x9888), 0x10d800e0 },
-       { _MMIO(0x9888), 0x10b800e0 },
-       { _MMIO(0x9888), 0x3580001a },
-       { _MMIO(0x9888), 0x3b800060 },
-       { _MMIO(0x9888), 0x3d800005 },
-       { _MMIO(0x9888), 0x06dc2100 },
-       { _MMIO(0x9888), 0x0adc0041 },
-       { _MMIO(0x9888), 0x0cdc6600 },
-       { _MMIO(0x9888), 0x00dc6580 },
-       { _MMIO(0x9888), 0x08dc8000 },
-       { _MMIO(0x9888), 0x0edc8000 },
-       { _MMIO(0x9888), 0x00d80042 },
-       { _MMIO(0x9888), 0x08d82080 },
-       { _MMIO(0x9888), 0x0cd8004c },
-       { _MMIO(0x9888), 0x0ed82580 },
-       { _MMIO(0x9888), 0x00db4000 },
-       { _MMIO(0x9888), 0x18db1000 },
-       { _MMIO(0x9888), 0x1adb0104 },
-       { _MMIO(0x9888), 0x0c9fa800 },
-       { _MMIO(0x9888), 0x0e9faa00 },
-       { _MMIO(0x9888), 0x109f02aa },
-       { _MMIO(0x9888), 0x08b80042 },
-       { _MMIO(0x9888), 0x0ab82080 },
-       { _MMIO(0x9888), 0x0eb8404c },
-       { _MMIO(0x9888), 0x02b8404b },
-       { _MMIO(0x9888), 0x00b84000 },
-       { _MMIO(0x9888), 0x16b80000 },
-       { _MMIO(0x9888), 0x18b81145 },
-       { _MMIO(0x9888), 0x04b80000 },
-       { _MMIO(0x9888), 0x00b9a000 },
-       { _MMIO(0x9888), 0x06b98000 },
-       { _MMIO(0x9888), 0x08b9a000 },
-       { _MMIO(0x9888), 0x0ab9a000 },
-       { _MMIO(0x9888), 0x0cb9a000 },
-       { _MMIO(0x9888), 0x0eb9a000 },
-       { _MMIO(0x9888), 0x02b92000 },
-       { _MMIO(0x9888), 0x01888000 },
-       { _MMIO(0x9888), 0x0d88f800 },
-       { _MMIO(0x9888), 0x0f88000f },
-       { _MMIO(0x9888), 0x03888000 },
-       { _MMIO(0x9888), 0x05888000 },
-       { _MMIO(0x9888), 0x238b0540 },
-       { _MMIO(0x9888), 0x258baaa0 },
-       { _MMIO(0x9888), 0x278b002a },
-       { _MMIO(0x9888), 0x018c4000 },
-       { _MMIO(0x9888), 0x0f8c4000 },
-       { _MMIO(0x9888), 0x178c2000 },
-       { _MMIO(0x9888), 0x198c5500 },
-       { _MMIO(0x9888), 0x1b8c0015 },
-       { _MMIO(0x9888), 0x038c4000 },
-       { _MMIO(0x9888), 0x058c4000 },
-       { _MMIO(0x9888), 0x018da000 },
-       { _MMIO(0x9888), 0x078d8000 },
-       { _MMIO(0x9888), 0x098da000 },
-       { _MMIO(0x9888), 0x0b8da000 },
-       { _MMIO(0x9888), 0x0d8da000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x038d2000 },
-       { _MMIO(0x9888), 0x1f850a80 },
-       { _MMIO(0x9888), 0x2185aaa0 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x03844000 },
-       { _MMIO(0x9888), 0x17808137 },
-       { _MMIO(0x9888), 0x1980c147 },
-       { _MMIO(0x9888), 0x1b80c0e5 },
-       { _MMIO(0x9888), 0x1d80c0e3 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x13804000 },
-       { _MMIO(0x9888), 0x15800000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d805000 },
-       { _MMIO(0x9888), 0x4f800555 },
-       { _MMIO(0x9888), 0x43800062 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800062 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800062 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800062 },
-       { _MMIO(0x9888), 0x41800000 },
-};
-
-static int
-get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
-                            const struct i915_oa_reg **regs,
-                            int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2);
-
-       if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) {
-               regs[n] = mux_config_compute_basic_0_slices_0x01;
-               lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01);
-               n++;
-       }
-       if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) {
-               regs[n] = mux_config_compute_basic_2_slices_0x02;
-               lens[n] = ARRAY_SIZE(mux_config_compute_basic_2_slices_0x02);
-               n++;
-       }
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
-       { _MMIO(0x2724), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2710), 0x00000000 },
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
        { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2770), 0x0007ffea },
-       { _MMIO(0x2774), 0x00007ffc },
-       { _MMIO(0x2778), 0x0007affa },
-       { _MMIO(0x277c), 0x0000f5fd },
-       { _MMIO(0x2780), 0x00079ffa },
-       { _MMIO(0x2784), 0x0000f3fb },
-       { _MMIO(0x2788), 0x0007bf7a },
-       { _MMIO(0x278c), 0x0000f7e7 },
-       { _MMIO(0x2790), 0x0007fefa },
-       { _MMIO(0x2794), 0x0000f7cf },
-       { _MMIO(0x2798), 0x00077ffa },
-       { _MMIO(0x279c), 0x0000efdf },
-       { _MMIO(0x27a0), 0x0006fffa },
-       { _MMIO(0x27a4), 0x0000cfbf },
-       { _MMIO(0x27a8), 0x0003fffa },
-       { _MMIO(0x27ac), 0x00005f7f },
-};
-
-static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00015014 },
-       { _MMIO(0xe658), 0x00025024 },
-       { _MMIO(0xe758), 0x00035034 },
-       { _MMIO(0xe45c), 0x00045044 },
-       { _MMIO(0xe55c), 0x00055054 },
-       { _MMIO(0xe65c), 0x00065064 },
-};
-
-static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
-       { _MMIO(0x9888), 0x0a1e0000 },
-       { _MMIO(0x9888), 0x0c1f000f },
-       { _MMIO(0x9888), 0x10176800 },
-       { _MMIO(0x9888), 0x1191001f },
-       { _MMIO(0x9888), 0x0b880320 },
-       { _MMIO(0x9888), 0x01890c40 },
-       { _MMIO(0x9888), 0x118a1c00 },
-       { _MMIO(0x9888), 0x118d7c00 },
-       { _MMIO(0x9888), 0x118e0020 },
-       { _MMIO(0x9888), 0x118f4c00 },
-       { _MMIO(0x9888), 0x11900000 },
-       { _MMIO(0x9888), 0x13900001 },
-       { _MMIO(0x9888), 0x065c4000 },
-       { _MMIO(0x9888), 0x0c3d8000 },
-       { _MMIO(0x9888), 0x06584000 },
-       { _MMIO(0x9888), 0x0c5b4000 },
-       { _MMIO(0x9888), 0x081e0040 },
-       { _MMIO(0x9888), 0x0e1e0000 },
-       { _MMIO(0x9888), 0x021f5400 },
-       { _MMIO(0x9888), 0x001f0000 },
-       { _MMIO(0x9888), 0x101f0010 },
-       { _MMIO(0x9888), 0x0e1f0080 },
-       { _MMIO(0x9888), 0x0c384000 },
-       { _MMIO(0x9888), 0x06392000 },
-       { _MMIO(0x9888), 0x0c13c000 },
-       { _MMIO(0x9888), 0x06164000 },
-       { _MMIO(0x9888), 0x06170012 },
-       { _MMIO(0x9888), 0x00170000 },
-       { _MMIO(0x9888), 0x01910005 },
-       { _MMIO(0x9888), 0x07880002 },
-       { _MMIO(0x9888), 0x01880c00 },
-       { _MMIO(0x9888), 0x0f880000 },
-       { _MMIO(0x9888), 0x0d880000 },
-       { _MMIO(0x9888), 0x05880000 },
-       { _MMIO(0x9888), 0x09890032 },
-       { _MMIO(0x9888), 0x078a0800 },
-       { _MMIO(0x9888), 0x0f8a0a00 },
-       { _MMIO(0x9888), 0x198a4000 },
-       { _MMIO(0x9888), 0x1b8a2000 },
-       { _MMIO(0x9888), 0x1d8a0000 },
-       { _MMIO(0x9888), 0x038a4000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x0d8a8000 },
-       { _MMIO(0x9888), 0x238b54c0 },
-       { _MMIO(0x9888), 0x258baa55 },
-       { _MMIO(0x9888), 0x278b0019 },
-       { _MMIO(0x9888), 0x198c0100 },
-       { _MMIO(0x9888), 0x058c4000 },
-       { _MMIO(0x9888), 0x0f8d0015 },
-       { _MMIO(0x9888), 0x018d1000 },
-       { _MMIO(0x9888), 0x098d8000 },
-       { _MMIO(0x9888), 0x0b8df000 },
-       { _MMIO(0x9888), 0x0d8d3000 },
-       { _MMIO(0x9888), 0x038de000 },
-       { _MMIO(0x9888), 0x058d3000 },
-       { _MMIO(0x9888), 0x0d8e0004 },
-       { _MMIO(0x9888), 0x058e000c },
-       { _MMIO(0x9888), 0x098e0000 },
-       { _MMIO(0x9888), 0x078e0000 },
-       { _MMIO(0x9888), 0x038e0000 },
-       { _MMIO(0x9888), 0x0b8f0020 },
-       { _MMIO(0x9888), 0x198f0c00 },
-       { _MMIO(0x9888), 0x078f8000 },
-       { _MMIO(0x9888), 0x098f4000 },
-       { _MMIO(0x9888), 0x0b900980 },
-       { _MMIO(0x9888), 0x03900d80 },
-       { _MMIO(0x9888), 0x01900000 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaaa },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x0784c000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x1780c000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d801111 },
-       { _MMIO(0x9888), 0x3d800800 },
-       { _MMIO(0x9888), 0x4f801011 },
-       { _MMIO(0x9888), 0x43800443 },
-       { _MMIO(0x9888), 0x51801111 },
-       { _MMIO(0x9888), 0x45800422 },
-       { _MMIO(0x9888), 0x53801111 },
-       { _MMIO(0x9888), 0x47800c60 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800422 },
-       { _MMIO(0x9888), 0x41800021 },
-};
-
-static int
-get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
-                                  const struct i915_oa_reg **regs,
-                                  int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_render_pipe_profile;
-       lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_memory_reads[] = {
-       { _MMIO(0x2724), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
+       { _MMIO(0x2744), 0x00800000 },
        { _MMIO(0x2714), 0xf0800000 },
        { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x274c), 0x86543210 },
-       { _MMIO(0x2748), 0x86543210 },
-       { _MMIO(0x2744), 0x00006667 },
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x275c), 0x86543210 },
-       { _MMIO(0x2758), 0x86543210 },
-       { _MMIO(0x2754), 0x00006465 },
-       { _MMIO(0x2750), 0x00000000 },
-       { _MMIO(0x2770), 0x0007f81a },
-       { _MMIO(0x2774), 0x0000fe00 },
-       { _MMIO(0x2778), 0x0007f82a },
-       { _MMIO(0x277c), 0x0000fe00 },
-       { _MMIO(0x2780), 0x0007f872 },
-       { _MMIO(0x2784), 0x0000fe00 },
-       { _MMIO(0x2788), 0x0007f8ba },
-       { _MMIO(0x278c), 0x0000fe00 },
-       { _MMIO(0x2790), 0x0007f87a },
-       { _MMIO(0x2794), 0x0000fe00 },
-       { _MMIO(0x2798), 0x0007f8ea },
-       { _MMIO(0x279c), 0x0000fe00 },
-       { _MMIO(0x27a0), 0x0007f8e2 },
-       { _MMIO(0x27a4), 0x0000fe00 },
-       { _MMIO(0x27a8), 0x0007f8f2 },
-       { _MMIO(0x27ac), 0x0000fe00 },
-};
-
-static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00015014 },
-       { _MMIO(0xe658), 0x00025024 },
-       { _MMIO(0xe758), 0x00035034 },
-       { _MMIO(0xe45c), 0x00045044 },
-       { _MMIO(0xe55c), 0x00055054 },
-       { _MMIO(0xe65c), 0x00065064 },
-};
-
-static const struct i915_oa_reg mux_config_memory_reads[] = {
-       { _MMIO(0x9888), 0x198b0343 },
-       { _MMIO(0x9888), 0x13845800 },
-       { _MMIO(0x9888), 0x15840018 },
-       { _MMIO(0x9888), 0x3580001a },
-       { _MMIO(0x9888), 0x038b6300 },
-       { _MMIO(0x9888), 0x058b6b62 },
-       { _MMIO(0x9888), 0x078b006a },
-       { _MMIO(0x9888), 0x118b0000 },
-       { _MMIO(0x9888), 0x238b0000 },
-       { _MMIO(0x9888), 0x258b0000 },
-       { _MMIO(0x9888), 0x1f85a080 },
-       { _MMIO(0x9888), 0x2185aaaa },
-       { _MMIO(0x9888), 0x2385000a },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x01840018 },
-       { _MMIO(0x9888), 0x07844c80 },
-       { _MMIO(0x9888), 0x09840d9a },
-       { _MMIO(0x9888), 0x0b840e9c },
-       { _MMIO(0x9888), 0x0d840f9e },
-       { _MMIO(0x9888), 0x0f840010 },
-       { _MMIO(0x9888), 0x11840000 },
-       { _MMIO(0x9888), 0x03848000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x2f8000e5 },
-       { _MMIO(0x9888), 0x138080e3 },
-       { _MMIO(0x9888), 0x1580c0e1 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x11804000 },
-       { _MMIO(0x9888), 0x1780c000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f804000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3d800800 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800842 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800842 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47801042 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800084 },
-       { _MMIO(0x9888), 0x41800000 },
-};
-
-static int
-get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
-                           const struct i915_oa_reg **regs,
-                           int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_memory_reads;
-       lens[n] = ARRAY_SIZE(mux_config_memory_reads);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_memory_writes[] = {
        { _MMIO(0x2724), 0xf0800000 },
        { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x274c), 0x86543210 },
-       { _MMIO(0x2748), 0x86543210 },
-       { _MMIO(0x2744), 0x00006667 },
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x275c), 0x86543210 },
-       { _MMIO(0x2758), 0x86543210 },
-       { _MMIO(0x2754), 0x00006465 },
-       { _MMIO(0x2750), 0x00000000 },
-       { _MMIO(0x2770), 0x0007f81a },
-       { _MMIO(0x2774), 0x0000fe00 },
-       { _MMIO(0x2778), 0x0007f82a },
-       { _MMIO(0x277c), 0x0000fe00 },
-       { _MMIO(0x2780), 0x0007f822 },
-       { _MMIO(0x2784), 0x0000fe00 },
-       { _MMIO(0x2788), 0x0007f8ba },
-       { _MMIO(0x278c), 0x0000fe00 },
-       { _MMIO(0x2790), 0x0007f87a },
-       { _MMIO(0x2794), 0x0000fe00 },
-       { _MMIO(0x2798), 0x0007f8ea },
-       { _MMIO(0x279c), 0x0000fe00 },
-       { _MMIO(0x27a0), 0x0007f8e2 },
-       { _MMIO(0x27a4), 0x0000fe00 },
-       { _MMIO(0x27a8), 0x0007f8f2 },
-       { _MMIO(0x27ac), 0x0000fe00 },
+       { _MMIO(0x2770), 0x00000004 },
+       { _MMIO(0x2774), 0x00000000 },
+       { _MMIO(0x2778), 0x00000003 },
+       { _MMIO(0x277c), 0x00000000 },
+       { _MMIO(0x2780), 0x00000007 },
+       { _MMIO(0x2784), 0x00000000 },
+       { _MMIO(0x2788), 0x00100002 },
+       { _MMIO(0x278c), 0x0000fff7 },
+       { _MMIO(0x2790), 0x00100002 },
+       { _MMIO(0x2794), 0x0000ffcf },
+       { _MMIO(0x2798), 0x00100082 },
+       { _MMIO(0x279c), 0x0000ffef },
+       { _MMIO(0x27a0), 0x001000c2 },
+       { _MMIO(0x27a4), 0x0000ffe7 },
+       { _MMIO(0x27a8), 0x00100001 },
+       { _MMIO(0x27ac), 0x0000ffe7 },
 };
 
-static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00015014 },
-       { _MMIO(0xe658), 0x00025024 },
-       { _MMIO(0xe758), 0x00035034 },
-       { _MMIO(0xe45c), 0x00045044 },
-       { _MMIO(0xe55c), 0x00055054 },
-       { _MMIO(0xe65c), 0x00065064 },
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
 };
 
-static const struct i915_oa_reg mux_config_memory_writes[] = {
-       { _MMIO(0x9888), 0x198b0343 },
-       { _MMIO(0x9888), 0x13845400 },
-       { _MMIO(0x9888), 0x3580001a },
-       { _MMIO(0x9888), 0x3d800805 },
-       { _MMIO(0x9888), 0x038b6300 },
-       { _MMIO(0x9888), 0x058b6b62 },
-       { _MMIO(0x9888), 0x078b006a },
+static const struct i915_oa_reg mux_config_test_oa[] = {
+       { _MMIO(0x9840), 0x000000a0 },
+       { _MMIO(0x9888), 0x198b0000 },
+       { _MMIO(0x9888), 0x078b0066 },
        { _MMIO(0x9888), 0x118b0000 },
-       { _MMIO(0x9888), 0x238b0000 },
        { _MMIO(0x9888), 0x258b0000 },
-       { _MMIO(0x9888), 0x1f85a080 },
-       { _MMIO(0x9888), 0x2185aaaa },
-       { _MMIO(0x9888), 0x23850002 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
+       { _MMIO(0x9888), 0x21850008 },
        { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x01840010 },
-       { _MMIO(0x9888), 0x07844880 },
-       { _MMIO(0x9888), 0x09840992 },
-       { _MMIO(0x9888), 0x0b840a94 },
-       { _MMIO(0x9888), 0x0d840b96 },
-       { _MMIO(0x9888), 0x11840000 },
-       { _MMIO(0x9888), 0x03848000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x2d800147 },
-       { _MMIO(0x9888), 0x2f8000e5 },
-       { _MMIO(0x9888), 0x138080e3 },
-       { _MMIO(0x9888), 0x1580c0e1 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x11804000 },
-       { _MMIO(0x9888), 0x1780c000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f800000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800842 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800842 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47801082 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800084 },
-       { _MMIO(0x9888), 0x41800000 },
-};
-
-static int
-get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
-                            const struct i915_oa_reg **regs,
-                            int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_memory_writes;
-       lens[n] = ARRAY_SIZE(mux_config_memory_writes);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_compute_extended[] = {
-       { _MMIO(0x2724), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2770), 0x0007fc2a },
-       { _MMIO(0x2774), 0x0000bf00 },
-       { _MMIO(0x2778), 0x0007fc6a },
-       { _MMIO(0x277c), 0x0000bf00 },
-       { _MMIO(0x2780), 0x0007fc92 },
-       { _MMIO(0x2784), 0x0000bf00 },
-       { _MMIO(0x2788), 0x0007fca2 },
-       { _MMIO(0x278c), 0x0000bf00 },
-       { _MMIO(0x2790), 0x0007fc32 },
-       { _MMIO(0x2794), 0x0000bf00 },
-       { _MMIO(0x2798), 0x0007fc9a },
-       { _MMIO(0x279c), 0x0000bf00 },
-       { _MMIO(0x27a0), 0x0007fe6a },
-       { _MMIO(0x27a4), 0x0000bf00 },
-       { _MMIO(0x27a8), 0x0007fe7a },
-       { _MMIO(0x27ac), 0x0000bf00 },
-};
-
-static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00000003 },
-       { _MMIO(0xe658), 0x00002001 },
-       { _MMIO(0xe758), 0x00778008 },
-       { _MMIO(0xe45c), 0x00088078 },
-       { _MMIO(0xe55c), 0x00808708 },
-       { _MMIO(0xe65c), 0x00a08908 },
-};
-
-static const struct i915_oa_reg mux_config_compute_extended_0_subslices_0x01[] = {
-       { _MMIO(0x9888), 0x143d0160 },
-       { _MMIO(0x9888), 0x163d2800 },
-       { _MMIO(0x9888), 0x183d0120 },
-       { _MMIO(0x9888), 0x105800e0 },
-       { _MMIO(0x9888), 0x005cc000 },
-       { _MMIO(0x9888), 0x065c8000 },
-       { _MMIO(0x9888), 0x085cc000 },
-       { _MMIO(0x9888), 0x0a5cc000 },
-       { _MMIO(0x9888), 0x0c5cc000 },
-       { _MMIO(0x9888), 0x0e5cc000 },
-       { _MMIO(0x9888), 0x025cc000 },
-       { _MMIO(0x9888), 0x045cc000 },
-       { _MMIO(0x9888), 0x003d0011 },
-       { _MMIO(0x9888), 0x063d0900 },
-       { _MMIO(0x9888), 0x083d0a13 },
-       { _MMIO(0x9888), 0x0a3d0b15 },
-       { _MMIO(0x9888), 0x0c3d2317 },
-       { _MMIO(0x9888), 0x043d21b7 },
-       { _MMIO(0x9888), 0x103d0000 },
-       { _MMIO(0x9888), 0x0e3d0000 },
-       { _MMIO(0x9888), 0x1a3d0000 },
-       { _MMIO(0x9888), 0x0e5825c1 },
-       { _MMIO(0x9888), 0x00586100 },
-       { _MMIO(0x9888), 0x0258204c },
-       { _MMIO(0x9888), 0x06588000 },
-       { _MMIO(0x9888), 0x0858c000 },
-       { _MMIO(0x9888), 0x0a58c000 },
-       { _MMIO(0x9888), 0x0c58c000 },
-       { _MMIO(0x9888), 0x0458c000 },
-       { _MMIO(0x9888), 0x005b4000 },
-       { _MMIO(0x9888), 0x0e5b4000 },
-       { _MMIO(0x9888), 0x185b5400 },
-       { _MMIO(0x9888), 0x1a5b0155 },
-       { _MMIO(0x9888), 0x025b4000 },
-       { _MMIO(0x9888), 0x045b4000 },
-       { _MMIO(0x9888), 0x065b4000 },
-       { _MMIO(0x9888), 0x085b4000 },
-       { _MMIO(0x9888), 0x0a5b4000 },
-       { _MMIO(0x9888), 0x0c1fa800 },
-       { _MMIO(0x9888), 0x0e1faa2a },
-       { _MMIO(0x9888), 0x101f02aa },
-       { _MMIO(0x9888), 0x00384000 },
-       { _MMIO(0x9888), 0x0e384000 },
-       { _MMIO(0x9888), 0x16384000 },
-       { _MMIO(0x9888), 0x18381555 },
-       { _MMIO(0x9888), 0x02384000 },
-       { _MMIO(0x9888), 0x04384000 },
-       { _MMIO(0x9888), 0x06384000 },
-       { _MMIO(0x9888), 0x08384000 },
-       { _MMIO(0x9888), 0x0a384000 },
-       { _MMIO(0x9888), 0x0039a000 },
-       { _MMIO(0x9888), 0x06398000 },
-       { _MMIO(0x9888), 0x0839a000 },
-       { _MMIO(0x9888), 0x0a39a000 },
-       { _MMIO(0x9888), 0x0c39a000 },
-       { _MMIO(0x9888), 0x0e39a000 },
-       { _MMIO(0x9888), 0x0239a000 },
-       { _MMIO(0x9888), 0x0439a000 },
-       { _MMIO(0x9888), 0x018a8000 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x198a8000 },
-       { _MMIO(0x9888), 0x1b8aaaa0 },
-       { _MMIO(0x9888), 0x1d8a0002 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x078a8000 },
-       { _MMIO(0x9888), 0x098a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x238b2aa0 },
-       { _MMIO(0x9888), 0x258b5551 },
-       { _MMIO(0x9888), 0x278b0015 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaa2 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x17808000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3d800000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800000 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800420 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800421 },
-       { _MMIO(0x9888), 0x41800000 },
-};
-
-static const struct i915_oa_reg mux_config_compute_extended_2_subslices_0x02[] = {
-       { _MMIO(0x9888), 0x105c00e0 },
-       { _MMIO(0x9888), 0x145b0160 },
-       { _MMIO(0x9888), 0x165b2800 },
-       { _MMIO(0x9888), 0x185b0120 },
-       { _MMIO(0x9888), 0x0e5c25c1 },
-       { _MMIO(0x9888), 0x005c6100 },
-       { _MMIO(0x9888), 0x025c204c },
-       { _MMIO(0x9888), 0x065c8000 },
-       { _MMIO(0x9888), 0x085cc000 },
-       { _MMIO(0x9888), 0x0a5cc000 },
-       { _MMIO(0x9888), 0x0c5cc000 },
-       { _MMIO(0x9888), 0x045cc000 },
-       { _MMIO(0x9888), 0x005b0011 },
-       { _MMIO(0x9888), 0x065b0900 },
-       { _MMIO(0x9888), 0x085b0a13 },
-       { _MMIO(0x9888), 0x0a5b0b15 },
-       { _MMIO(0x9888), 0x0c5b2317 },
-       { _MMIO(0x9888), 0x045b21b7 },
-       { _MMIO(0x9888), 0x105b0000 },
-       { _MMIO(0x9888), 0x0e5b0000 },
-       { _MMIO(0x9888), 0x1a5b0000 },
-       { _MMIO(0x9888), 0x0c1fa800 },
-       { _MMIO(0x9888), 0x0e1faa2a },
-       { _MMIO(0x9888), 0x101f02aa },
-       { _MMIO(0x9888), 0x00384000 },
-       { _MMIO(0x9888), 0x0e384000 },
-       { _MMIO(0x9888), 0x16384000 },
-       { _MMIO(0x9888), 0x18381555 },
-       { _MMIO(0x9888), 0x02384000 },
-       { _MMIO(0x9888), 0x04384000 },
-       { _MMIO(0x9888), 0x06384000 },
-       { _MMIO(0x9888), 0x08384000 },
-       { _MMIO(0x9888), 0x0a384000 },
-       { _MMIO(0x9888), 0x0039a000 },
-       { _MMIO(0x9888), 0x06398000 },
-       { _MMIO(0x9888), 0x0839a000 },
-       { _MMIO(0x9888), 0x0a39a000 },
-       { _MMIO(0x9888), 0x0c39a000 },
-       { _MMIO(0x9888), 0x0e39a000 },
-       { _MMIO(0x9888), 0x0239a000 },
-       { _MMIO(0x9888), 0x0439a000 },
-       { _MMIO(0x9888), 0x018a8000 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x198a8000 },
-       { _MMIO(0x9888), 0x1b8aaaa0 },
-       { _MMIO(0x9888), 0x1d8a0002 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x078a8000 },
-       { _MMIO(0x9888), 0x098a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x238b2aa0 },
-       { _MMIO(0x9888), 0x258b5551 },
-       { _MMIO(0x9888), 0x278b0015 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaa2 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x17808000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3d800000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800000 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800420 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800421 },
-       { _MMIO(0x9888), 0x41800000 },
-};
-
-static const struct i915_oa_reg mux_config_compute_extended_4_subslices_0x04[] = {
-       { _MMIO(0x9888), 0x103800e0 },
-       { _MMIO(0x9888), 0x143a0160 },
-       { _MMIO(0x9888), 0x163a2800 },
-       { _MMIO(0x9888), 0x183a0120 },
-       { _MMIO(0x9888), 0x0c1fa800 },
-       { _MMIO(0x9888), 0x0e1faa2a },
-       { _MMIO(0x9888), 0x101f02aa },
-       { _MMIO(0x9888), 0x0e38a5c1 },
-       { _MMIO(0x9888), 0x0038a100 },
-       { _MMIO(0x9888), 0x0238204c },
-       { _MMIO(0x9888), 0x16388000 },
-       { _MMIO(0x9888), 0x183802aa },
-       { _MMIO(0x9888), 0x04380000 },
-       { _MMIO(0x9888), 0x06380000 },
-       { _MMIO(0x9888), 0x08388000 },
-       { _MMIO(0x9888), 0x0a388000 },
-       { _MMIO(0x9888), 0x0039a000 },
-       { _MMIO(0x9888), 0x06398000 },
-       { _MMIO(0x9888), 0x0839a000 },
-       { _MMIO(0x9888), 0x0a39a000 },
-       { _MMIO(0x9888), 0x0c39a000 },
-       { _MMIO(0x9888), 0x0e39a000 },
-       { _MMIO(0x9888), 0x0239a000 },
-       { _MMIO(0x9888), 0x0439a000 },
-       { _MMIO(0x9888), 0x003a0011 },
-       { _MMIO(0x9888), 0x063a0900 },
-       { _MMIO(0x9888), 0x083a0a13 },
-       { _MMIO(0x9888), 0x0a3a0b15 },
-       { _MMIO(0x9888), 0x0c3a2317 },
-       { _MMIO(0x9888), 0x043a21b7 },
-       { _MMIO(0x9888), 0x103a0000 },
-       { _MMIO(0x9888), 0x0e3a0000 },
-       { _MMIO(0x9888), 0x1a3a0000 },
-       { _MMIO(0x9888), 0x018a8000 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x198a8000 },
-       { _MMIO(0x9888), 0x1b8aaaa0 },
-       { _MMIO(0x9888), 0x1d8a0002 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x078a8000 },
-       { _MMIO(0x9888), 0x098a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x238b2aa0 },
-       { _MMIO(0x9888), 0x258b5551 },
-       { _MMIO(0x9888), 0x278b0015 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaa2 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x17808000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3d800000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800000 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800420 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800421 },
-       { _MMIO(0x9888), 0x41800000 },
-};
-
-static const struct i915_oa_reg mux_config_compute_extended_1_subslices_0x08[] = {
-       { _MMIO(0x9888), 0x14bd0160 },
-       { _MMIO(0x9888), 0x16bd2800 },
-       { _MMIO(0x9888), 0x18bd0120 },
-       { _MMIO(0x9888), 0x10d800e0 },
-       { _MMIO(0x9888), 0x00dcc000 },
-       { _MMIO(0x9888), 0x06dc8000 },
-       { _MMIO(0x9888), 0x08dcc000 },
-       { _MMIO(0x9888), 0x0adcc000 },
-       { _MMIO(0x9888), 0x0cdcc000 },
-       { _MMIO(0x9888), 0x0edcc000 },
-       { _MMIO(0x9888), 0x02dcc000 },
-       { _MMIO(0x9888), 0x04dcc000 },
-       { _MMIO(0x9888), 0x00bd0011 },
-       { _MMIO(0x9888), 0x06bd0900 },
-       { _MMIO(0x9888), 0x08bd0a13 },
-       { _MMIO(0x9888), 0x0abd0b15 },
-       { _MMIO(0x9888), 0x0cbd2317 },
-       { _MMIO(0x9888), 0x04bd21b7 },
-       { _MMIO(0x9888), 0x10bd0000 },
-       { _MMIO(0x9888), 0x0ebd0000 },
-       { _MMIO(0x9888), 0x1abd0000 },
-       { _MMIO(0x9888), 0x0ed825c1 },
-       { _MMIO(0x9888), 0x00d86100 },
-       { _MMIO(0x9888), 0x02d8204c },
-       { _MMIO(0x9888), 0x06d88000 },
-       { _MMIO(0x9888), 0x08d8c000 },
-       { _MMIO(0x9888), 0x0ad8c000 },
-       { _MMIO(0x9888), 0x0cd8c000 },
-       { _MMIO(0x9888), 0x04d8c000 },
-       { _MMIO(0x9888), 0x00db4000 },
-       { _MMIO(0x9888), 0x0edb4000 },
-       { _MMIO(0x9888), 0x18db5400 },
-       { _MMIO(0x9888), 0x1adb0155 },
-       { _MMIO(0x9888), 0x02db4000 },
-       { _MMIO(0x9888), 0x04db4000 },
-       { _MMIO(0x9888), 0x06db4000 },
-       { _MMIO(0x9888), 0x08db4000 },
-       { _MMIO(0x9888), 0x0adb4000 },
-       { _MMIO(0x9888), 0x0c9fa800 },
-       { _MMIO(0x9888), 0x0e9faa2a },
-       { _MMIO(0x9888), 0x109f02aa },
-       { _MMIO(0x9888), 0x00b84000 },
-       { _MMIO(0x9888), 0x0eb84000 },
-       { _MMIO(0x9888), 0x16b84000 },
-       { _MMIO(0x9888), 0x18b81555 },
-       { _MMIO(0x9888), 0x02b84000 },
-       { _MMIO(0x9888), 0x04b84000 },
-       { _MMIO(0x9888), 0x06b84000 },
-       { _MMIO(0x9888), 0x08b84000 },
-       { _MMIO(0x9888), 0x0ab84000 },
-       { _MMIO(0x9888), 0x00b9a000 },
-       { _MMIO(0x9888), 0x06b98000 },
-       { _MMIO(0x9888), 0x08b9a000 },
-       { _MMIO(0x9888), 0x0ab9a000 },
-       { _MMIO(0x9888), 0x0cb9a000 },
-       { _MMIO(0x9888), 0x0eb9a000 },
-       { _MMIO(0x9888), 0x02b9a000 },
-       { _MMIO(0x9888), 0x04b9a000 },
-       { _MMIO(0x9888), 0x01888000 },
-       { _MMIO(0x9888), 0x0d88f800 },
-       { _MMIO(0x9888), 0x0f88000f },
-       { _MMIO(0x9888), 0x03888000 },
-       { _MMIO(0x9888), 0x05888000 },
-       { _MMIO(0x9888), 0x07888000 },
-       { _MMIO(0x9888), 0x09888000 },
-       { _MMIO(0x9888), 0x0b888000 },
-       { _MMIO(0x9888), 0x238b5540 },
-       { _MMIO(0x9888), 0x258baaa2 },
-       { _MMIO(0x9888), 0x278b002a },
-       { _MMIO(0x9888), 0x018c4000 },
-       { _MMIO(0x9888), 0x0f8c4000 },
-       { _MMIO(0x9888), 0x178c2000 },
-       { _MMIO(0x9888), 0x198c5500 },
-       { _MMIO(0x9888), 0x1b8c0015 },
-       { _MMIO(0x9888), 0x038c4000 },
-       { _MMIO(0x9888), 0x058c4000 },
-       { _MMIO(0x9888), 0x078c4000 },
-       { _MMIO(0x9888), 0x098c4000 },
-       { _MMIO(0x9888), 0x0b8c4000 },
-       { _MMIO(0x9888), 0x018da000 },
-       { _MMIO(0x9888), 0x078d8000 },
-       { _MMIO(0x9888), 0x098da000 },
-       { _MMIO(0x9888), 0x0b8da000 },
-       { _MMIO(0x9888), 0x0d8da000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x038da000 },
-       { _MMIO(0x9888), 0x058da000 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaa2 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x17808000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3d800000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800000 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800420 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800421 },
-       { _MMIO(0x9888), 0x41800000 },
-};
-
-static const struct i915_oa_reg mux_config_compute_extended_3_subslices_0x10[] = {
-       { _MMIO(0x9888), 0x10dc00e0 },
-       { _MMIO(0x9888), 0x14db0160 },
-       { _MMIO(0x9888), 0x16db2800 },
-       { _MMIO(0x9888), 0x18db0120 },
-       { _MMIO(0x9888), 0x0edc25c1 },
-       { _MMIO(0x9888), 0x00dc6100 },
-       { _MMIO(0x9888), 0x02dc204c },
-       { _MMIO(0x9888), 0x06dc8000 },
-       { _MMIO(0x9888), 0x08dcc000 },
-       { _MMIO(0x9888), 0x0adcc000 },
-       { _MMIO(0x9888), 0x0cdcc000 },
-       { _MMIO(0x9888), 0x04dcc000 },
-       { _MMIO(0x9888), 0x00db0011 },
-       { _MMIO(0x9888), 0x06db0900 },
-       { _MMIO(0x9888), 0x08db0a13 },
-       { _MMIO(0x9888), 0x0adb0b15 },
-       { _MMIO(0x9888), 0x0cdb2317 },
-       { _MMIO(0x9888), 0x04db21b7 },
-       { _MMIO(0x9888), 0x10db0000 },
-       { _MMIO(0x9888), 0x0edb0000 },
-       { _MMIO(0x9888), 0x1adb0000 },
-       { _MMIO(0x9888), 0x0c9fa800 },
-       { _MMIO(0x9888), 0x0e9faa2a },
-       { _MMIO(0x9888), 0x109f02aa },
-       { _MMIO(0x9888), 0x00b84000 },
-       { _MMIO(0x9888), 0x0eb84000 },
-       { _MMIO(0x9888), 0x16b84000 },
-       { _MMIO(0x9888), 0x18b81555 },
-       { _MMIO(0x9888), 0x02b84000 },
-       { _MMIO(0x9888), 0x04b84000 },
-       { _MMIO(0x9888), 0x06b84000 },
-       { _MMIO(0x9888), 0x08b84000 },
-       { _MMIO(0x9888), 0x0ab84000 },
-       { _MMIO(0x9888), 0x00b9a000 },
-       { _MMIO(0x9888), 0x06b98000 },
-       { _MMIO(0x9888), 0x08b9a000 },
-       { _MMIO(0x9888), 0x0ab9a000 },
-       { _MMIO(0x9888), 0x0cb9a000 },
-       { _MMIO(0x9888), 0x0eb9a000 },
-       { _MMIO(0x9888), 0x02b9a000 },
-       { _MMIO(0x9888), 0x04b9a000 },
-       { _MMIO(0x9888), 0x01888000 },
-       { _MMIO(0x9888), 0x0d88f800 },
-       { _MMIO(0x9888), 0x0f88000f },
-       { _MMIO(0x9888), 0x03888000 },
-       { _MMIO(0x9888), 0x05888000 },
-       { _MMIO(0x9888), 0x07888000 },
-       { _MMIO(0x9888), 0x09888000 },
-       { _MMIO(0x9888), 0x0b888000 },
-       { _MMIO(0x9888), 0x238b5540 },
-       { _MMIO(0x9888), 0x258baaa2 },
-       { _MMIO(0x9888), 0x278b002a },
-       { _MMIO(0x9888), 0x018c4000 },
-       { _MMIO(0x9888), 0x0f8c4000 },
-       { _MMIO(0x9888), 0x178c2000 },
-       { _MMIO(0x9888), 0x198c5500 },
-       { _MMIO(0x9888), 0x1b8c0015 },
-       { _MMIO(0x9888), 0x038c4000 },
-       { _MMIO(0x9888), 0x058c4000 },
-       { _MMIO(0x9888), 0x078c4000 },
-       { _MMIO(0x9888), 0x098c4000 },
-       { _MMIO(0x9888), 0x0b8c4000 },
-       { _MMIO(0x9888), 0x018da000 },
-       { _MMIO(0x9888), 0x078d8000 },
-       { _MMIO(0x9888), 0x098da000 },
-       { _MMIO(0x9888), 0x0b8da000 },
-       { _MMIO(0x9888), 0x0d8da000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x038da000 },
-       { _MMIO(0x9888), 0x058da000 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaa2 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x17808000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3d800000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800000 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800420 },
+       { _MMIO(0x9888), 0x07844000 },
+       { _MMIO(0x9888), 0x17804000 },
        { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800421 },
-       { _MMIO(0x9888), 0x41800000 },
-};
-
-static const struct i915_oa_reg mux_config_compute_extended_5_subslices_0x20[] = {
-       { _MMIO(0x9888), 0x10b800e0 },
-       { _MMIO(0x9888), 0x14ba0160 },
-       { _MMIO(0x9888), 0x16ba2800 },
-       { _MMIO(0x9888), 0x18ba0120 },
-       { _MMIO(0x9888), 0x0c9fa800 },
-       { _MMIO(0x9888), 0x0e9faa2a },
-       { _MMIO(0x9888), 0x109f02aa },
-       { _MMIO(0x9888), 0x0eb8a5c1 },
-       { _MMIO(0x9888), 0x00b8a100 },
-       { _MMIO(0x9888), 0x02b8204c },
-       { _MMIO(0x9888), 0x16b88000 },
-       { _MMIO(0x9888), 0x18b802aa },
-       { _MMIO(0x9888), 0x04b80000 },
-       { _MMIO(0x9888), 0x06b80000 },
-       { _MMIO(0x9888), 0x08b88000 },
-       { _MMIO(0x9888), 0x0ab88000 },
-       { _MMIO(0x9888), 0x00b9a000 },
-       { _MMIO(0x9888), 0x06b98000 },
-       { _MMIO(0x9888), 0x08b9a000 },
-       { _MMIO(0x9888), 0x0ab9a000 },
-       { _MMIO(0x9888), 0x0cb9a000 },
-       { _MMIO(0x9888), 0x0eb9a000 },
-       { _MMIO(0x9888), 0x02b9a000 },
-       { _MMIO(0x9888), 0x04b9a000 },
-       { _MMIO(0x9888), 0x00ba0011 },
-       { _MMIO(0x9888), 0x06ba0900 },
-       { _MMIO(0x9888), 0x08ba0a13 },
-       { _MMIO(0x9888), 0x0aba0b15 },
-       { _MMIO(0x9888), 0x0cba2317 },
-       { _MMIO(0x9888), 0x04ba21b7 },
-       { _MMIO(0x9888), 0x10ba0000 },
-       { _MMIO(0x9888), 0x0eba0000 },
-       { _MMIO(0x9888), 0x1aba0000 },
-       { _MMIO(0x9888), 0x01888000 },
-       { _MMIO(0x9888), 0x0d88f800 },
-       { _MMIO(0x9888), 0x0f88000f },
-       { _MMIO(0x9888), 0x03888000 },
-       { _MMIO(0x9888), 0x05888000 },
-       { _MMIO(0x9888), 0x07888000 },
-       { _MMIO(0x9888), 0x09888000 },
-       { _MMIO(0x9888), 0x0b888000 },
-       { _MMIO(0x9888), 0x238b5540 },
-       { _MMIO(0x9888), 0x258baaa2 },
-       { _MMIO(0x9888), 0x278b002a },
-       { _MMIO(0x9888), 0x018c4000 },
-       { _MMIO(0x9888), 0x0f8c4000 },
-       { _MMIO(0x9888), 0x178c2000 },
-       { _MMIO(0x9888), 0x198c5500 },
-       { _MMIO(0x9888), 0x1b8c0015 },
-       { _MMIO(0x9888), 0x038c4000 },
-       { _MMIO(0x9888), 0x058c4000 },
-       { _MMIO(0x9888), 0x078c4000 },
-       { _MMIO(0x9888), 0x098c4000 },
-       { _MMIO(0x9888), 0x0b8c4000 },
-       { _MMIO(0x9888), 0x018da000 },
-       { _MMIO(0x9888), 0x078d8000 },
-       { _MMIO(0x9888), 0x098da000 },
-       { _MMIO(0x9888), 0x0b8da000 },
-       { _MMIO(0x9888), 0x0d8da000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x038da000 },
-       { _MMIO(0x9888), 0x058da000 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaa2 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x17808000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3d800000 },
        { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800000 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800420 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800421 },
        { _MMIO(0x9888), 0x41800000 },
-};
-
-static int
-get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
-                               const struct i915_oa_reg **regs,
-                               int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 6);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 6);
-
-       if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
-               regs[n] = mux_config_compute_extended_0_subslices_0x01;
-               lens[n] = ARRAY_SIZE(mux_config_compute_extended_0_subslices_0x01);
-               n++;
-       }
-       if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x08) {
-               regs[n] = mux_config_compute_extended_1_subslices_0x08;
-               lens[n] = ARRAY_SIZE(mux_config_compute_extended_1_subslices_0x08);
-               n++;
-       }
-       if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x02) {
-               regs[n] = mux_config_compute_extended_2_subslices_0x02;
-               lens[n] = ARRAY_SIZE(mux_config_compute_extended_2_subslices_0x02);
-               n++;
-       }
-       if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x10) {
-               regs[n] = mux_config_compute_extended_3_subslices_0x10;
-               lens[n] = ARRAY_SIZE(mux_config_compute_extended_3_subslices_0x10);
-               n++;
-       }
-       if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x04) {
-               regs[n] = mux_config_compute_extended_4_subslices_0x04;
-               lens[n] = ARRAY_SIZE(mux_config_compute_extended_4_subslices_0x04);
-               n++;
-       }
-       if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x20) {
-               regs[n] = mux_config_compute_extended_5_subslices_0x20;
-               lens[n] = ARRAY_SIZE(mux_config_compute_extended_5_subslices_0x20);
-               n++;
-       }
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0x30800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x30800000 },
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2770), 0x0007fffa },
-       { _MMIO(0x2774), 0x0000fefe },
-       { _MMIO(0x2778), 0x0007fffa },
-       { _MMIO(0x277c), 0x0000fefd },
-       { _MMIO(0x2790), 0x0007fffa },
-       { _MMIO(0x2794), 0x0000fbef },
-       { _MMIO(0x2798), 0x0007fffa },
-       { _MMIO(0x279c), 0x0000fbdf },
-};
-
-static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00000003 },
-       { _MMIO(0xe658), 0x00002001 },
-       { _MMIO(0xe758), 0x00101100 },
-       { _MMIO(0xe45c), 0x00201200 },
-       { _MMIO(0xe55c), 0x00301300 },
-       { _MMIO(0xe65c), 0x00401400 },
-};
-
-static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
-       { _MMIO(0x9888), 0x143f00b3 },
-       { _MMIO(0x9888), 0x14bf00b3 },
-       { _MMIO(0x9888), 0x138303c0 },
-       { _MMIO(0x9888), 0x3b800060 },
-       { _MMIO(0x9888), 0x3d800805 },
-       { _MMIO(0x9888), 0x003f0029 },
-       { _MMIO(0x9888), 0x063f1400 },
-       { _MMIO(0x9888), 0x083f1225 },
-       { _MMIO(0x9888), 0x0e3f1327 },
-       { _MMIO(0x9888), 0x103f0000 },
-       { _MMIO(0x9888), 0x005a4000 },
-       { _MMIO(0x9888), 0x065a8000 },
-       { _MMIO(0x9888), 0x085ac000 },
-       { _MMIO(0x9888), 0x0e5ac000 },
-       { _MMIO(0x9888), 0x001d4000 },
-       { _MMIO(0x9888), 0x061d8000 },
-       { _MMIO(0x9888), 0x081dc000 },
-       { _MMIO(0x9888), 0x0e1dc000 },
-       { _MMIO(0x9888), 0x0c1f0800 },
-       { _MMIO(0x9888), 0x0e1f2a00 },
-       { _MMIO(0x9888), 0x101f0280 },
-       { _MMIO(0x9888), 0x00391000 },
-       { _MMIO(0x9888), 0x06394000 },
-       { _MMIO(0x9888), 0x08395000 },
-       { _MMIO(0x9888), 0x0e395000 },
-       { _MMIO(0x9888), 0x0abf1429 },
-       { _MMIO(0x9888), 0x0cbf1225 },
-       { _MMIO(0x9888), 0x00bf1380 },
-       { _MMIO(0x9888), 0x02bf0026 },
-       { _MMIO(0x9888), 0x10bf0000 },
-       { _MMIO(0x9888), 0x0adac000 },
-       { _MMIO(0x9888), 0x0cdac000 },
-       { _MMIO(0x9888), 0x00da8000 },
-       { _MMIO(0x9888), 0x02da4000 },
-       { _MMIO(0x9888), 0x0a9dc000 },
-       { _MMIO(0x9888), 0x0c9dc000 },
-       { _MMIO(0x9888), 0x009d8000 },
-       { _MMIO(0x9888), 0x029d4000 },
-       { _MMIO(0x9888), 0x0e9f8000 },
-       { _MMIO(0x9888), 0x109f002a },
-       { _MMIO(0x9888), 0x0c9fa000 },
-       { _MMIO(0x9888), 0x0ab95000 },
-       { _MMIO(0x9888), 0x0cb95000 },
-       { _MMIO(0x9888), 0x00b94000 },
-       { _MMIO(0x9888), 0x02b91000 },
-       { _MMIO(0x9888), 0x0d88c000 },
-       { _MMIO(0x9888), 0x0f880003 },
-       { _MMIO(0x9888), 0x03888000 },
-       { _MMIO(0x9888), 0x05888000 },
-       { _MMIO(0x9888), 0x018a8000 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x198a8000 },
-       { _MMIO(0x9888), 0x1b8a8020 },
-       { _MMIO(0x9888), 0x1d8a0002 },
-       { _MMIO(0x9888), 0x238b0520 },
-       { _MMIO(0x9888), 0x258ba950 },
-       { _MMIO(0x9888), 0x278b0016 },
-       { _MMIO(0x9888), 0x198c5400 },
-       { _MMIO(0x9888), 0x1b8c0001 },
-       { _MMIO(0x9888), 0x038c4000 },
-       { _MMIO(0x9888), 0x058c4000 },
-       { _MMIO(0x9888), 0x0b8da000 },
-       { _MMIO(0x9888), 0x0d8da000 },
-       { _MMIO(0x9888), 0x018d8000 },
-       { _MMIO(0x9888), 0x038d2000 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaa0 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x03835180 },
-       { _MMIO(0x9888), 0x05834022 },
-       { _MMIO(0x9888), 0x11830000 },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x07830000 },
-       { _MMIO(0x9888), 0x09830000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x05844000 },
-       { _MMIO(0x9888), 0x1b80c137 },
-       { _MMIO(0x9888), 0x1d80c147 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x17808000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x15804000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d801000 },
-       { _MMIO(0x9888), 0x4f800111 },
-       { _MMIO(0x9888), 0x43800842 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800840 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800800 },
-       { _MMIO(0x9888), 0x418014a2 },
-};
-
-static int
-get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
-                               const struct i915_oa_reg **regs,
-                               int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_compute_l3_cache;
-       lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_data_port_reads_coalescing[] = {
-       { _MMIO(0x2724), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x274c), 0xba98ba98 },
-       { _MMIO(0x2748), 0xba98ba98 },
-       { _MMIO(0x2744), 0x00003377 },
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2770), 0x0007fff2 },
-       { _MMIO(0x2774), 0x00007ff0 },
-       { _MMIO(0x2778), 0x0007ffe2 },
-       { _MMIO(0x277c), 0x00007ff0 },
-       { _MMIO(0x2780), 0x0007ffc2 },
-       { _MMIO(0x2784), 0x00007ff0 },
-       { _MMIO(0x2788), 0x0007ff82 },
-       { _MMIO(0x278c), 0x00007ff0 },
-       { _MMIO(0x2790), 0x0007fffa },
-       { _MMIO(0x2794), 0x0000bfef },
-       { _MMIO(0x2798), 0x0007fffa },
-       { _MMIO(0x279c), 0x0000bfdf },
-       { _MMIO(0x27a0), 0x0007fffa },
-       { _MMIO(0x27a4), 0x0000bfbf },
-       { _MMIO(0x27a8), 0x0007fffa },
-       { _MMIO(0x27ac), 0x0000bf7f },
-};
-
-static const struct i915_oa_reg flex_eu_config_data_port_reads_coalescing[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00000003 },
-       { _MMIO(0xe658), 0x00002001 },
-       { _MMIO(0xe758), 0x00778008 },
-       { _MMIO(0xe45c), 0x00088078 },
-       { _MMIO(0xe55c), 0x00808708 },
-       { _MMIO(0xe65c), 0x00a08908 },
-};
-
-static const struct i915_oa_reg mux_config_data_port_reads_coalescing_0_subslices_0x01[] = {
-       { _MMIO(0x9888), 0x103d0005 },
-       { _MMIO(0x9888), 0x163d240b },
-       { _MMIO(0x9888), 0x1058022f },
-       { _MMIO(0x9888), 0x185b5520 },
-       { _MMIO(0x9888), 0x198b0003 },
-       { _MMIO(0x9888), 0x005cc000 },
-       { _MMIO(0x9888), 0x065cc000 },
-       { _MMIO(0x9888), 0x085cc000 },
-       { _MMIO(0x9888), 0x0a5cc000 },
-       { _MMIO(0x9888), 0x0c5cc000 },
-       { _MMIO(0x9888), 0x0e5cc000 },
-       { _MMIO(0x9888), 0x025c4000 },
-       { _MMIO(0x9888), 0x045c8000 },
-       { _MMIO(0x9888), 0x003d0000 },
-       { _MMIO(0x9888), 0x063d00b0 },
-       { _MMIO(0x9888), 0x083d0182 },
-       { _MMIO(0x9888), 0x0a3d10a0 },
-       { _MMIO(0x9888), 0x0c3d11a2 },
-       { _MMIO(0x9888), 0x0e3d0000 },
-       { _MMIO(0x9888), 0x183d0000 },
-       { _MMIO(0x9888), 0x1a3d0000 },
-       { _MMIO(0x9888), 0x0e582242 },
-       { _MMIO(0x9888), 0x00586700 },
-       { _MMIO(0x9888), 0x0258004f },
-       { _MMIO(0x9888), 0x0658c000 },
-       { _MMIO(0x9888), 0x0858c000 },
-       { _MMIO(0x9888), 0x0a58c000 },
-       { _MMIO(0x9888), 0x0c58c000 },
-       { _MMIO(0x9888), 0x045b6300 },
-       { _MMIO(0x9888), 0x105b0000 },
-       { _MMIO(0x9888), 0x005b4000 },
-       { _MMIO(0x9888), 0x0e5b4000 },
-       { _MMIO(0x9888), 0x1a5b0155 },
-       { _MMIO(0x9888), 0x025b4000 },
-       { _MMIO(0x9888), 0x0a5b0000 },
-       { _MMIO(0x9888), 0x0c5b4000 },
-       { _MMIO(0x9888), 0x0c1fa800 },
-       { _MMIO(0x9888), 0x0e1faaa0 },
-       { _MMIO(0x9888), 0x101f02aa },
-       { _MMIO(0x9888), 0x00384000 },
-       { _MMIO(0x9888), 0x0e384000 },
-       { _MMIO(0x9888), 0x16384000 },
-       { _MMIO(0x9888), 0x18381555 },
-       { _MMIO(0x9888), 0x02384000 },
-       { _MMIO(0x9888), 0x04384000 },
-       { _MMIO(0x9888), 0x0a384000 },
-       { _MMIO(0x9888), 0x0c384000 },
-       { _MMIO(0x9888), 0x0039a000 },
-       { _MMIO(0x9888), 0x0639a000 },
-       { _MMIO(0x9888), 0x0839a000 },
-       { _MMIO(0x9888), 0x0a39a000 },
-       { _MMIO(0x9888), 0x0c39a000 },
-       { _MMIO(0x9888), 0x0e39a000 },
-       { _MMIO(0x9888), 0x02392000 },
-       { _MMIO(0x9888), 0x04398000 },
-       { _MMIO(0x9888), 0x018a8000 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x198a8000 },
-       { _MMIO(0x9888), 0x1b8aaaa0 },
-       { _MMIO(0x9888), 0x1d8a0002 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x0d8a8000 },
-       { _MMIO(0x9888), 0x038b6300 },
-       { _MMIO(0x9888), 0x058b0062 },
-       { _MMIO(0x9888), 0x118b0000 },
-       { _MMIO(0x9888), 0x238b02a0 },
-       { _MMIO(0x9888), 0x258b5555 },
-       { _MMIO(0x9888), 0x278b0015 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaaa },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x0784c000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x1780c000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d801000 },
-       { _MMIO(0x9888), 0x3d800000 },
-       { _MMIO(0x9888), 0x4f800001 },
-       { _MMIO(0x9888), 0x43800000 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800420 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800421 },
-       { _MMIO(0x9888), 0x41800041 },
-};
-
-static int
-get_data_port_reads_coalescing_mux_config(struct drm_i915_private *dev_priv,
-                                         const struct i915_oa_reg **regs,
-                                         int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
-               regs[n] = mux_config_data_port_reads_coalescing_0_subslices_0x01;
-               lens[n] = ARRAY_SIZE(mux_config_data_port_reads_coalescing_0_subslices_0x01);
-               n++;
-       }
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_data_port_writes_coalescing[] = {
-       { _MMIO(0x2724), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x274c), 0xba98ba98 },
-       { _MMIO(0x2748), 0xba98ba98 },
-       { _MMIO(0x2744), 0x00003377 },
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2770), 0x0007ff72 },
-       { _MMIO(0x2774), 0x0000bfd0 },
-       { _MMIO(0x2778), 0x0007ff62 },
-       { _MMIO(0x277c), 0x0000bfd0 },
-       { _MMIO(0x2780), 0x0007ff42 },
-       { _MMIO(0x2784), 0x0000bfd0 },
-       { _MMIO(0x2788), 0x0007ff02 },
-       { _MMIO(0x278c), 0x0000bfd0 },
-       { _MMIO(0x2790), 0x0005fff2 },
-       { _MMIO(0x2794), 0x0000bfd0 },
-       { _MMIO(0x2798), 0x0005ffe2 },
-       { _MMIO(0x279c), 0x0000bfd0 },
-       { _MMIO(0x27a0), 0x0005ffc2 },
-       { _MMIO(0x27a4), 0x0000bfd0 },
-       { _MMIO(0x27a8), 0x0005ff82 },
-       { _MMIO(0x27ac), 0x0000bfd0 },
-};
-
-static const struct i915_oa_reg flex_eu_config_data_port_writes_coalescing[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00000003 },
-       { _MMIO(0xe658), 0x00002001 },
-       { _MMIO(0xe758), 0x00778008 },
-       { _MMIO(0xe45c), 0x00088078 },
-       { _MMIO(0xe55c), 0x00808708 },
-       { _MMIO(0xe65c), 0x00a08908 },
-};
-
-static const struct i915_oa_reg mux_config_data_port_writes_coalescing_0_subslices_0x01[] = {
-       { _MMIO(0x9888), 0x103d0005 },
-       { _MMIO(0x9888), 0x143d0120 },
-       { _MMIO(0x9888), 0x163d2400 },
-       { _MMIO(0x9888), 0x1058022f },
-       { _MMIO(0x9888), 0x105b0000 },
-       { _MMIO(0x9888), 0x198b0003 },
-       { _MMIO(0x9888), 0x005cc000 },
-       { _MMIO(0x9888), 0x065cc000 },
-       { _MMIO(0x9888), 0x085cc000 },
-       { _MMIO(0x9888), 0x0a5cc000 },
-       { _MMIO(0x9888), 0x0e5cc000 },
-       { _MMIO(0x9888), 0x025c4000 },
-       { _MMIO(0x9888), 0x045c8000 },
-       { _MMIO(0x9888), 0x003d0000 },
-       { _MMIO(0x9888), 0x063d0094 },
-       { _MMIO(0x9888), 0x083d0182 },
-       { _MMIO(0x9888), 0x0a3d1814 },
-       { _MMIO(0x9888), 0x0e3d0000 },
-       { _MMIO(0x9888), 0x183d0000 },
-       { _MMIO(0x9888), 0x1a3d0000 },
-       { _MMIO(0x9888), 0x0c3d0000 },
-       { _MMIO(0x9888), 0x0e582242 },
-       { _MMIO(0x9888), 0x00586700 },
-       { _MMIO(0x9888), 0x0258004f },
-       { _MMIO(0x9888), 0x0658c000 },
-       { _MMIO(0x9888), 0x0858c000 },
-       { _MMIO(0x9888), 0x0a58c000 },
-       { _MMIO(0x9888), 0x045b6a80 },
-       { _MMIO(0x9888), 0x005b4000 },
-       { _MMIO(0x9888), 0x0e5b4000 },
-       { _MMIO(0x9888), 0x185b5400 },
-       { _MMIO(0x9888), 0x1a5b0141 },
-       { _MMIO(0x9888), 0x025b4000 },
-       { _MMIO(0x9888), 0x0a5b0000 },
-       { _MMIO(0x9888), 0x0c5b4000 },
-       { _MMIO(0x9888), 0x0c1fa800 },
-       { _MMIO(0x9888), 0x0e1faaa0 },
-       { _MMIO(0x9888), 0x101f0282 },
-       { _MMIO(0x9888), 0x00384000 },
-       { _MMIO(0x9888), 0x0e384000 },
-       { _MMIO(0x9888), 0x16384000 },
-       { _MMIO(0x9888), 0x18381415 },
-       { _MMIO(0x9888), 0x02384000 },
-       { _MMIO(0x9888), 0x04384000 },
-       { _MMIO(0x9888), 0x0a384000 },
-       { _MMIO(0x9888), 0x0c384000 },
-       { _MMIO(0x9888), 0x0039a000 },
-       { _MMIO(0x9888), 0x0639a000 },
-       { _MMIO(0x9888), 0x0839a000 },
-       { _MMIO(0x9888), 0x0a39a000 },
-       { _MMIO(0x9888), 0x0e39a000 },
-       { _MMIO(0x9888), 0x02392000 },
-       { _MMIO(0x9888), 0x04398000 },
-       { _MMIO(0x9888), 0x018a8000 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x198a8000 },
-       { _MMIO(0x9888), 0x1b8a82a0 },
-       { _MMIO(0x9888), 0x1d8a0002 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x0d8a8000 },
-       { _MMIO(0x9888), 0x038b6300 },
-       { _MMIO(0x9888), 0x058b0062 },
-       { _MMIO(0x9888), 0x118b0000 },
-       { _MMIO(0x9888), 0x238b02a0 },
-       { _MMIO(0x9888), 0x258b1555 },
-       { _MMIO(0x9888), 0x278b0014 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x21852aaa },
-       { _MMIO(0x9888), 0x23850028 },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830141 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x0784c000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x1780c000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0xd24), 0x00000000 },
-       { _MMIO(0x9888), 0x4d801000 },
-       { _MMIO(0x9888), 0x3d800000 },
-       { _MMIO(0x9888), 0x4f800001 },
-       { _MMIO(0x9888), 0x43800000 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x21800000 },
        { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800420 },
-       { _MMIO(0x9888), 0x3f800421 },
-       { _MMIO(0x9888), 0x41800041 },
+       { _MMIO(0x9840), 0x00000080 },
 };
 
-static int
-get_data_port_writes_coalescing_mux_config(struct drm_i915_private *dev_priv,
-                                          const struct i915_oa_reg **regs,
-                                          int *lens)
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
 {
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
-               regs[n] = mux_config_data_port_writes_coalescing_0_subslices_0x01;
-               lens[n] = ARRAY_SIZE(mux_config_data_port_writes_coalescing_0_subslices_0x01);
-               n++;
-       }
-
-       return n;
+       return sprintf(buf, "1\n");
 }
 
-static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0x10800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x00800000 },
-       { _MMIO(0x2770), 0x00000002 },
-       { _MMIO(0x2774), 0x0000fff7 },
-};
-
-static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
-       { _MMIO(0x9888), 0x105c0232 },
-       { _MMIO(0x9888), 0x10580232 },
-       { _MMIO(0x9888), 0x10380232 },
-       { _MMIO(0x9888), 0x10dc0232 },
-       { _MMIO(0x9888), 0x10d80232 },
-       { _MMIO(0x9888), 0x10b80232 },
-       { _MMIO(0x9888), 0x118e4400 },
-       { _MMIO(0x9888), 0x025c6080 },
-       { _MMIO(0x9888), 0x045c004b },
-       { _MMIO(0x9888), 0x005c8000 },
-       { _MMIO(0x9888), 0x00582080 },
-       { _MMIO(0x9888), 0x0258004b },
-       { _MMIO(0x9888), 0x025b4000 },
-       { _MMIO(0x9888), 0x045b4000 },
-       { _MMIO(0x9888), 0x0c1fa000 },
-       { _MMIO(0x9888), 0x0e1f00aa },
-       { _MMIO(0x9888), 0x04386080 },
-       { _MMIO(0x9888), 0x0638404b },
-       { _MMIO(0x9888), 0x02384000 },
-       { _MMIO(0x9888), 0x08384000 },
-       { _MMIO(0x9888), 0x0a380000 },
-       { _MMIO(0x9888), 0x0c380000 },
-       { _MMIO(0x9888), 0x00398000 },
-       { _MMIO(0x9888), 0x0239a000 },
-       { _MMIO(0x9888), 0x0439a000 },
-       { _MMIO(0x9888), 0x06392000 },
-       { _MMIO(0x9888), 0x0cdc25c1 },
-       { _MMIO(0x9888), 0x0adcc000 },
-       { _MMIO(0x9888), 0x0ad825c1 },
-       { _MMIO(0x9888), 0x18db4000 },
-       { _MMIO(0x9888), 0x1adb0001 },
-       { _MMIO(0x9888), 0x0e9f8000 },
-       { _MMIO(0x9888), 0x109f02aa },
-       { _MMIO(0x9888), 0x0eb825c1 },
-       { _MMIO(0x9888), 0x18b80154 },
-       { _MMIO(0x9888), 0x0ab9a000 },
-       { _MMIO(0x9888), 0x0cb9a000 },
-       { _MMIO(0x9888), 0x0eb9a000 },
-       { _MMIO(0x9888), 0x0d88c000 },
-       { _MMIO(0x9888), 0x0f88000f },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x078a8000 },
-       { _MMIO(0x9888), 0x098a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x0d8a8000 },
-       { _MMIO(0x9888), 0x258baa05 },
-       { _MMIO(0x9888), 0x278b002a },
-       { _MMIO(0x9888), 0x238b2a80 },
-       { _MMIO(0x9888), 0x198c5400 },
-       { _MMIO(0x9888), 0x1b8c0015 },
-       { _MMIO(0x9888), 0x098dc000 },
-       { _MMIO(0x9888), 0x0b8da000 },
-       { _MMIO(0x9888), 0x0d8da000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x098e05c0 },
-       { _MMIO(0x9888), 0x058e0000 },
-       { _MMIO(0x9888), 0x198f0020 },
-       { _MMIO(0x9888), 0x2185aa0a },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x1f85aa00 },
-       { _MMIO(0x9888), 0x19835000 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x09848000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x01848000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x07844000 },
-       { _MMIO(0x9888), 0x19808000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x11808000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x17804000 },
-       { _MMIO(0x9888), 0x51800040 },
-       { _MMIO(0x9888), 0x43800400 },
-       { _MMIO(0x9888), 0x45800800 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800c62 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3f801042 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x418014a4 },
-};
-
-static int
-get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
-                         const struct i915_oa_reg **regs,
-                         int *lens)
+void
+i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv)
 {
-       int n = 0;
+       strncpy(dev_priv->perf.oa.test_config.uuid,
+               "d6de6f55-e526-4f79-a6a6-d7315c09044e",
+               UUID_STRING_LEN);
+       dev_priv->perf.oa.test_config.id = 1;
 
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+       dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
+       dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
 
-       regs[n] = mux_config_hdc_and_sf;
-       lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
-       n++;
+       dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
+       dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
 
-       return n;
-}
+       dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
+       dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
 
-static const struct i915_oa_reg b_counter_config_l3_1[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0xf0800000 },
-       { _MMIO(0x2770), 0x00100070 },
-       { _MMIO(0x2774), 0x0000fff1 },
-       { _MMIO(0x2778), 0x00014002 },
-       { _MMIO(0x277c), 0x0000c3ff },
-       { _MMIO(0x2780), 0x00010002 },
-       { _MMIO(0x2784), 0x0000c7ff },
-       { _MMIO(0x2788), 0x00004002 },
-       { _MMIO(0x278c), 0x0000d3ff },
-       { _MMIO(0x2790), 0x00100700 },
-       { _MMIO(0x2794), 0x0000ff1f },
-       { _MMIO(0x2798), 0x00001402 },
-       { _MMIO(0x279c), 0x0000fc3f },
-       { _MMIO(0x27a0), 0x00001002 },
-       { _MMIO(0x27a4), 0x0000fc7f },
-       { _MMIO(0x27a8), 0x00000402 },
-       { _MMIO(0x27ac), 0x0000fd3f },
-};
+       dev_priv->perf.oa.test_config.sysfs_metric.name = "d6de6f55-e526-4f79-a6a6-d7315c09044e";
+       dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
 
-static const struct i915_oa_reg flex_eu_config_l3_1[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_l3_1[] = {
-       { _MMIO(0x9888), 0x10bf03da },
-       { _MMIO(0x9888), 0x14bf0001 },
-       { _MMIO(0x9888), 0x12980340 },
-       { _MMIO(0x9888), 0x12990340 },
-       { _MMIO(0x9888), 0x0cbf1187 },
-       { _MMIO(0x9888), 0x0ebf1205 },
-       { _MMIO(0x9888), 0x00bf0500 },
-       { _MMIO(0x9888), 0x02bf042b },
-       { _MMIO(0x9888), 0x04bf002c },
-       { _MMIO(0x9888), 0x0cdac000 },
-       { _MMIO(0x9888), 0x0edac000 },
-       { _MMIO(0x9888), 0x00da8000 },
-       { _MMIO(0x9888), 0x02dac000 },
-       { _MMIO(0x9888), 0x04da4000 },
-       { _MMIO(0x9888), 0x04983400 },
-       { _MMIO(0x9888), 0x10980000 },
-       { _MMIO(0x9888), 0x06990034 },
-       { _MMIO(0x9888), 0x10990000 },
-       { _MMIO(0x9888), 0x0c9dc000 },
-       { _MMIO(0x9888), 0x0e9dc000 },
-       { _MMIO(0x9888), 0x009d8000 },
-       { _MMIO(0x9888), 0x029dc000 },
-       { _MMIO(0x9888), 0x049d4000 },
-       { _MMIO(0x9888), 0x109f02a8 },
-       { _MMIO(0x9888), 0x0c9fa000 },
-       { _MMIO(0x9888), 0x0e9f00ba },
-       { _MMIO(0x9888), 0x0cb88000 },
-       { _MMIO(0x9888), 0x0cb95000 },
-       { _MMIO(0x9888), 0x0eb95000 },
-       { _MMIO(0x9888), 0x00b94000 },
-       { _MMIO(0x9888), 0x02b95000 },
-       { _MMIO(0x9888), 0x04b91000 },
-       { _MMIO(0x9888), 0x06b92000 },
-       { _MMIO(0x9888), 0x0cba4000 },
-       { _MMIO(0x9888), 0x0f88000f },
-       { _MMIO(0x9888), 0x03888000 },
-       { _MMIO(0x9888), 0x05888000 },
-       { _MMIO(0x9888), 0x07888000 },
-       { _MMIO(0x9888), 0x09888000 },
-       { _MMIO(0x9888), 0x0b888000 },
-       { _MMIO(0x9888), 0x0d880400 },
-       { _MMIO(0x9888), 0x258b800a },
-       { _MMIO(0x9888), 0x278b002a },
-       { _MMIO(0x9888), 0x238b5500 },
-       { _MMIO(0x9888), 0x198c4000 },
-       { _MMIO(0x9888), 0x1b8c0015 },
-       { _MMIO(0x9888), 0x038c4000 },
-       { _MMIO(0x9888), 0x058c4000 },
-       { _MMIO(0x9888), 0x078c4000 },
-       { _MMIO(0x9888), 0x098c4000 },
-       { _MMIO(0x9888), 0x0b8c4000 },
-       { _MMIO(0x9888), 0x0d8c4000 },
-       { _MMIO(0x9888), 0x0d8da000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x018d8000 },
-       { _MMIO(0x9888), 0x038da000 },
-       { _MMIO(0x9888), 0x058da000 },
-       { _MMIO(0x9888), 0x078d2000 },
-       { _MMIO(0x9888), 0x2185800a },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x1f85aa00 },
-       { _MMIO(0x9888), 0x1b830154 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x01848000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x07844000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x11808000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x17804000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x47800000 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3f800000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x41800060 },
-};
-
-static int
-get_l3_1_mux_config(struct drm_i915_private *dev_priv,
-                   const struct i915_oa_reg **regs,
-                   int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_l3_1;
-       lens[n] = ARRAY_SIZE(mux_config_l3_1);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_l3_2[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0xf0800000 },
-       { _MMIO(0x2770), 0x00100070 },
-       { _MMIO(0x2774), 0x0000fff1 },
-       { _MMIO(0x2778), 0x00014002 },
-       { _MMIO(0x277c), 0x0000c3ff },
-       { _MMIO(0x2780), 0x00010002 },
-       { _MMIO(0x2784), 0x0000c7ff },
-       { _MMIO(0x2788), 0x00004002 },
-       { _MMIO(0x278c), 0x0000d3ff },
-       { _MMIO(0x2790), 0x00100700 },
-       { _MMIO(0x2794), 0x0000ff1f },
-       { _MMIO(0x2798), 0x00001402 },
-       { _MMIO(0x279c), 0x0000fc3f },
-       { _MMIO(0x27a0), 0x00001002 },
-       { _MMIO(0x27a4), 0x0000fc7f },
-       { _MMIO(0x27a8), 0x00000402 },
-       { _MMIO(0x27ac), 0x0000fd3f },
-};
-
-static const struct i915_oa_reg flex_eu_config_l3_2[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_l3_2[] = {
-       { _MMIO(0x9888), 0x103f03da },
-       { _MMIO(0x9888), 0x143f0001 },
-       { _MMIO(0x9888), 0x12180340 },
-       { _MMIO(0x9888), 0x12190340 },
-       { _MMIO(0x9888), 0x0c3f1187 },
-       { _MMIO(0x9888), 0x0e3f1205 },
-       { _MMIO(0x9888), 0x003f0500 },
-       { _MMIO(0x9888), 0x023f042b },
-       { _MMIO(0x9888), 0x043f002c },
-       { _MMIO(0x9888), 0x0c5ac000 },
-       { _MMIO(0x9888), 0x0e5ac000 },
-       { _MMIO(0x9888), 0x005a8000 },
-       { _MMIO(0x9888), 0x025ac000 },
-       { _MMIO(0x9888), 0x045a4000 },
-       { _MMIO(0x9888), 0x04183400 },
-       { _MMIO(0x9888), 0x10180000 },
-       { _MMIO(0x9888), 0x06190034 },
-       { _MMIO(0x9888), 0x10190000 },
-       { _MMIO(0x9888), 0x0c1dc000 },
-       { _MMIO(0x9888), 0x0e1dc000 },
-       { _MMIO(0x9888), 0x001d8000 },
-       { _MMIO(0x9888), 0x021dc000 },
-       { _MMIO(0x9888), 0x041d4000 },
-       { _MMIO(0x9888), 0x101f02a8 },
-       { _MMIO(0x9888), 0x0c1fa000 },
-       { _MMIO(0x9888), 0x0e1f00ba },
-       { _MMIO(0x9888), 0x0c388000 },
-       { _MMIO(0x9888), 0x0c395000 },
-       { _MMIO(0x9888), 0x0e395000 },
-       { _MMIO(0x9888), 0x00394000 },
-       { _MMIO(0x9888), 0x02395000 },
-       { _MMIO(0x9888), 0x04391000 },
-       { _MMIO(0x9888), 0x06392000 },
-       { _MMIO(0x9888), 0x0c3a4000 },
-       { _MMIO(0x9888), 0x1b8aa800 },
-       { _MMIO(0x9888), 0x1d8a0002 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x078a8000 },
-       { _MMIO(0x9888), 0x098a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x0d8a8000 },
-       { _MMIO(0x9888), 0x258b4005 },
-       { _MMIO(0x9888), 0x278b0015 },
-       { _MMIO(0x9888), 0x238b2a80 },
-       { _MMIO(0x9888), 0x2185800a },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x1f85aa00 },
-       { _MMIO(0x9888), 0x1b830154 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x01848000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x07844000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x11808000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x17804000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x45800000 },
-       { _MMIO(0x9888), 0x47800000 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3f800000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x41800060 },
-};
-
-static int
-get_l3_2_mux_config(struct drm_i915_private *dev_priv,
-                   const struct i915_oa_reg **regs,
-                   int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_l3_2;
-       lens[n] = ARRAY_SIZE(mux_config_l3_2);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_l3_3[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0xf0800000 },
-       { _MMIO(0x2770), 0x00100070 },
-       { _MMIO(0x2774), 0x0000fff1 },
-       { _MMIO(0x2778), 0x00014002 },
-       { _MMIO(0x277c), 0x0000c3ff },
-       { _MMIO(0x2780), 0x00010002 },
-       { _MMIO(0x2784), 0x0000c7ff },
-       { _MMIO(0x2788), 0x00004002 },
-       { _MMIO(0x278c), 0x0000d3ff },
-       { _MMIO(0x2790), 0x00100700 },
-       { _MMIO(0x2794), 0x0000ff1f },
-       { _MMIO(0x2798), 0x00001402 },
-       { _MMIO(0x279c), 0x0000fc3f },
-       { _MMIO(0x27a0), 0x00001002 },
-       { _MMIO(0x27a4), 0x0000fc7f },
-       { _MMIO(0x27a8), 0x00000402 },
-       { _MMIO(0x27ac), 0x0000fd3f },
-};
-
-static const struct i915_oa_reg flex_eu_config_l3_3[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_l3_3[] = {
-       { _MMIO(0x9888), 0x121b0340 },
-       { _MMIO(0x9888), 0x103f0274 },
-       { _MMIO(0x9888), 0x123f0000 },
-       { _MMIO(0x9888), 0x129b0340 },
-       { _MMIO(0x9888), 0x10bf0274 },
-       { _MMIO(0x9888), 0x12bf0000 },
-       { _MMIO(0x9888), 0x041b3400 },
-       { _MMIO(0x9888), 0x101b0000 },
-       { _MMIO(0x9888), 0x045c8000 },
-       { _MMIO(0x9888), 0x0a3d4000 },
-       { _MMIO(0x9888), 0x003f0080 },
-       { _MMIO(0x9888), 0x023f0793 },
-       { _MMIO(0x9888), 0x043f0014 },
-       { _MMIO(0x9888), 0x04588000 },
-       { _MMIO(0x9888), 0x005a8000 },
-       { _MMIO(0x9888), 0x025ac000 },
-       { _MMIO(0x9888), 0x045a4000 },
-       { _MMIO(0x9888), 0x0a5b4000 },
-       { _MMIO(0x9888), 0x001d8000 },
-       { _MMIO(0x9888), 0x021dc000 },
-       { _MMIO(0x9888), 0x041d4000 },
-       { _MMIO(0x9888), 0x0c1fa000 },
-       { _MMIO(0x9888), 0x0e1f002a },
-       { _MMIO(0x9888), 0x0a384000 },
-       { _MMIO(0x9888), 0x00394000 },
-       { _MMIO(0x9888), 0x02395000 },
-       { _MMIO(0x9888), 0x04399000 },
-       { _MMIO(0x9888), 0x069b0034 },
-       { _MMIO(0x9888), 0x109b0000 },
-       { _MMIO(0x9888), 0x06dc4000 },
-       { _MMIO(0x9888), 0x0cbd4000 },
-       { _MMIO(0x9888), 0x0cbf0981 },
-       { _MMIO(0x9888), 0x0ebf0a0f },
-       { _MMIO(0x9888), 0x06d84000 },
-       { _MMIO(0x9888), 0x0cdac000 },
-       { _MMIO(0x9888), 0x0edac000 },
-       { _MMIO(0x9888), 0x0cdb4000 },
-       { _MMIO(0x9888), 0x0c9dc000 },
-       { _MMIO(0x9888), 0x0e9dc000 },
-       { _MMIO(0x9888), 0x109f02a8 },
-       { _MMIO(0x9888), 0x0e9f0080 },
-       { _MMIO(0x9888), 0x0cb84000 },
-       { _MMIO(0x9888), 0x0cb95000 },
-       { _MMIO(0x9888), 0x0eb95000 },
-       { _MMIO(0x9888), 0x06b92000 },
-       { _MMIO(0x9888), 0x0f88000f },
-       { _MMIO(0x9888), 0x0d880400 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x078a8000 },
-       { _MMIO(0x9888), 0x098a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x258b8009 },
-       { _MMIO(0x9888), 0x278b002a },
-       { _MMIO(0x9888), 0x238b2a80 },
-       { _MMIO(0x9888), 0x198c4000 },
-       { _MMIO(0x9888), 0x1b8c0015 },
-       { _MMIO(0x9888), 0x0d8c4000 },
-       { _MMIO(0x9888), 0x0d8da000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x078d2000 },
-       { _MMIO(0x9888), 0x2185800a },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x1f85aa00 },
-       { _MMIO(0x9888), 0x1b830154 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x01848000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x07844000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x11808000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x17804000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x45800c00 },
-       { _MMIO(0x9888), 0x47800c63 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3f8014a5 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x41800045 },
-};
-
-static int
-get_l3_3_mux_config(struct drm_i915_private *dev_priv,
-                   const struct i915_oa_reg **regs,
-                   int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_l3_3;
-       lens[n] = ARRAY_SIZE(mux_config_l3_3);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_l3_4[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0xf0800000 },
-       { _MMIO(0x2770), 0x00100070 },
-       { _MMIO(0x2774), 0x0000fff1 },
-       { _MMIO(0x2778), 0x00014002 },
-       { _MMIO(0x277c), 0x0000c3ff },
-       { _MMIO(0x2780), 0x00010002 },
-       { _MMIO(0x2784), 0x0000c7ff },
-       { _MMIO(0x2788), 0x00004002 },
-       { _MMIO(0x278c), 0x0000d3ff },
-       { _MMIO(0x2790), 0x00100700 },
-       { _MMIO(0x2794), 0x0000ff1f },
-       { _MMIO(0x2798), 0x00001402 },
-       { _MMIO(0x279c), 0x0000fc3f },
-       { _MMIO(0x27a0), 0x00001002 },
-       { _MMIO(0x27a4), 0x0000fc7f },
-       { _MMIO(0x27a8), 0x00000402 },
-       { _MMIO(0x27ac), 0x0000fd3f },
-};
-
-static const struct i915_oa_reg flex_eu_config_l3_4[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_l3_4[] = {
-       { _MMIO(0x9888), 0x121a0340 },
-       { _MMIO(0x9888), 0x103f0017 },
-       { _MMIO(0x9888), 0x123f0020 },
-       { _MMIO(0x9888), 0x129a0340 },
-       { _MMIO(0x9888), 0x10bf0017 },
-       { _MMIO(0x9888), 0x12bf0020 },
-       { _MMIO(0x9888), 0x041a3400 },
-       { _MMIO(0x9888), 0x101a0000 },
-       { _MMIO(0x9888), 0x043b8000 },
-       { _MMIO(0x9888), 0x0a3e0010 },
-       { _MMIO(0x9888), 0x003f0200 },
-       { _MMIO(0x9888), 0x023f0113 },
-       { _MMIO(0x9888), 0x043f0014 },
-       { _MMIO(0x9888), 0x02592000 },
-       { _MMIO(0x9888), 0x005a8000 },
-       { _MMIO(0x9888), 0x025ac000 },
-       { _MMIO(0x9888), 0x045a4000 },
-       { _MMIO(0x9888), 0x0a1c8000 },
-       { _MMIO(0x9888), 0x001d8000 },
-       { _MMIO(0x9888), 0x021dc000 },
-       { _MMIO(0x9888), 0x041d4000 },
-       { _MMIO(0x9888), 0x0a1e8000 },
-       { _MMIO(0x9888), 0x0c1fa000 },
-       { _MMIO(0x9888), 0x0e1f001a },
-       { _MMIO(0x9888), 0x00394000 },
-       { _MMIO(0x9888), 0x02395000 },
-       { _MMIO(0x9888), 0x04391000 },
-       { _MMIO(0x9888), 0x069a0034 },
-       { _MMIO(0x9888), 0x109a0000 },
-       { _MMIO(0x9888), 0x06bb4000 },
-       { _MMIO(0x9888), 0x0abe0040 },
-       { _MMIO(0x9888), 0x0cbf0984 },
-       { _MMIO(0x9888), 0x0ebf0a02 },
-       { _MMIO(0x9888), 0x02d94000 },
-       { _MMIO(0x9888), 0x0cdac000 },
-       { _MMIO(0x9888), 0x0edac000 },
-       { _MMIO(0x9888), 0x0c9c0400 },
-       { _MMIO(0x9888), 0x0c9dc000 },
-       { _MMIO(0x9888), 0x0e9dc000 },
-       { _MMIO(0x9888), 0x0c9e0400 },
-       { _MMIO(0x9888), 0x109f02a8 },
-       { _MMIO(0x9888), 0x0e9f0040 },
-       { _MMIO(0x9888), 0x0cb95000 },
-       { _MMIO(0x9888), 0x0eb95000 },
-       { _MMIO(0x9888), 0x0f88000f },
-       { _MMIO(0x9888), 0x0d880400 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x078a8000 },
-       { _MMIO(0x9888), 0x098a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x258b8009 },
-       { _MMIO(0x9888), 0x278b002a },
-       { _MMIO(0x9888), 0x238b2a80 },
-       { _MMIO(0x9888), 0x198c4000 },
-       { _MMIO(0x9888), 0x1b8c0015 },
-       { _MMIO(0x9888), 0x0d8c4000 },
-       { _MMIO(0x9888), 0x0d8da000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x078d2000 },
-       { _MMIO(0x9888), 0x2185800a },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x1f85aa00 },
-       { _MMIO(0x9888), 0x1b830154 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x01848000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x07844000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x11808000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x17804000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x45800800 },
-       { _MMIO(0x9888), 0x47800842 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3f801084 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x41800044 },
-};
-
-static int
-get_l3_4_mux_config(struct drm_i915_private *dev_priv,
-                   const struct i915_oa_reg **regs,
-                   int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_l3_4;
-       lens[n] = ARRAY_SIZE(mux_config_l3_4);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x30800000 },
-       { _MMIO(0x2770), 0x00006000 },
-       { _MMIO(0x2774), 0x0000f3ff },
-       { _MMIO(0x2778), 0x00001800 },
-       { _MMIO(0x277c), 0x0000fcff },
-       { _MMIO(0x2780), 0x00000600 },
-       { _MMIO(0x2784), 0x0000ff3f },
-       { _MMIO(0x2788), 0x00000180 },
-       { _MMIO(0x278c), 0x0000ffcf },
-       { _MMIO(0x2790), 0x00000060 },
-       { _MMIO(0x2794), 0x0000fff3 },
-       { _MMIO(0x2798), 0x00000018 },
-       { _MMIO(0x279c), 0x0000fffc },
-};
-
-static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
-       { _MMIO(0x9888), 0x143b000e },
-       { _MMIO(0x9888), 0x043c55c0 },
-       { _MMIO(0x9888), 0x0a1e0280 },
-       { _MMIO(0x9888), 0x0c1e0408 },
-       { _MMIO(0x9888), 0x10390000 },
-       { _MMIO(0x9888), 0x12397a1f },
-       { _MMIO(0x9888), 0x14bb000e },
-       { _MMIO(0x9888), 0x04bc5000 },
-       { _MMIO(0x9888), 0x0a9e0296 },
-       { _MMIO(0x9888), 0x0c9e0008 },
-       { _MMIO(0x9888), 0x10b90000 },
-       { _MMIO(0x9888), 0x12b97a1f },
-       { _MMIO(0x9888), 0x063b0042 },
-       { _MMIO(0x9888), 0x103b0000 },
-       { _MMIO(0x9888), 0x083c0000 },
-       { _MMIO(0x9888), 0x0a3e0040 },
-       { _MMIO(0x9888), 0x043f8000 },
-       { _MMIO(0x9888), 0x02594000 },
-       { _MMIO(0x9888), 0x045a8000 },
-       { _MMIO(0x9888), 0x0c1c0400 },
-       { _MMIO(0x9888), 0x041d8000 },
-       { _MMIO(0x9888), 0x081e02c0 },
-       { _MMIO(0x9888), 0x0e1e0000 },
-       { _MMIO(0x9888), 0x0c1fa800 },
-       { _MMIO(0x9888), 0x0e1f0260 },
-       { _MMIO(0x9888), 0x101f0014 },
-       { _MMIO(0x9888), 0x003905e0 },
-       { _MMIO(0x9888), 0x06390bc0 },
-       { _MMIO(0x9888), 0x02390018 },
-       { _MMIO(0x9888), 0x04394000 },
-       { _MMIO(0x9888), 0x04bb0042 },
-       { _MMIO(0x9888), 0x10bb0000 },
-       { _MMIO(0x9888), 0x02bc05c0 },
-       { _MMIO(0x9888), 0x08bc0000 },
-       { _MMIO(0x9888), 0x0abe0004 },
-       { _MMIO(0x9888), 0x02bf8000 },
-       { _MMIO(0x9888), 0x02d91000 },
-       { _MMIO(0x9888), 0x02da8000 },
-       { _MMIO(0x9888), 0x089c8000 },
-       { _MMIO(0x9888), 0x029d8000 },
-       { _MMIO(0x9888), 0x089e8000 },
-       { _MMIO(0x9888), 0x0e9e0000 },
-       { _MMIO(0x9888), 0x0e9fa806 },
-       { _MMIO(0x9888), 0x109f0142 },
-       { _MMIO(0x9888), 0x08b90617 },
-       { _MMIO(0x9888), 0x0ab90be0 },
-       { _MMIO(0x9888), 0x02b94000 },
-       { _MMIO(0x9888), 0x0d88f000 },
-       { _MMIO(0x9888), 0x0f88000c },
-       { _MMIO(0x9888), 0x07888000 },
-       { _MMIO(0x9888), 0x09888000 },
-       { _MMIO(0x9888), 0x018a8000 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x1b8a2800 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x0d8a8000 },
-       { _MMIO(0x9888), 0x238b52a0 },
-       { _MMIO(0x9888), 0x258b6a95 },
-       { _MMIO(0x9888), 0x278b0029 },
-       { _MMIO(0x9888), 0x178c2000 },
-       { _MMIO(0x9888), 0x198c1500 },
-       { _MMIO(0x9888), 0x1b8c0014 },
-       { _MMIO(0x9888), 0x078c4000 },
-       { _MMIO(0x9888), 0x098c4000 },
-       { _MMIO(0x9888), 0x098da000 },
-       { _MMIO(0x9888), 0x0b8da000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x038d8000 },
-       { _MMIO(0x9888), 0x058d2000 },
-       { _MMIO(0x9888), 0x1f85aa80 },
-       { _MMIO(0x9888), 0x2185aaaa },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0184c000 },
-       { _MMIO(0x9888), 0x0784c000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1180c000 },
-       { _MMIO(0x9888), 0x1780c000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x4d800444 },
-       { _MMIO(0x9888), 0x3d800000 },
-       { _MMIO(0x9888), 0x4f804000 },
-       { _MMIO(0x9888), 0x43801080 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800084 },
-       { _MMIO(0x9888), 0x53800044 },
-       { _MMIO(0x9888), 0x47801080 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x3f800000 },
-       { _MMIO(0x9888), 0x41800840 },
-};
-
-static int
-get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
-                                           const struct i915_oa_reg **regs,
-                                           int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_rasterizer_and_pixel_backend;
-       lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_sampler_1[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0x70800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x00800000 },
-       { _MMIO(0x2770), 0x0000c000 },
-       { _MMIO(0x2774), 0x0000e7ff },
-       { _MMIO(0x2778), 0x00003000 },
-       { _MMIO(0x277c), 0x0000f9ff },
-       { _MMIO(0x2780), 0x00000c00 },
-       { _MMIO(0x2784), 0x0000fe7f },
-};
-
-static const struct i915_oa_reg flex_eu_config_sampler_1[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_sampler_1[] = {
-       { _MMIO(0x9888), 0x18921400 },
-       { _MMIO(0x9888), 0x149500ab },
-       { _MMIO(0x9888), 0x18b21400 },
-       { _MMIO(0x9888), 0x14b500ab },
-       { _MMIO(0x9888), 0x18d21400 },
-       { _MMIO(0x9888), 0x14d500ab },
-       { _MMIO(0x9888), 0x0cdc8000 },
-       { _MMIO(0x9888), 0x0edc4000 },
-       { _MMIO(0x9888), 0x02dcc000 },
-       { _MMIO(0x9888), 0x04dcc000 },
-       { _MMIO(0x9888), 0x1abd00a0 },
-       { _MMIO(0x9888), 0x0abd8000 },
-       { _MMIO(0x9888), 0x0cd88000 },
-       { _MMIO(0x9888), 0x0ed84000 },
-       { _MMIO(0x9888), 0x04d88000 },
-       { _MMIO(0x9888), 0x1adb0050 },
-       { _MMIO(0x9888), 0x04db8000 },
-       { _MMIO(0x9888), 0x06db8000 },
-       { _MMIO(0x9888), 0x08db8000 },
-       { _MMIO(0x9888), 0x0adb4000 },
-       { _MMIO(0x9888), 0x109f02a0 },
-       { _MMIO(0x9888), 0x0c9fa000 },
-       { _MMIO(0x9888), 0x0e9f00aa },
-       { _MMIO(0x9888), 0x18b82500 },
-       { _MMIO(0x9888), 0x02b88000 },
-       { _MMIO(0x9888), 0x04b84000 },
-       { _MMIO(0x9888), 0x06b84000 },
-       { _MMIO(0x9888), 0x08b84000 },
-       { _MMIO(0x9888), 0x0ab84000 },
-       { _MMIO(0x9888), 0x0cb88000 },
-       { _MMIO(0x9888), 0x0cb98000 },
-       { _MMIO(0x9888), 0x0eb9a000 },
-       { _MMIO(0x9888), 0x00b98000 },
-       { _MMIO(0x9888), 0x02b9a000 },
-       { _MMIO(0x9888), 0x04b9a000 },
-       { _MMIO(0x9888), 0x06b92000 },
-       { _MMIO(0x9888), 0x1aba0200 },
-       { _MMIO(0x9888), 0x02ba8000 },
-       { _MMIO(0x9888), 0x0cba8000 },
-       { _MMIO(0x9888), 0x04908000 },
-       { _MMIO(0x9888), 0x04918000 },
-       { _MMIO(0x9888), 0x04927300 },
-       { _MMIO(0x9888), 0x10920000 },
-       { _MMIO(0x9888), 0x1893000a },
-       { _MMIO(0x9888), 0x0a934000 },
-       { _MMIO(0x9888), 0x0a946000 },
-       { _MMIO(0x9888), 0x0c959000 },
-       { _MMIO(0x9888), 0x0e950098 },
-       { _MMIO(0x9888), 0x10950000 },
-       { _MMIO(0x9888), 0x04b04000 },
-       { _MMIO(0x9888), 0x04b14000 },
-       { _MMIO(0x9888), 0x04b20073 },
-       { _MMIO(0x9888), 0x10b20000 },
-       { _MMIO(0x9888), 0x04b38000 },
-       { _MMIO(0x9888), 0x06b38000 },
-       { _MMIO(0x9888), 0x08b34000 },
-       { _MMIO(0x9888), 0x04b4c000 },
-       { _MMIO(0x9888), 0x02b59890 },
-       { _MMIO(0x9888), 0x10b50000 },
-       { _MMIO(0x9888), 0x06d04000 },
-       { _MMIO(0x9888), 0x06d14000 },
-       { _MMIO(0x9888), 0x06d20073 },
-       { _MMIO(0x9888), 0x10d20000 },
-       { _MMIO(0x9888), 0x18d30020 },
-       { _MMIO(0x9888), 0x02d38000 },
-       { _MMIO(0x9888), 0x0cd34000 },
-       { _MMIO(0x9888), 0x0ad48000 },
-       { _MMIO(0x9888), 0x04d42000 },
-       { _MMIO(0x9888), 0x0ed59000 },
-       { _MMIO(0x9888), 0x00d59800 },
-       { _MMIO(0x9888), 0x10d50000 },
-       { _MMIO(0x9888), 0x0f88000e },
-       { _MMIO(0x9888), 0x03888000 },
-       { _MMIO(0x9888), 0x05888000 },
-       { _MMIO(0x9888), 0x07888000 },
-       { _MMIO(0x9888), 0x09888000 },
-       { _MMIO(0x9888), 0x0b888000 },
-       { _MMIO(0x9888), 0x0d880400 },
-       { _MMIO(0x9888), 0x278b002a },
-       { _MMIO(0x9888), 0x238b5500 },
-       { _MMIO(0x9888), 0x258b000a },
-       { _MMIO(0x9888), 0x1b8c0015 },
-       { _MMIO(0x9888), 0x038c4000 },
-       { _MMIO(0x9888), 0x058c4000 },
-       { _MMIO(0x9888), 0x078c4000 },
-       { _MMIO(0x9888), 0x098c4000 },
-       { _MMIO(0x9888), 0x0b8c4000 },
-       { _MMIO(0x9888), 0x0d8c4000 },
-       { _MMIO(0x9888), 0x0d8d8000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x018d8000 },
-       { _MMIO(0x9888), 0x038da000 },
-       { _MMIO(0x9888), 0x058da000 },
-       { _MMIO(0x9888), 0x078d2000 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x1f85aa00 },
-       { _MMIO(0x9888), 0x2185000a },
-       { _MMIO(0x9888), 0x1b830150 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0d848000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x01848000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x07844000 },
-       { _MMIO(0x9888), 0x1d808000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x11808000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x17804000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47801021 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3f800c64 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x41800c02 },
-};
-
-static int
-get_sampler_1_mux_config(struct drm_i915_private *dev_priv,
-                        const struct i915_oa_reg **regs,
-                        int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_sampler_1;
-       lens[n] = ARRAY_SIZE(mux_config_sampler_1);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_sampler_2[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0x70800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x00800000 },
-       { _MMIO(0x2770), 0x0000c000 },
-       { _MMIO(0x2774), 0x0000e7ff },
-       { _MMIO(0x2778), 0x00003000 },
-       { _MMIO(0x277c), 0x0000f9ff },
-       { _MMIO(0x2780), 0x00000c00 },
-       { _MMIO(0x2784), 0x0000fe7f },
-};
-
-static const struct i915_oa_reg flex_eu_config_sampler_2[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_sampler_2[] = {
-       { _MMIO(0x9888), 0x18121400 },
-       { _MMIO(0x9888), 0x141500ab },
-       { _MMIO(0x9888), 0x18321400 },
-       { _MMIO(0x9888), 0x143500ab },
-       { _MMIO(0x9888), 0x18521400 },
-       { _MMIO(0x9888), 0x145500ab },
-       { _MMIO(0x9888), 0x0c5c8000 },
-       { _MMIO(0x9888), 0x0e5c4000 },
-       { _MMIO(0x9888), 0x025cc000 },
-       { _MMIO(0x9888), 0x045cc000 },
-       { _MMIO(0x9888), 0x1a3d00a0 },
-       { _MMIO(0x9888), 0x0a3d8000 },
-       { _MMIO(0x9888), 0x0c588000 },
-       { _MMIO(0x9888), 0x0e584000 },
-       { _MMIO(0x9888), 0x04588000 },
-       { _MMIO(0x9888), 0x1a5b0050 },
-       { _MMIO(0x9888), 0x045b8000 },
-       { _MMIO(0x9888), 0x065b8000 },
-       { _MMIO(0x9888), 0x085b8000 },
-       { _MMIO(0x9888), 0x0a5b4000 },
-       { _MMIO(0x9888), 0x101f02a0 },
-       { _MMIO(0x9888), 0x0c1fa000 },
-       { _MMIO(0x9888), 0x0e1f00aa },
-       { _MMIO(0x9888), 0x18382500 },
-       { _MMIO(0x9888), 0x02388000 },
-       { _MMIO(0x9888), 0x04384000 },
-       { _MMIO(0x9888), 0x06384000 },
-       { _MMIO(0x9888), 0x08384000 },
-       { _MMIO(0x9888), 0x0a384000 },
-       { _MMIO(0x9888), 0x0c388000 },
-       { _MMIO(0x9888), 0x0c398000 },
-       { _MMIO(0x9888), 0x0e39a000 },
-       { _MMIO(0x9888), 0x00398000 },
-       { _MMIO(0x9888), 0x0239a000 },
-       { _MMIO(0x9888), 0x0439a000 },
-       { _MMIO(0x9888), 0x06392000 },
-       { _MMIO(0x9888), 0x1a3a0200 },
-       { _MMIO(0x9888), 0x023a8000 },
-       { _MMIO(0x9888), 0x0c3a8000 },
-       { _MMIO(0x9888), 0x04108000 },
-       { _MMIO(0x9888), 0x04118000 },
-       { _MMIO(0x9888), 0x04127300 },
-       { _MMIO(0x9888), 0x10120000 },
-       { _MMIO(0x9888), 0x1813000a },
-       { _MMIO(0x9888), 0x0a134000 },
-       { _MMIO(0x9888), 0x0a146000 },
-       { _MMIO(0x9888), 0x0c159000 },
-       { _MMIO(0x9888), 0x0e150098 },
-       { _MMIO(0x9888), 0x10150000 },
-       { _MMIO(0x9888), 0x04304000 },
-       { _MMIO(0x9888), 0x04314000 },
-       { _MMIO(0x9888), 0x04320073 },
-       { _MMIO(0x9888), 0x10320000 },
-       { _MMIO(0x9888), 0x04338000 },
-       { _MMIO(0x9888), 0x06338000 },
-       { _MMIO(0x9888), 0x08334000 },
-       { _MMIO(0x9888), 0x0434c000 },
-       { _MMIO(0x9888), 0x02359890 },
-       { _MMIO(0x9888), 0x10350000 },
-       { _MMIO(0x9888), 0x06504000 },
-       { _MMIO(0x9888), 0x06514000 },
-       { _MMIO(0x9888), 0x06520073 },
-       { _MMIO(0x9888), 0x10520000 },
-       { _MMIO(0x9888), 0x18530020 },
-       { _MMIO(0x9888), 0x02538000 },
-       { _MMIO(0x9888), 0x0c534000 },
-       { _MMIO(0x9888), 0x0a548000 },
-       { _MMIO(0x9888), 0x04542000 },
-       { _MMIO(0x9888), 0x0e559000 },
-       { _MMIO(0x9888), 0x00559800 },
-       { _MMIO(0x9888), 0x10550000 },
-       { _MMIO(0x9888), 0x1b8aa000 },
-       { _MMIO(0x9888), 0x1d8a0002 },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x078a8000 },
-       { _MMIO(0x9888), 0x098a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x0d8a8000 },
-       { _MMIO(0x9888), 0x278b0015 },
-       { _MMIO(0x9888), 0x238b2a80 },
-       { _MMIO(0x9888), 0x258b0005 },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x1f85aa00 },
-       { _MMIO(0x9888), 0x2185000a },
-       { _MMIO(0x9888), 0x1b830150 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0d848000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x01848000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x07844000 },
-       { _MMIO(0x9888), 0x1d808000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x11808000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x17804000 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47801021 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3f800c64 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x41800c02 },
-};
-
-static int
-get_sampler_2_mux_config(struct drm_i915_private *dev_priv,
-                        const struct i915_oa_reg **regs,
-                        int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_sampler_2;
-       lens[n] = ARRAY_SIZE(mux_config_sampler_2);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_tdl_1[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x30800000 },
-       { _MMIO(0x2770), 0x00000002 },
-       { _MMIO(0x2774), 0x0000fdff },
-       { _MMIO(0x2778), 0x00000000 },
-       { _MMIO(0x277c), 0x0000fe7f },
-       { _MMIO(0x2780), 0x00000002 },
-       { _MMIO(0x2784), 0x0000ffbf },
-       { _MMIO(0x2788), 0x00000000 },
-       { _MMIO(0x278c), 0x0000ffcf },
-       { _MMIO(0x2790), 0x00000002 },
-       { _MMIO(0x2794), 0x0000fff7 },
-       { _MMIO(0x2798), 0x00000000 },
-       { _MMIO(0x279c), 0x0000fff9 },
-};
-
-static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_tdl_1[] = {
-       { _MMIO(0x9888), 0x16154d60 },
-       { _MMIO(0x9888), 0x16352e60 },
-       { _MMIO(0x9888), 0x16554d60 },
-       { _MMIO(0x9888), 0x16950000 },
-       { _MMIO(0x9888), 0x16b50000 },
-       { _MMIO(0x9888), 0x16d50000 },
-       { _MMIO(0x9888), 0x005c8000 },
-       { _MMIO(0x9888), 0x045cc000 },
-       { _MMIO(0x9888), 0x065c4000 },
-       { _MMIO(0x9888), 0x083d8000 },
-       { _MMIO(0x9888), 0x0a3d8000 },
-       { _MMIO(0x9888), 0x0458c000 },
-       { _MMIO(0x9888), 0x025b8000 },
-       { _MMIO(0x9888), 0x085b4000 },
-       { _MMIO(0x9888), 0x0a5b4000 },
-       { _MMIO(0x9888), 0x0c5b8000 },
-       { _MMIO(0x9888), 0x0c1fa000 },
-       { _MMIO(0x9888), 0x0e1f00aa },
-       { _MMIO(0x9888), 0x02384000 },
-       { _MMIO(0x9888), 0x04388000 },
-       { _MMIO(0x9888), 0x06388000 },
-       { _MMIO(0x9888), 0x08384000 },
-       { _MMIO(0x9888), 0x0a384000 },
-       { _MMIO(0x9888), 0x0c384000 },
-       { _MMIO(0x9888), 0x00398000 },
-       { _MMIO(0x9888), 0x0239a000 },
-       { _MMIO(0x9888), 0x0439a000 },
-       { _MMIO(0x9888), 0x06392000 },
-       { _MMIO(0x9888), 0x043a8000 },
-       { _MMIO(0x9888), 0x063a8000 },
-       { _MMIO(0x9888), 0x08138000 },
-       { _MMIO(0x9888), 0x0a138000 },
-       { _MMIO(0x9888), 0x06143000 },
-       { _MMIO(0x9888), 0x0415cfc7 },
-       { _MMIO(0x9888), 0x10150000 },
-       { _MMIO(0x9888), 0x02338000 },
-       { _MMIO(0x9888), 0x0c338000 },
-       { _MMIO(0x9888), 0x04342000 },
-       { _MMIO(0x9888), 0x06344000 },
-       { _MMIO(0x9888), 0x0035c700 },
-       { _MMIO(0x9888), 0x063500cf },
-       { _MMIO(0x9888), 0x10350000 },
-       { _MMIO(0x9888), 0x04538000 },
-       { _MMIO(0x9888), 0x06538000 },
-       { _MMIO(0x9888), 0x0454c000 },
-       { _MMIO(0x9888), 0x0255cfc7 },
-       { _MMIO(0x9888), 0x10550000 },
-       { _MMIO(0x9888), 0x06dc8000 },
-       { _MMIO(0x9888), 0x08dc4000 },
-       { _MMIO(0x9888), 0x0cdcc000 },
-       { _MMIO(0x9888), 0x0edcc000 },
-       { _MMIO(0x9888), 0x1abd00a8 },
-       { _MMIO(0x9888), 0x0cd8c000 },
-       { _MMIO(0x9888), 0x0ed84000 },
-       { _MMIO(0x9888), 0x0edb8000 },
-       { _MMIO(0x9888), 0x18db0800 },
-       { _MMIO(0x9888), 0x1adb0254 },
-       { _MMIO(0x9888), 0x0e9faa00 },
-       { _MMIO(0x9888), 0x109f02aa },
-       { _MMIO(0x9888), 0x0eb84000 },
-       { _MMIO(0x9888), 0x16b84000 },
-       { _MMIO(0x9888), 0x18b8156a },
-       { _MMIO(0x9888), 0x06b98000 },
-       { _MMIO(0x9888), 0x08b9a000 },
-       { _MMIO(0x9888), 0x0ab9a000 },
-       { _MMIO(0x9888), 0x0cb9a000 },
-       { _MMIO(0x9888), 0x0eb9a000 },
-       { _MMIO(0x9888), 0x18baa000 },
-       { _MMIO(0x9888), 0x1aba0002 },
-       { _MMIO(0x9888), 0x16934000 },
-       { _MMIO(0x9888), 0x1893000a },
-       { _MMIO(0x9888), 0x0a947000 },
-       { _MMIO(0x9888), 0x0c95c5c1 },
-       { _MMIO(0x9888), 0x0e9500c3 },
-       { _MMIO(0x9888), 0x10950000 },
-       { _MMIO(0x9888), 0x0eb38000 },
-       { _MMIO(0x9888), 0x16b30040 },
-       { _MMIO(0x9888), 0x18b30020 },
-       { _MMIO(0x9888), 0x06b48000 },
-       { _MMIO(0x9888), 0x08b41000 },
-       { _MMIO(0x9888), 0x0ab48000 },
-       { _MMIO(0x9888), 0x06b5c500 },
-       { _MMIO(0x9888), 0x08b500c3 },
-       { _MMIO(0x9888), 0x0eb5c100 },
-       { _MMIO(0x9888), 0x10b50000 },
-       { _MMIO(0x9888), 0x16d31500 },
-       { _MMIO(0x9888), 0x08d4e000 },
-       { _MMIO(0x9888), 0x08d5c100 },
-       { _MMIO(0x9888), 0x0ad5c3c5 },
-       { _MMIO(0x9888), 0x10d50000 },
-       { _MMIO(0x9888), 0x0d88f800 },
-       { _MMIO(0x9888), 0x0f88000f },
-       { _MMIO(0x9888), 0x038a8000 },
-       { _MMIO(0x9888), 0x058a8000 },
-       { _MMIO(0x9888), 0x078a8000 },
-       { _MMIO(0x9888), 0x098a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x0d8a8000 },
-       { _MMIO(0x9888), 0x258baaa5 },
-       { _MMIO(0x9888), 0x278b002a },
-       { _MMIO(0x9888), 0x238b2a80 },
-       { _MMIO(0x9888), 0x0f8c4000 },
-       { _MMIO(0x9888), 0x178c2000 },
-       { _MMIO(0x9888), 0x198c5500 },
-       { _MMIO(0x9888), 0x1b8c0015 },
-       { _MMIO(0x9888), 0x078d8000 },
-       { _MMIO(0x9888), 0x098da000 },
-       { _MMIO(0x9888), 0x0b8da000 },
-       { _MMIO(0x9888), 0x0d8da000 },
-       { _MMIO(0x9888), 0x0f8da000 },
-       { _MMIO(0x9888), 0x2185aaaa },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x1f85aa00 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0784c000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x01848000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1780c000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x11808000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800c42 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800063 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800800 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3f8014a4 },
-       { _MMIO(0x9888), 0x41801042 },
-};
-
-static int
-get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
-                    const struct i915_oa_reg **regs,
-                    int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_tdl_1;
-       lens[n] = ARRAY_SIZE(mux_config_tdl_1);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_tdl_2[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x30800000 },
-       { _MMIO(0x2770), 0x00000002 },
-       { _MMIO(0x2774), 0x0000fdff },
-       { _MMIO(0x2778), 0x00000000 },
-       { _MMIO(0x277c), 0x0000fe7f },
-       { _MMIO(0x2780), 0x00000000 },
-       { _MMIO(0x2784), 0x0000ff9f },
-       { _MMIO(0x2788), 0x00000000 },
-       { _MMIO(0x278c), 0x0000ffe7 },
-       { _MMIO(0x2790), 0x00000002 },
-       { _MMIO(0x2794), 0x0000fffb },
-       { _MMIO(0x2798), 0x00000002 },
-       { _MMIO(0x279c), 0x0000fffd },
-};
-
-static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_tdl_2[] = {
-       { _MMIO(0x9888), 0x16150000 },
-       { _MMIO(0x9888), 0x16350000 },
-       { _MMIO(0x9888), 0x16550000 },
-       { _MMIO(0x9888), 0x16952e60 },
-       { _MMIO(0x9888), 0x16b54d60 },
-       { _MMIO(0x9888), 0x16d52e60 },
-       { _MMIO(0x9888), 0x065c8000 },
-       { _MMIO(0x9888), 0x085cc000 },
-       { _MMIO(0x9888), 0x0a5cc000 },
-       { _MMIO(0x9888), 0x0c5c4000 },
-       { _MMIO(0x9888), 0x0e3d8000 },
-       { _MMIO(0x9888), 0x183da000 },
-       { _MMIO(0x9888), 0x06588000 },
-       { _MMIO(0x9888), 0x08588000 },
-       { _MMIO(0x9888), 0x0a584000 },
-       { _MMIO(0x9888), 0x0e5b4000 },
-       { _MMIO(0x9888), 0x185b5800 },
-       { _MMIO(0x9888), 0x1a5b000a },
-       { _MMIO(0x9888), 0x0e1faa00 },
-       { _MMIO(0x9888), 0x101f02aa },
-       { _MMIO(0x9888), 0x0e384000 },
-       { _MMIO(0x9888), 0x16384000 },
-       { _MMIO(0x9888), 0x18382a55 },
-       { _MMIO(0x9888), 0x06398000 },
-       { _MMIO(0x9888), 0x0839a000 },
-       { _MMIO(0x9888), 0x0a39a000 },
-       { _MMIO(0x9888), 0x0c39a000 },
-       { _MMIO(0x9888), 0x0e39a000 },
-       { _MMIO(0x9888), 0x1a3a02a0 },
-       { _MMIO(0x9888), 0x0e138000 },
-       { _MMIO(0x9888), 0x16130500 },
-       { _MMIO(0x9888), 0x06148000 },
-       { _MMIO(0x9888), 0x08146000 },
-       { _MMIO(0x9888), 0x0615c100 },
-       { _MMIO(0x9888), 0x0815c500 },
-       { _MMIO(0x9888), 0x0a1500c3 },
-       { _MMIO(0x9888), 0x10150000 },
-       { _MMIO(0x9888), 0x16335040 },
-       { _MMIO(0x9888), 0x08349000 },
-       { _MMIO(0x9888), 0x0a341000 },
-       { _MMIO(0x9888), 0x083500c1 },
-       { _MMIO(0x9888), 0x0a35c500 },
-       { _MMIO(0x9888), 0x0c3500c3 },
-       { _MMIO(0x9888), 0x10350000 },
-       { _MMIO(0x9888), 0x1853002a },
-       { _MMIO(0x9888), 0x0a54e000 },
-       { _MMIO(0x9888), 0x0c55c500 },
-       { _MMIO(0x9888), 0x0e55c1c3 },
-       { _MMIO(0x9888), 0x10550000 },
-       { _MMIO(0x9888), 0x00dc8000 },
-       { _MMIO(0x9888), 0x02dcc000 },
-       { _MMIO(0x9888), 0x04dc4000 },
-       { _MMIO(0x9888), 0x04bd8000 },
-       { _MMIO(0x9888), 0x06bd8000 },
-       { _MMIO(0x9888), 0x02d8c000 },
-       { _MMIO(0x9888), 0x02db8000 },
-       { _MMIO(0x9888), 0x04db4000 },
-       { _MMIO(0x9888), 0x06db4000 },
-       { _MMIO(0x9888), 0x08db8000 },
-       { _MMIO(0x9888), 0x0c9fa000 },
-       { _MMIO(0x9888), 0x0e9f00aa },
-       { _MMIO(0x9888), 0x02b84000 },
-       { _MMIO(0x9888), 0x04b84000 },
-       { _MMIO(0x9888), 0x06b84000 },
-       { _MMIO(0x9888), 0x08b84000 },
-       { _MMIO(0x9888), 0x0ab88000 },
-       { _MMIO(0x9888), 0x0cb88000 },
-       { _MMIO(0x9888), 0x00b98000 },
-       { _MMIO(0x9888), 0x02b9a000 },
-       { _MMIO(0x9888), 0x04b9a000 },
-       { _MMIO(0x9888), 0x06b92000 },
-       { _MMIO(0x9888), 0x0aba8000 },
-       { _MMIO(0x9888), 0x0cba8000 },
-       { _MMIO(0x9888), 0x04938000 },
-       { _MMIO(0x9888), 0x06938000 },
-       { _MMIO(0x9888), 0x0494c000 },
-       { _MMIO(0x9888), 0x0295cfc7 },
-       { _MMIO(0x9888), 0x10950000 },
-       { _MMIO(0x9888), 0x02b38000 },
-       { _MMIO(0x9888), 0x08b38000 },
-       { _MMIO(0x9888), 0x04b42000 },
-       { _MMIO(0x9888), 0x06b41000 },
-       { _MMIO(0x9888), 0x00b5c700 },
-       { _MMIO(0x9888), 0x04b500cf },
-       { _MMIO(0x9888), 0x10b50000 },
-       { _MMIO(0x9888), 0x0ad38000 },
-       { _MMIO(0x9888), 0x0cd38000 },
-       { _MMIO(0x9888), 0x06d46000 },
-       { _MMIO(0x9888), 0x04d5c700 },
-       { _MMIO(0x9888), 0x06d500cf },
-       { _MMIO(0x9888), 0x10d50000 },
-       { _MMIO(0x9888), 0x03888000 },
-       { _MMIO(0x9888), 0x05888000 },
-       { _MMIO(0x9888), 0x07888000 },
-       { _MMIO(0x9888), 0x09888000 },
-       { _MMIO(0x9888), 0x0b888000 },
-       { _MMIO(0x9888), 0x0d880400 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x198a8000 },
-       { _MMIO(0x9888), 0x1b8aaaa0 },
-       { _MMIO(0x9888), 0x1d8a0002 },
-       { _MMIO(0x9888), 0x258b555a },
-       { _MMIO(0x9888), 0x278b0015 },
-       { _MMIO(0x9888), 0x238b5500 },
-       { _MMIO(0x9888), 0x038c4000 },
-       { _MMIO(0x9888), 0x058c4000 },
-       { _MMIO(0x9888), 0x078c4000 },
-       { _MMIO(0x9888), 0x098c4000 },
-       { _MMIO(0x9888), 0x0b8c4000 },
-       { _MMIO(0x9888), 0x0d8c4000 },
-       { _MMIO(0x9888), 0x018d8000 },
-       { _MMIO(0x9888), 0x038da000 },
-       { _MMIO(0x9888), 0x058da000 },
-       { _MMIO(0x9888), 0x078d2000 },
-       { _MMIO(0x9888), 0x2185aaaa },
-       { _MMIO(0x9888), 0x2385002a },
-       { _MMIO(0x9888), 0x1f85aa00 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830155 },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x0784c000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x0f84c000 },
-       { _MMIO(0x9888), 0x01848000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x1780c000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x1f80c000 },
-       { _MMIO(0x9888), 0x11808000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800882 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45801082 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x478014a5 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3f800002 },
-       { _MMIO(0x9888), 0x41800c62 },
-};
-
-static int
-get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
-                    const struct i915_oa_reg **regs,
-                    int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_tdl_2;
-       lens[n] = ARRAY_SIZE(mux_config_tdl_2);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_compute_extra[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0x00800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x00800000 },
-};
-
-static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
-       { _MMIO(0xe458), 0x00001000 },
-       { _MMIO(0xe558), 0x00003002 },
-       { _MMIO(0xe658), 0x00005004 },
-       { _MMIO(0xe758), 0x00011010 },
-       { _MMIO(0xe45c), 0x00050012 },
-       { _MMIO(0xe55c), 0x00052051 },
-       { _MMIO(0xe65c), 0x00000008 },
-};
-
-static const struct i915_oa_reg mux_config_compute_extra[] = {
-       { _MMIO(0x9888), 0x161503e0 },
-       { _MMIO(0x9888), 0x163503e0 },
-       { _MMIO(0x9888), 0x165503e0 },
-       { _MMIO(0x9888), 0x169503e0 },
-       { _MMIO(0x9888), 0x16b503e0 },
-       { _MMIO(0x9888), 0x16d503e0 },
-       { _MMIO(0x9888), 0x045cc000 },
-       { _MMIO(0x9888), 0x083d8000 },
-       { _MMIO(0x9888), 0x04584000 },
-       { _MMIO(0x9888), 0x085b4000 },
-       { _MMIO(0x9888), 0x0a5b8000 },
-       { _MMIO(0x9888), 0x0e1f00a8 },
-       { _MMIO(0x9888), 0x08384000 },
-       { _MMIO(0x9888), 0x0a384000 },
-       { _MMIO(0x9888), 0x0c388000 },
-       { _MMIO(0x9888), 0x0439a000 },
-       { _MMIO(0x9888), 0x06392000 },
-       { _MMIO(0x9888), 0x0c3a8000 },
-       { _MMIO(0x9888), 0x08138000 },
-       { _MMIO(0x9888), 0x06141000 },
-       { _MMIO(0x9888), 0x041500c3 },
-       { _MMIO(0x9888), 0x10150000 },
-       { _MMIO(0x9888), 0x0a338000 },
-       { _MMIO(0x9888), 0x06342000 },
-       { _MMIO(0x9888), 0x0435c300 },
-       { _MMIO(0x9888), 0x10350000 },
-       { _MMIO(0x9888), 0x0c538000 },
-       { _MMIO(0x9888), 0x06544000 },
-       { _MMIO(0x9888), 0x065500c3 },
-       { _MMIO(0x9888), 0x10550000 },
-       { _MMIO(0x9888), 0x00dc8000 },
-       { _MMIO(0x9888), 0x02dc4000 },
-       { _MMIO(0x9888), 0x02bd8000 },
-       { _MMIO(0x9888), 0x00d88000 },
-       { _MMIO(0x9888), 0x02db4000 },
-       { _MMIO(0x9888), 0x04db8000 },
-       { _MMIO(0x9888), 0x0c9fa000 },
-       { _MMIO(0x9888), 0x0e9f0002 },
-       { _MMIO(0x9888), 0x02b84000 },
-       { _MMIO(0x9888), 0x04b84000 },
-       { _MMIO(0x9888), 0x06b88000 },
-       { _MMIO(0x9888), 0x00b98000 },
-       { _MMIO(0x9888), 0x02b9a000 },
-       { _MMIO(0x9888), 0x06ba8000 },
-       { _MMIO(0x9888), 0x02938000 },
-       { _MMIO(0x9888), 0x04942000 },
-       { _MMIO(0x9888), 0x0095c300 },
-       { _MMIO(0x9888), 0x10950000 },
-       { _MMIO(0x9888), 0x04b38000 },
-       { _MMIO(0x9888), 0x04b44000 },
-       { _MMIO(0x9888), 0x02b500c3 },
-       { _MMIO(0x9888), 0x10b50000 },
-       { _MMIO(0x9888), 0x06d38000 },
-       { _MMIO(0x9888), 0x04d48000 },
-       { _MMIO(0x9888), 0x02d5c300 },
-       { _MMIO(0x9888), 0x10d50000 },
-       { _MMIO(0x9888), 0x03888000 },
-       { _MMIO(0x9888), 0x05888000 },
-       { _MMIO(0x9888), 0x07888000 },
-       { _MMIO(0x9888), 0x098a8000 },
-       { _MMIO(0x9888), 0x0b8a8000 },
-       { _MMIO(0x9888), 0x0d8a8000 },
-       { _MMIO(0x9888), 0x238b3500 },
-       { _MMIO(0x9888), 0x258b0005 },
-       { _MMIO(0x9888), 0x038c4000 },
-       { _MMIO(0x9888), 0x058c4000 },
-       { _MMIO(0x9888), 0x078c4000 },
-       { _MMIO(0x9888), 0x018d8000 },
-       { _MMIO(0x9888), 0x038da000 },
-       { _MMIO(0x9888), 0x1f85aa00 },
-       { _MMIO(0x9888), 0x2185000a },
-       { _MMIO(0x9888), 0x03834000 },
-       { _MMIO(0x9888), 0x05834000 },
-       { _MMIO(0x9888), 0x07834000 },
-       { _MMIO(0x9888), 0x09834000 },
-       { _MMIO(0x9888), 0x0b834000 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x01848000 },
-       { _MMIO(0x9888), 0x0384c000 },
-       { _MMIO(0x9888), 0x0584c000 },
-       { _MMIO(0x9888), 0x07844000 },
-       { _MMIO(0x9888), 0x11808000 },
-       { _MMIO(0x9888), 0x1380c000 },
-       { _MMIO(0x9888), 0x1580c000 },
-       { _MMIO(0x9888), 0x17804000 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3f800c40 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x41801482 },
-       { _MMIO(0x9888), 0x31800000 },
-};
-
-static int
-get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
-                            const struct i915_oa_reg **regs,
-                            int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_compute_extra;
-       lens[n] = ARRAY_SIZE(mux_config_compute_extra);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x30800000 },
-       { _MMIO(0x2770), 0x00100030 },
-       { _MMIO(0x2774), 0x0000fff9 },
-       { _MMIO(0x2778), 0x00000002 },
-       { _MMIO(0x277c), 0x0000fffc },
-       { _MMIO(0x2780), 0x00000002 },
-       { _MMIO(0x2784), 0x0000fff3 },
-       { _MMIO(0x2788), 0x00100180 },
-       { _MMIO(0x278c), 0x0000ffcf },
-       { _MMIO(0x2790), 0x00000002 },
-       { _MMIO(0x2794), 0x0000ffcf },
-       { _MMIO(0x2798), 0x00000002 },
-       { _MMIO(0x279c), 0x0000ff3f },
-};
-
-static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00008003 },
-};
-
-static const struct i915_oa_reg mux_config_vme_pipe[] = {
-       { _MMIO(0x9888), 0x14100812 },
-       { _MMIO(0x9888), 0x14125800 },
-       { _MMIO(0x9888), 0x161200c0 },
-       { _MMIO(0x9888), 0x14300812 },
-       { _MMIO(0x9888), 0x14325800 },
-       { _MMIO(0x9888), 0x163200c0 },
-       { _MMIO(0x9888), 0x005c4000 },
-       { _MMIO(0x9888), 0x065c8000 },
-       { _MMIO(0x9888), 0x085cc000 },
-       { _MMIO(0x9888), 0x0a5cc000 },
-       { _MMIO(0x9888), 0x0c5cc000 },
-       { _MMIO(0x9888), 0x003d8000 },
-       { _MMIO(0x9888), 0x0e3d8000 },
-       { _MMIO(0x9888), 0x183d2800 },
-       { _MMIO(0x9888), 0x00584000 },
-       { _MMIO(0x9888), 0x06588000 },
-       { _MMIO(0x9888), 0x0858c000 },
-       { _MMIO(0x9888), 0x005b4000 },
-       { _MMIO(0x9888), 0x0e5b4000 },
-       { _MMIO(0x9888), 0x185b9400 },
-       { _MMIO(0x9888), 0x1a5b002a },
-       { _MMIO(0x9888), 0x0c1f0800 },
-       { _MMIO(0x9888), 0x0e1faa00 },
-       { _MMIO(0x9888), 0x101f002a },
-       { _MMIO(0x9888), 0x00384000 },
-       { _MMIO(0x9888), 0x0e384000 },
-       { _MMIO(0x9888), 0x16384000 },
-       { _MMIO(0x9888), 0x18380155 },
-       { _MMIO(0x9888), 0x00392000 },
-       { _MMIO(0x9888), 0x06398000 },
-       { _MMIO(0x9888), 0x0839a000 },
-       { _MMIO(0x9888), 0x0a39a000 },
-       { _MMIO(0x9888), 0x0c39a000 },
-       { _MMIO(0x9888), 0x00100047 },
-       { _MMIO(0x9888), 0x06101a80 },
-       { _MMIO(0x9888), 0x10100000 },
-       { _MMIO(0x9888), 0x0810c000 },
-       { _MMIO(0x9888), 0x0811c000 },
-       { _MMIO(0x9888), 0x08126151 },
-       { _MMIO(0x9888), 0x10120000 },
-       { _MMIO(0x9888), 0x00134000 },
-       { _MMIO(0x9888), 0x0e134000 },
-       { _MMIO(0x9888), 0x161300a0 },
-       { _MMIO(0x9888), 0x0a301ac7 },
-       { _MMIO(0x9888), 0x10300000 },
-       { _MMIO(0x9888), 0x0c30c000 },
-       { _MMIO(0x9888), 0x0c31c000 },
-       { _MMIO(0x9888), 0x0c326151 },
-       { _MMIO(0x9888), 0x10320000 },
-       { _MMIO(0x9888), 0x16332a00 },
-       { _MMIO(0x9888), 0x18330001 },
-       { _MMIO(0x9888), 0x018a8000 },
-       { _MMIO(0x9888), 0x0f8a8000 },
-       { _MMIO(0x9888), 0x198a8000 },
-       { _MMIO(0x9888), 0x1b8a2aa0 },
-       { _MMIO(0x9888), 0x238b0020 },
-       { _MMIO(0x9888), 0x258b5550 },
-       { _MMIO(0x9888), 0x278b0001 },
-       { _MMIO(0x9888), 0x1f850080 },
-       { _MMIO(0x9888), 0x2185aaa0 },
-       { _MMIO(0x9888), 0x23850002 },
-       { _MMIO(0x9888), 0x01834000 },
-       { _MMIO(0x9888), 0x0f834000 },
-       { _MMIO(0x9888), 0x19835400 },
-       { _MMIO(0x9888), 0x1b830015 },
-       { _MMIO(0x9888), 0x01844000 },
-       { _MMIO(0x9888), 0x07848000 },
-       { _MMIO(0x9888), 0x0984c000 },
-       { _MMIO(0x9888), 0x0b84c000 },
-       { _MMIO(0x9888), 0x0d84c000 },
-       { _MMIO(0x9888), 0x11804000 },
-       { _MMIO(0x9888), 0x17808000 },
-       { _MMIO(0x9888), 0x1980c000 },
-       { _MMIO(0x9888), 0x1b80c000 },
-       { _MMIO(0x9888), 0x1d80c000 },
-       { _MMIO(0x9888), 0x4d800000 },
-       { _MMIO(0x9888), 0x3d800800 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x43800002 },
-       { _MMIO(0x9888), 0x51800000 },
-       { _MMIO(0x9888), 0x45800884 },
-       { _MMIO(0x9888), 0x53800000 },
-       { _MMIO(0x9888), 0x47800002 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x31800000 },
-};
-
-static int
-get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
-                       const struct i915_oa_reg **regs,
-                       int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_vme_pipe;
-       lens[n] = ARRAY_SIZE(mux_config_vme_pipe);
-       n++;
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_test_oa[] = {
-       { _MMIO(0x2740), 0x00000000 },
-       { _MMIO(0x2744), 0x00800000 },
-       { _MMIO(0x2714), 0xf0800000 },
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2724), 0xf0800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2770), 0x00000004 },
-       { _MMIO(0x2774), 0x00000000 },
-       { _MMIO(0x2778), 0x00000003 },
-       { _MMIO(0x277c), 0x00000000 },
-       { _MMIO(0x2780), 0x00000007 },
-       { _MMIO(0x2784), 0x00000000 },
-       { _MMIO(0x2788), 0x00100002 },
-       { _MMIO(0x278c), 0x0000fff7 },
-       { _MMIO(0x2790), 0x00100002 },
-       { _MMIO(0x2794), 0x0000ffcf },
-       { _MMIO(0x2798), 0x00100082 },
-       { _MMIO(0x279c), 0x0000ffef },
-       { _MMIO(0x27a0), 0x001000c2 },
-       { _MMIO(0x27a4), 0x0000ffe7 },
-       { _MMIO(0x27a8), 0x00100001 },
-       { _MMIO(0x27ac), 0x0000ffe7 },
-};
-
-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
-};
-
-static const struct i915_oa_reg mux_config_test_oa[] = {
-       { _MMIO(0x9888), 0x198b0000 },
-       { _MMIO(0x9888), 0x078b0066 },
-       { _MMIO(0x9888), 0x118b0000 },
-       { _MMIO(0x9888), 0x258b0000 },
-       { _MMIO(0x9888), 0x21850008 },
-       { _MMIO(0x9888), 0x0d834000 },
-       { _MMIO(0x9888), 0x07844000 },
-       { _MMIO(0x9888), 0x17804000 },
-       { _MMIO(0x9888), 0x21800000 },
-       { _MMIO(0x9888), 0x4f800000 },
-       { _MMIO(0x9888), 0x41800000 },
-       { _MMIO(0x9888), 0x31800000 },
-};
-
-static int
-get_test_oa_mux_config(struct drm_i915_private *dev_priv,
-                      const struct i915_oa_reg **regs,
-                      int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_test_oa;
-       lens[n] = ARRAY_SIZE(mux_config_test_oa);
-       n++;
-
-       return n;
-}
-
-int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv)
-{
-       dev_priv->perf.oa.n_mux_configs = 0;
-       dev_priv->perf.oa.b_counter_regs = NULL;
-       dev_priv->perf.oa.b_counter_regs_len = 0;
-       dev_priv->perf.oa.flex_regs = NULL;
-       dev_priv->perf.oa.flex_regs_len = 0;
-
-       switch (dev_priv->perf.oa.metrics_set) {
-       case METRIC_SET_ID_RENDER_BASIC:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_render_basic_mux_config(dev_priv,
-                                                   dev_priv->perf.oa.mux_regs,
-                                                   dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_render_basic;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_render_basic);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_render_basic;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_render_basic);
-
-               return 0;
-       case METRIC_SET_ID_COMPUTE_BASIC:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_compute_basic_mux_config(dev_priv,
-                                                    dev_priv->perf.oa.mux_regs,
-                                                    dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_compute_basic;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_compute_basic);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_compute_basic;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_compute_basic);
-
-               return 0;
-       case METRIC_SET_ID_RENDER_PIPE_PROFILE:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_render_pipe_profile_mux_config(dev_priv,
-                                                          dev_priv->perf.oa.mux_regs,
-                                                          dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_render_pipe_profile;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_render_pipe_profile);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_render_pipe_profile;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_render_pipe_profile);
-
-               return 0;
-       case METRIC_SET_ID_MEMORY_READS:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_memory_reads_mux_config(dev_priv,
-                                                   dev_priv->perf.oa.mux_regs,
-                                                   dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_memory_reads;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_memory_reads);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_memory_reads;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_memory_reads);
-
-               return 0;
-       case METRIC_SET_ID_MEMORY_WRITES:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_memory_writes_mux_config(dev_priv,
-                                                    dev_priv->perf.oa.mux_regs,
-                                                    dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_memory_writes;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_memory_writes);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_memory_writes;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_memory_writes);
-
-               return 0;
-       case METRIC_SET_ID_COMPUTE_EXTENDED:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_compute_extended_mux_config(dev_priv,
-                                                       dev_priv->perf.oa.mux_regs,
-                                                       dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_compute_extended;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_compute_extended);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_compute_extended;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_compute_extended);
-
-               return 0;
-       case METRIC_SET_ID_COMPUTE_L3_CACHE:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_compute_l3_cache_mux_config(dev_priv,
-                                                       dev_priv->perf.oa.mux_regs,
-                                                       dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_compute_l3_cache;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_compute_l3_cache);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_compute_l3_cache;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_compute_l3_cache);
-
-               return 0;
-       case METRIC_SET_ID_DATA_PORT_READS_COALESCING:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_data_port_reads_coalescing_mux_config(dev_priv,
-                                                                 dev_priv->perf.oa.mux_regs,
-                                                                 dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_READS_COALESCING\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_data_port_reads_coalescing;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_data_port_reads_coalescing);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_data_port_reads_coalescing;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_data_port_reads_coalescing);
-
-               return 0;
-       case METRIC_SET_ID_DATA_PORT_WRITES_COALESCING:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_data_port_writes_coalescing_mux_config(dev_priv,
-                                                                  dev_priv->perf.oa.mux_regs,
-                                                                  dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_WRITES_COALESCING\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_data_port_writes_coalescing;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_data_port_writes_coalescing);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_data_port_writes_coalescing;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_data_port_writes_coalescing);
-
-               return 0;
-       case METRIC_SET_ID_HDC_AND_SF:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_hdc_and_sf_mux_config(dev_priv,
-                                                 dev_priv->perf.oa.mux_regs,
-                                                 dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_hdc_and_sf;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_hdc_and_sf);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_hdc_and_sf;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_hdc_and_sf);
-
-               return 0;
-       case METRIC_SET_ID_L3_1:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_l3_1_mux_config(dev_priv,
-                                           dev_priv->perf.oa.mux_regs,
-                                           dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_l3_1;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_l3_1);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_l3_1;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_l3_1);
-
-               return 0;
-       case METRIC_SET_ID_L3_2:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_l3_2_mux_config(dev_priv,
-                                           dev_priv->perf.oa.mux_regs,
-                                           dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_l3_2;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_l3_2);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_l3_2;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_l3_2);
-
-               return 0;
-       case METRIC_SET_ID_L3_3:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_l3_3_mux_config(dev_priv,
-                                           dev_priv->perf.oa.mux_regs,
-                                           dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_l3_3;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_l3_3);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_l3_3;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_l3_3);
-
-               return 0;
-       case METRIC_SET_ID_L3_4:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_l3_4_mux_config(dev_priv,
-                                           dev_priv->perf.oa.mux_regs,
-                                           dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_l3_4;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_l3_4);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_l3_4;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_l3_4);
-
-               return 0;
-       case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_rasterizer_and_pixel_backend_mux_config(dev_priv,
-                                                                   dev_priv->perf.oa.mux_regs,
-                                                                   dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_rasterizer_and_pixel_backend;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_rasterizer_and_pixel_backend;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
-
-               return 0;
-       case METRIC_SET_ID_SAMPLER_1:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_sampler_1_mux_config(dev_priv,
-                                                dev_priv->perf.oa.mux_regs,
-                                                dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_sampler_1;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_sampler_1);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_sampler_1;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_sampler_1);
-
-               return 0;
-       case METRIC_SET_ID_SAMPLER_2:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_sampler_2_mux_config(dev_priv,
-                                                dev_priv->perf.oa.mux_regs,
-                                                dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_sampler_2;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_sampler_2);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_sampler_2;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_sampler_2);
-
-               return 0;
-       case METRIC_SET_ID_TDL_1:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_tdl_1_mux_config(dev_priv,
-                                            dev_priv->perf.oa.mux_regs,
-                                            dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_tdl_1;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_tdl_1);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_tdl_1;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_tdl_1);
-
-               return 0;
-       case METRIC_SET_ID_TDL_2:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_tdl_2_mux_config(dev_priv,
-                                            dev_priv->perf.oa.mux_regs,
-                                            dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_tdl_2;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_tdl_2);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_tdl_2;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_tdl_2);
-
-               return 0;
-       case METRIC_SET_ID_COMPUTE_EXTRA:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_compute_extra_mux_config(dev_priv,
-                                                    dev_priv->perf.oa.mux_regs,
-                                                    dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_compute_extra;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_compute_extra);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_compute_extra;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_compute_extra);
-
-               return 0;
-       case METRIC_SET_ID_VME_PIPE:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_vme_pipe_mux_config(dev_priv,
-                                               dev_priv->perf.oa.mux_regs,
-                                               dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_vme_pipe;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_vme_pipe);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_vme_pipe;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_vme_pipe);
-
-               return 0;
-       case METRIC_SET_ID_TEST_OA:
-               dev_priv->perf.oa.n_mux_configs =
-                       get_test_oa_mux_config(dev_priv,
-                                              dev_priv->perf.oa.mux_regs,
-                                              dev_priv->perf.oa.mux_regs_lens);
-               if (dev_priv->perf.oa.n_mux_configs == 0) {
-                       DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
-
-                       /* EINVAL because *_register_sysfs already checked this
-                        * and so it wouldn't have been advertised to userspace and
-                        * so shouldn't have been requested
-                        */
-                       return -EINVAL;
-               }
-
-               dev_priv->perf.oa.b_counter_regs =
-                       b_counter_config_test_oa;
-               dev_priv->perf.oa.b_counter_regs_len =
-                       ARRAY_SIZE(b_counter_config_test_oa);
-
-               dev_priv->perf.oa.flex_regs =
-                       flex_eu_config_test_oa;
-               dev_priv->perf.oa.flex_regs_len =
-                       ARRAY_SIZE(flex_eu_config_test_oa);
-
-               return 0;
-       default:
-               return -ENODEV;
-       }
-}
-
-static ssize_t
-show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
-}
-
-static struct device_attribute dev_attr_render_basic_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_render_basic_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_render_basic[] = {
-       &dev_attr_render_basic_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_render_basic = {
-       .name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7",
-       .attrs =  attrs_render_basic,
-};
-
-static ssize_t
-show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
-}
-
-static struct device_attribute dev_attr_compute_basic_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_compute_basic_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_compute_basic[] = {
-       &dev_attr_compute_basic_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_compute_basic = {
-       .name = "35fbc9b2-a891-40a6-a38d-022bb7057552",
-       .attrs =  attrs_compute_basic,
-};
-
-static ssize_t
-show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
-}
-
-static struct device_attribute dev_attr_render_pipe_profile_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_render_pipe_profile_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_render_pipe_profile[] = {
-       &dev_attr_render_pipe_profile_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_render_pipe_profile = {
-       .name = "233d0544-fff7-4281-8291-e02f222aff72",
-       .attrs =  attrs_render_pipe_profile,
-};
-
-static ssize_t
-show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
-}
-
-static struct device_attribute dev_attr_memory_reads_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_memory_reads_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_memory_reads[] = {
-       &dev_attr_memory_reads_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_memory_reads = {
-       .name = "2b255d48-2117-4fef-a8f7-f151e1d25a2c",
-       .attrs =  attrs_memory_reads,
-};
-
-static ssize_t
-show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
-}
-
-static struct device_attribute dev_attr_memory_writes_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_memory_writes_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_memory_writes[] = {
-       &dev_attr_memory_writes_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_memory_writes = {
-       .name = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c",
-       .attrs =  attrs_memory_writes,
-};
-
-static ssize_t
-show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
-}
-
-static struct device_attribute dev_attr_compute_extended_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_compute_extended_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_compute_extended[] = {
-       &dev_attr_compute_extended_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_compute_extended = {
-       .name = "e99ccaca-821c-4df9-97a7-96bdb7204e43",
-       .attrs =  attrs_compute_extended,
-};
-
-static ssize_t
-show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
-}
-
-static struct device_attribute dev_attr_compute_l3_cache_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_compute_l3_cache_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_compute_l3_cache[] = {
-       &dev_attr_compute_l3_cache_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_compute_l3_cache = {
-       .name = "27a364dc-8225-4ecb-b607-d6f1925598d9",
-       .attrs =  attrs_compute_l3_cache,
-};
-
-static ssize_t
-show_data_port_reads_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_READS_COALESCING);
-}
-
-static struct device_attribute dev_attr_data_port_reads_coalescing_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_data_port_reads_coalescing_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_data_port_reads_coalescing[] = {
-       &dev_attr_data_port_reads_coalescing_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_data_port_reads_coalescing = {
-       .name = "857fc630-2f09-4804-85f1-084adfadd5ab",
-       .attrs =  attrs_data_port_reads_coalescing,
-};
-
-static ssize_t
-show_data_port_writes_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_WRITES_COALESCING);
-}
-
-static struct device_attribute dev_attr_data_port_writes_coalescing_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_data_port_writes_coalescing_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_data_port_writes_coalescing[] = {
-       &dev_attr_data_port_writes_coalescing_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_data_port_writes_coalescing = {
-       .name = "343ebc99-4a55-414c-8c17-d8e259cf5e20",
-       .attrs =  attrs_data_port_writes_coalescing,
-};
-
-static ssize_t
-show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
-}
-
-static struct device_attribute dev_attr_hdc_and_sf_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_hdc_and_sf_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_hdc_and_sf[] = {
-       &dev_attr_hdc_and_sf_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_hdc_and_sf = {
-       .name = "7bdafd88-a4fa-4ed5-bc09-1a977aa5be3e",
-       .attrs =  attrs_hdc_and_sf,
-};
-
-static ssize_t
-show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
-}
-
-static struct device_attribute dev_attr_l3_1_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_l3_1_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_l3_1[] = {
-       &dev_attr_l3_1_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_l3_1 = {
-       .name = "9385ebb2-f34f-4aa5-aec5-7e9cbbea0f0b",
-       .attrs =  attrs_l3_1,
-};
-
-static ssize_t
-show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
-}
-
-static struct device_attribute dev_attr_l3_2_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_l3_2_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_l3_2[] = {
-       &dev_attr_l3_2_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_l3_2 = {
-       .name = "446ae59b-ff2e-41c9-b49e-0184a54bf00a",
-       .attrs =  attrs_l3_2,
-};
-
-static ssize_t
-show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
-}
-
-static struct device_attribute dev_attr_l3_3_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_l3_3_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_l3_3[] = {
-       &dev_attr_l3_3_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_l3_3 = {
-       .name = "84a7956f-1ea4-4d0d-837f-e39a0376e38c",
-       .attrs =  attrs_l3_3,
-};
-
-static ssize_t
-show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4);
-}
-
-static struct device_attribute dev_attr_l3_4_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_l3_4_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_l3_4[] = {
-       &dev_attr_l3_4_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_l3_4 = {
-       .name = "92b493d9-df18-4bed-be06-5cac6f2a6f5f",
-       .attrs =  attrs_l3_4,
-};
-
-static ssize_t
-show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
-}
-
-static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_rasterizer_and_pixel_backend_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
-       &dev_attr_rasterizer_and_pixel_backend_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_rasterizer_and_pixel_backend = {
-       .name = "14345c35-cc46-40d0-bb04-6ed1fbb43679",
-       .attrs =  attrs_rasterizer_and_pixel_backend,
-};
-
-static ssize_t
-show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1);
-}
-
-static struct device_attribute dev_attr_sampler_1_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_sampler_1_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_sampler_1[] = {
-       &dev_attr_sampler_1_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_sampler_1 = {
-       .name = "f0c6ba37-d3d3-4211-91b5-226730312a54",
-       .attrs =  attrs_sampler_1,
-};
-
-static ssize_t
-show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2);
-}
-
-static struct device_attribute dev_attr_sampler_2_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_sampler_2_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_sampler_2[] = {
-       &dev_attr_sampler_2_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_sampler_2 = {
-       .name = "30bf3702-48cf-4bca-b412-7cf50bb2f564",
-       .attrs =  attrs_sampler_2,
-};
-
-static ssize_t
-show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
-}
-
-static struct device_attribute dev_attr_tdl_1_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_tdl_1_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_tdl_1[] = {
-       &dev_attr_tdl_1_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_tdl_1 = {
-       .name = "238bec85-df05-44f3-b905-d166712f2451",
-       .attrs =  attrs_tdl_1,
-};
-
-static ssize_t
-show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
-}
-
-static struct device_attribute dev_attr_tdl_2_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_tdl_2_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_tdl_2[] = {
-       &dev_attr_tdl_2_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_tdl_2 = {
-       .name = "24bf02cd-8693-4583-981c-c4165b33da01",
-       .attrs =  attrs_tdl_2,
-};
-
-static ssize_t
-show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
-}
-
-static struct device_attribute dev_attr_compute_extra_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_compute_extra_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_compute_extra[] = {
-       &dev_attr_compute_extra_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_compute_extra = {
-       .name = "8fb61ba2-2fbb-454c-a136-2dec5a8a595e",
-       .attrs =  attrs_compute_extra,
-};
-
-static ssize_t
-show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
-}
-
-static struct device_attribute dev_attr_vme_pipe_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_vme_pipe_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_vme_pipe[] = {
-       &dev_attr_vme_pipe_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_vme_pipe = {
-       .name = "e1743ca0-7fc8-410b-a066-de7bbb9280b7",
-       .attrs =  attrs_vme_pipe,
-};
-
-static ssize_t
-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
-{
-       return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
-}
-
-static struct device_attribute dev_attr_test_oa_id = {
-       .attr = { .name = "id", .mode = 0444 },
-       .show = show_test_oa_id,
-       .store = NULL,
-};
-
-static struct attribute *attrs_test_oa[] = {
-       &dev_attr_test_oa_id.attr,
-       NULL,
-};
-
-static struct attribute_group group_test_oa = {
-       .name = "d6de6f55-e526-4f79-a6a6-d7315c09044e",
-       .attrs =  attrs_test_oa,
-};
-
-int
-i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv)
-{
-       const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
-       int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
-       int ret = 0;
-
-       if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
-               if (ret)
-                       goto error_render_basic;
-       }
-       if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
-               if (ret)
-                       goto error_compute_basic;
-       }
-       if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
-               if (ret)
-                       goto error_render_pipe_profile;
-       }
-       if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
-               if (ret)
-                       goto error_memory_reads;
-       }
-       if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
-               if (ret)
-                       goto error_memory_writes;
-       }
-       if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
-               if (ret)
-                       goto error_compute_extended;
-       }
-       if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
-               if (ret)
-                       goto error_compute_l3_cache;
-       }
-       if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing);
-               if (ret)
-                       goto error_data_port_reads_coalescing;
-       }
-       if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing);
-               if (ret)
-                       goto error_data_port_writes_coalescing;
-       }
-       if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
-               if (ret)
-                       goto error_hdc_and_sf;
-       }
-       if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
-               if (ret)
-                       goto error_l3_1;
-       }
-       if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
-               if (ret)
-                       goto error_l3_2;
-       }
-       if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
-               if (ret)
-                       goto error_l3_3;
-       }
-       if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4);
-               if (ret)
-                       goto error_l3_4;
-       }
-       if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
-               if (ret)
-                       goto error_rasterizer_and_pixel_backend;
-       }
-       if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
-               if (ret)
-                       goto error_sampler_1;
-       }
-       if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
-               if (ret)
-                       goto error_sampler_2;
-       }
-       if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
-               if (ret)
-                       goto error_tdl_1;
-       }
-       if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
-               if (ret)
-                       goto error_tdl_2;
-       }
-       if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
-               if (ret)
-                       goto error_compute_extra;
-       }
-       if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
-               if (ret)
-                       goto error_vme_pipe;
-       }
-       if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
-               ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
-               if (ret)
-                       goto error_test_oa;
-       }
-
-       return 0;
-
-error_test_oa:
-       if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
-error_vme_pipe:
-       if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
-error_compute_extra:
-       if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
-error_tdl_2:
-       if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
-error_tdl_1:
-       if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
-error_sampler_2:
-       if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
-error_sampler_1:
-       if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
-error_rasterizer_and_pixel_backend:
-       if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
-error_l3_4:
-       if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
-error_l3_3:
-       if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
-error_l3_2:
-       if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
-error_l3_1:
-       if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
-error_hdc_and_sf:
-       if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing);
-error_data_port_writes_coalescing:
-       if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing);
-error_data_port_reads_coalescing:
-       if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
-error_compute_l3_cache:
-       if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
-error_compute_extended:
-       if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
-error_memory_writes:
-       if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
-error_memory_reads:
-       if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
-error_render_pipe_profile:
-       if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
-error_compute_basic:
-       if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
-error_render_basic:
-       return ret;
-}
-
-void
-i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv)
-{
-       const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
-       int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
+       dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
 
-       if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
-       if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
-       if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
-       if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
-       if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
-       if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
-       if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
-       if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing);
-       if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing);
-       if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
-       if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
-       if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
-       if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
-       if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
-       if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
-       if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
-       if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
-       if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
-       if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
-       if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
-       if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
-       if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
-               sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+       dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
+       dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
+       dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
 }
index 6363ff9..b812d16 100644 (file)
 #ifndef __I915_OA_BDW_H__
 #define __I915_OA_BDW_H__
 
-extern int i915_oa_n_builtin_metric_sets_bdw;
-
-extern int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv);
-
-extern int i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv);
-
-extern void i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv);
+extern void i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv);
 
 #endif
index 93864d8..b69b900 100644 (file)
 #include "i915_drv.h"
 #include "i915_oa_bxt.h"
 
-enum metric_set_id {
-       METRIC_SET_ID_RENDER_BASIC = 1,
-       METRIC_SET_ID_COMPUTE_BASIC,
-       METRIC_SET_ID_RENDER_PIPE_PROFILE,
-       METRIC_SET_ID_MEMORY_READS,
-       METRIC_SET_ID_MEMORY_WRITES,
-       METRIC_SET_ID_COMPUTE_EXTENDED,
-       METRIC_SET_ID_COMPUTE_L3_CACHE,
-       METRIC_SET_ID_HDC_AND_SF,
-       METRIC_SET_ID_L3_1,
-       METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
-       METRIC_SET_ID_SAMPLER,
-       METRIC_SET_ID_TDL_1,
-       METRIC_SET_ID_TDL_2,
-       METRIC_SET_ID_COMPUTE_EXTRA,
-       METRIC_SET_ID_TEST_OA,
-};
-
-int i915_oa_n_builtin_metric_sets_bxt = 15;
-
-static const struct i915_oa_reg b_counter_config_render_basic[] = {
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0x00800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x00800000 },
-       { _MMIO(0x2740), 0x00000000 },
-};
-
-static const struct i915_oa_reg flex_eu_config_render_basic[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00010003 },
-       { _MMIO(0xe658), 0x00012011 },
-       { _MMIO(0xe758), 0x00015014 },
-       { _MMIO(0xe45c), 0x00051050 },
-       { _MMIO(0xe55c), 0x00053052 },
-       { _MMIO(0xe65c), 0x00055054 },
-};
-
-static const struct i915_oa_reg mux_config_render_basic_0_sku_gte_0x03[] = {
-       { _MMIO(0x9888), 0x166c00f0 },
-       { _MMIO(0x9888), 0x12120280 },
-       { _MMIO(0x9888), 0x12320280 },
-       { _MMIO(0x9888), 0x11930317 },
-       { _MMIO(0x9888), 0x159303df },
-       { _MMIO(0x9888), 0x3f900c00 },
-       { _MMIO(0x9888), 0x419000a0 },
-       { _MMIO(0x9888), 0x002d1000 },
-       { _MMIO(0x9888), 0x062d4000 },
-       { _MMIO(0x9888), 0x082d5000 },
-       { _MMIO(0x9888), 0x0a2d1000 },
-       { _MMIO(0x9888), 0x0c2e0800 },
-       { _MMIO(0x9888), 0x0e2e5900 },
-       { _MMIO(0x9888), 0x0a4c8000 },
-       { _MMIO(0x9888), 0x0c4c8000 },
-       { _MMIO(0x9888), 0x0e4c4000 },
-       { _MMIO(0x9888), 0x064e8000 },
-       { _MMIO(0x9888), 0x084e8000 },
-       { _MMIO(0x9888), 0x0a4e2000 },
-       { _MMIO(0x9888), 0x1c4f0010 },
-       { _MMIO(0x9888), 0x0a6c0053 },
-       { _MMIO(0x9888), 0x106c0000 },
-       { _MMIO(0x9888), 0x1c6c0000 },
-       { _MMIO(0x9888), 0x1a0fcc00 },
-       { _MMIO(0x9888), 0x1c0f0002 },
-       { _MMIO(0x9888), 0x1c2c0040 },
-       { _MMIO(0x9888), 0x00101000 },
-       { _MMIO(0x9888), 0x04101000 },
-       { _MMIO(0x9888), 0x00114000 },
-       { _MMIO(0x9888), 0x08114000 },
-       { _MMIO(0x9888), 0x00120020 },
-       { _MMIO(0x9888), 0x08120021 },
-       { _MMIO(0x9888), 0x00141000 },
-       { _MMIO(0x9888), 0x08141000 },
-       { _MMIO(0x9888), 0x02308000 },
-       { _MMIO(0x9888), 0x04302000 },
-       { _MMIO(0x9888), 0x06318000 },
-       { _MMIO(0x9888), 0x08318000 },
-       { _MMIO(0x9888), 0x06320800 },
-       { _MMIO(0x9888), 0x08320840 },
-       { _MMIO(0x9888), 0x00320000 },
-       { _MMIO(0x9888), 0x06344000 },
-       { _MMIO(0x9888), 0x08344000 },
-       { _MMIO(0x9888), 0x0d931831 },
-       { _MMIO(0x9888), 0x0f939f3f },
-       { _MMIO(0x9888), 0x01939e80 },
-       { _MMIO(0x9888), 0x039303bc },
-       { _MMIO(0x9888), 0x0593000e },
-       { _MMIO(0x9888), 0x1993002a },
-       { _MMIO(0x9888), 0x07930000 },
-       { _MMIO(0x9888), 0x09930000 },
-       { _MMIO(0x9888), 0x1d900177 },
-       { _MMIO(0x9888), 0x1f900187 },
-       { _MMIO(0x9888), 0x35900000 },
-       { _MMIO(0x9888), 0x13904000 },
-       { _MMIO(0x9888), 0x21904000 },
-       { _MMIO(0x9888), 0x23904000 },
-       { _MMIO(0x9888), 0x25904000 },
-       { _MMIO(0x9888), 0x27904000 },
-       { _MMIO(0x9888), 0x2b904000 },
-       { _MMIO(0x9888), 0x2d904000 },
-       { _MMIO(0x9888), 0x2f904000 },
-       { _MMIO(0x9888), 0x31904000 },
-       { _MMIO(0x9888), 0x15904000 },
-       { _MMIO(0x9888), 0x17904000 },
-       { _MMIO(0x9888), 0x19904000 },
-       { _MMIO(0x9888), 0x1b904000 },
-       { _MMIO(0x9888), 0x53901110 },
-       { _MMIO(0x9888), 0x43900423 },
-       { _MMIO(0x9888), 0x55900111 },
-       { _MMIO(0x9888), 0x47900c02 },
-       { _MMIO(0x9888), 0x57900000 },
-       { _MMIO(0x9888), 0x49900020 },
-       { _MMIO(0x9888), 0x59901111 },
-       { _MMIO(0x9888), 0x4b900421 },
-       { _MMIO(0x9888), 0x37900000 },
-       { _MMIO(0x9888), 0x33900000 },
-       { _MMIO(0x9888), 0x4d900001 },
-       { _MMIO(0x9888), 0x45900821 },
-};
-
-static int
-get_render_basic_mux_config(struct drm_i915_private *dev_priv,
-                           const struct i915_oa_reg **regs,
-                           int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       if (dev_priv->drm.pdev->revision >= 0x03) {
-               regs[n] = mux_config_render_basic_0_sku_gte_0x03;
-               lens[n] = ARRAY_SIZE(mux_config_render_basic_0_sku_gte_0x03);
-               n++;
-       }
-
-       return n;
-}
-
-static const struct i915_oa_reg b_counter_config_compute_basic[] = {
-       { _MMIO(0x2710), 0x00000000 },
-       { _MMIO(0x2714), 0x00800000 },
-       { _MMIO(0x2720), 0x00000000 },
-       { _MMIO(0x2724), 0x00800000 },
-       { _MMIO(0x2740), 0x00000000 },
-};
-
-static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
-       { _MMIO(0xe458), 0x00005004 },
-       { _MMIO(0xe558), 0x00000003 },
-       { _MMIO(0xe658), 0x00002001 },
-       { _MMIO(0xe758), 0x00778008 },
-       { _MMIO(0xe45c), 0x00088078 },
-       { _MMIO(0xe55c), 0x00808708 },
-       { _MMIO(0xe65c), 0x00a08908 },
-};
-
-static const struct i915_oa_reg mux_config_compute_basic[] = {
-       { _MMIO(0x9888), 0x104f00e0 },
-       { _MMIO(0x9888), 0x124f1c00 },
-       { _MMIO(0x9888), 0x39900340 },
-       { _MMIO(0x9888), 0x3f900c00 },
-       { _MMIO(0x9888), 0x41900000 },
-       { _MMIO(0x9888), 0x002d5000 },
-       { _MMIO(0x9888), 0x062d4000 },
-       { _MMIO(0x9888), 0x082d4000 },
-       { _MMIO(0x9888), 0x0a2d1000 },
-       { _MMIO(0x9888), 0x0c2d5000 },
-       { _MMIO(0x9888), 0x0e2d4000 },
-       { _MMIO(0x9888), 0x0c2e1400 },
-       { _MMIO(0x9888), 0x0e2e5100 },
-       { _MMIO(0x9888), 0x102e0114 },
-       { _MMIO(0x9888), 0x044cc000 },
-       { _MMIO(0x9888), 0x0a4c8000 },
-       { _MMIO(0x9888), 0x0c4c8000 },
-       { _MMIO(0x9888), 0x0e4c4000 },
-       { _MMIO(0x9888), 0x104c8000 },
-       { _MMIO(0x9888), 0x124c8000 },
-       { _MMIO(0x9888), 0x164c2000 },
-       { _MMIO(0x9888), 0x004ea000 },
-       { _MMIO(0x9888), 0x064e8000 },
-       { _MMIO(0x9888), 0x084e8000 },
-       { _MMIO(0x9888), 0x0a4e2000 },
-       { _MMIO(0x9888), 0x0c4ea000 },
-       { _MMIO(0x9888), 0x0e4e8000 },
-       { _MMIO(0x9888), 0x004f6b42 },
-       { _MMIO(0x9888), 0x064f6200 },
-       { _MMIO(0x9888), 0x084f4100 },
-       { _MMIO(0x9888), 0x0a4f0061 },
-       { _MMIO(0x9888), 0x0c4f6c4c },
-       { _MMIO(0x9888), 0x0e4f4b00 },
-       { _MMIO(0x9888), 0x1a4f0000 },
-       { _MMIO(0x9888), 0x1c4f0000 },
-       { _MMIO(0x9888), 0x180f5000 },
-       { _MMIO(0x9888), 0x1a0f8800 },
-       { _MMIO(0x9888), 0x1c0f08a2 },
-       { _MMIO(0x9888), 0x182c4000 },
-       { _MMIO(0x9888), 0x1c2c1451 },
-       { _MMIO(0x9888), 0x1e2c0001 },
-       { _MMIO(0x9888), 0x1a2c0010 },
-       { _MMIO(0x9888), 0x01938000 },
-       { _MMIO(0x9888), 0x0f938000 },
-       { _MMIO(0x9888), 0x19938a28 },
-       { _MMIO(0x9888), 0x03938000 },
-       { _MMIO(0x9888), 0x19900177 },
-       { _MMIO(0x9888), 0x1b900178 },
-       { _MMIO(0x9888), 0x1d900125 },
-       { _MMIO(0x9888), 0x1f900123 },
-       { _MMIO(0x9888), 0x35900000 },
-       { _MMIO(0x9888), 0x13904000 },
-       { _MMIO(0x9888), 0x21904000 },
-       { _MMIO(0x9888), 0x25904000 },
-       { _MMIO(0x9888), 0x27904000 },
-       { _MMIO(0x9888), 0x2b904000 },
-       { _MMIO(0x9888), 0x2d904000 },
-       { _MMIO(0x9888), 0x31904000 },
-       { _MMIO(0x9888), 0x15904000 },
-       { _MMIO(0x9888), 0x53901000 },
-       { _MMIO(0x9888), 0x43900000 },
-       { _MMIO(0x9888), 0x55900111 },
-       { _MMIO(0x9888), 0x47900000 },
-       { _MMIO(0x9888), 0x57900000 },
-       { _MMIO(0x9888), 0x49900000 },
-       { _MMIO(0x9888), 0x59900000 },
-       { _MMIO(0x9888), 0x4b900000 },
-       { _MMIO(0x9888), 0x37900000 },
-       { _MMIO(0x9888), 0x33900000 },
-       { _MMIO(0x9888), 0x4d900000 },
-       { _MMIO(0x9888), 0x45900000 },
-};
-
-static int
-get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
-                            const struct i915_oa_reg **regs,
-                            int *lens)
-{
-       int n = 0;
-
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
-       BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
-
-       regs[n] = mux_config_compute_basic;
-       lens[n] = ARRAY_SIZE(mux_config_compute_basic);
-       n++;
-
-       return n;
-}
-