arm64/cpufeature: Introduce ID_PFR2 CPU register
authorAnshuman Khandual <anshuman.khandual@arm.com>
Tue, 19 May 2020 09:40:41 +0000 (15:10 +0530)
committerWill Deacon <will@kernel.org>
Thu, 21 May 2020 14:47:11 +0000 (15:47 +0100)
This adds basic building blocks required for ID_PFR2 CPU register which
provides information about the AArch32 programmers model which must be
interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added
per ARM DDI 0487F.a specification.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1589881254-10082-5-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
arch/arm64/include/asm/cpu.h
arch/arm64/include/asm/sysreg.h
arch/arm64/kernel/cpufeature.c
arch/arm64/kernel/cpuinfo.c
arch/arm64/kvm/sys_regs.c

index b4a4053..464e828 100644 (file)
@@ -46,6 +46,7 @@ struct cpuinfo_arm64 {
        u32             reg_id_mmfr3;
        u32             reg_id_pfr0;
        u32             reg_id_pfr1;
+       u32             reg_id_pfr2;
 
        u32             reg_mvfr0;
        u32             reg_mvfr1;
index ea55fe5..d0ea916 100644 (file)
 
 #define SYS_ID_PFR0_EL1                        sys_reg(3, 0, 0, 1, 0)
 #define SYS_ID_PFR1_EL1                        sys_reg(3, 0, 0, 1, 1)
+#define SYS_ID_PFR2_EL1                        sys_reg(3, 0, 0, 3, 4)
 #define SYS_ID_DFR0_EL1                        sys_reg(3, 0, 0, 1, 2)
 #define SYS_ID_AFR0_EL1                        sys_reg(3, 0, 0, 1, 3)
 #define SYS_ID_MMFR0_EL1               sys_reg(3, 0, 0, 1, 4)
 #define ID_ISAR6_DP_SHIFT              4
 #define ID_ISAR6_JSCVT_SHIFT           0
 
+#define ID_PFR2_SSBS_SHIFT             4
+#define ID_PFR2_CSV3_SHIFT             0
+
 #define MVFR0_FPROUND_SHIFT            28
 #define MVFR0_FPSHVEC_SHIFT            24
 #define MVFR0_FPSQRT_SHIFT             20
index ae88d2c..b81b74d 100644 (file)
@@ -439,6 +439,12 @@ static const struct arm64_ftr_bits ftr_id_pfr1[] = {
        ARM64_FTR_END,
 };
 
+static const struct arm64_ftr_bits ftr_id_pfr2[] = {
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
+       ARM64_FTR_END,
+};
+
 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
        /* [31:28] TraceFilt */
        S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
@@ -520,6 +526,7 @@ static const struct __ftr_reg_entry {
        ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
        ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
        ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
+       ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
 
        /* Op1 = 0, CRn = 0, CRm = 4 */
        ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
@@ -726,6 +733,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
                init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
                init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
                init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
+               init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
                init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
                init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
                init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
@@ -859,6 +867,8 @@ static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
                                      info->reg_id_pfr0, boot->reg_id_pfr0);
        taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
                                      info->reg_id_pfr1, boot->reg_id_pfr1);
+       taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
+                                     info->reg_id_pfr2, boot->reg_id_pfr2);
        taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
                                      info->reg_mvfr0, boot->reg_mvfr0);
        taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
@@ -986,6 +996,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id)
        switch (sys_id) {
        read_sysreg_case(SYS_ID_PFR0_EL1);
        read_sysreg_case(SYS_ID_PFR1_EL1);
+       read_sysreg_case(SYS_ID_PFR2_EL1);
        read_sysreg_case(SYS_ID_DFR0_EL1);
        read_sysreg_case(SYS_ID_MMFR0_EL1);
        read_sysreg_case(SYS_ID_MMFR1_EL1);
index 8613607..cb79b08 100644 (file)
@@ -375,6 +375,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
                info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
                info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
                info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
+               info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
 
                info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
                info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
index 51db934..b784b15 100644 (file)
@@ -1456,7 +1456,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
        ID_SANITISED(MVFR1_EL1),
        ID_SANITISED(MVFR2_EL1),
        ID_UNALLOCATED(3,3),
-       ID_UNALLOCATED(3,4),
+       ID_SANITISED(ID_PFR2_EL1),
        ID_UNALLOCATED(3,5),
        ID_UNALLOCATED(3,6),
        ID_UNALLOCATED(3,7),