Merge tag 'imx-dt-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo...
authorOlof Johansson <olof@lixom.net>
Sat, 21 Jul 2018 21:55:45 +0000 (14:55 -0700)
committerOlof Johansson <olof@lixom.net>
Sat, 21 Jul 2018 21:55:45 +0000 (14:55 -0700)
i.MX device tree update for 4.19:
 - Add device tree support for i.MX6SLL SoC.
 - New board support: ConnectCore 6UL System-On-Module and SBC Express;
   ZII SCU2 Mezz, SCU3 ESB, SSMB SPU3 and CFU1 board; i.MX6SLL EVK
   board; Engicam i.CoreM6 1.5 Quad/Dual MIPI; LogicPD MX31Lite board;
   i.MX53 HSC/DDC boards from K+P.
 - Remove fake regulator bus container node and enable USB OTG support
   for i.MX6 wandboard and riotboard.
 - Populate RAVE SP EEPROM, backlight, power button and watchdog devices
   for ZII boards.
 - Add cooling-cells for cpufreq cooling device, and add OPP properties
   for all CPUs.
 - A series from Anson Huang to enable LCD panel and backlight support
   for imx6sll-evk board.
 - Make pfuze100 sw4 regulator always-on for for a few Freescale/NXP
   development boards, because the regulator is critical there and
   cannot be turned off.
 - Add more device support for i.MX5: AIPSTZ, SAHARA Crypto, M4IF,
   Tigerp, PMU, CodaHx4 VPU.
 - Enable PMU secure-reg-access for imx51-babbage, imx51-zii-rdu1 and
   imx53-ppd board.
 - Switch more device tree license to use SPDX identifier.
 - Switch to use OF graph to describe the display for imx7d-nitrogen7.
 - Add chosen/stdout-path for more boards, so that earlycon can be
   enabled more easily on kernel cmdline.
 - Convert GPC to new device tree bindings and add Vivante gpu nodes
   for i.MX6SL SoC.
 - Add more device support for imx6dl-mamoj board: parallel display,
   WiFi and USB.
 - A series from Stefan Agner to update i.MX6 apalis/colibri boards on
   various aspects: SD/MMC card detection, regulators, etc.

* tag 'imx-dt-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (96 commits)
  ARM: dts: imx7d: remove "operating-points" property for cpu1
  ARM: dts: vf610-zii-ssmb-spu3: Fix W=1 level warnings
  ARM: dts: vf610: Add ZII CFU1 board
  ARM: dts: imx6dl-mamoj: Add usb host and device support
  ARM: dts: imx6dl-mamoj: Add Wifi support
  ARM: dts: imx6dl-mamoj: Add parallel display support
  ARM: dts: vf610: Add ZII SSMB SPU3 board
  ARM: dts: imx6ul-pico-hobbit: Do not hardcode the memory size
  ARM: dts: imx6sl-evk: make pfuze100 sw4 always on
  ARM: dts: imx6sll-evk: make pfuze100 sw4 always on
  ARM: dts: imx6sx-sdb-reva: make pfuze100 sw4 always on
  ARM: dts: imx6qdl-sabresd: make pfuze100 sw4 always on
  ARM: dts: imx6sl-evk: add missing GPIO iomux setting
  ARM: dts: imx51-zii-scu3-esb: Fix RAVE SP watchdog compatible string
  ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config
  ARM: dts: imx6sx-nitrogen6sx: remove obsolete display configuration
  ARM: dts: imx7d-nitrogen7: use OF graph to describe the display
  ARM: dts: imx: Switch Boundary Devices boards to SPDX identifier
  ARM: dts: imx6sl: Add vivante gpu nodes
  ARM: dts: imx6sll-evk: enable SEIKO 43WVF1G lcdif panel
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
73 files changed:
Documentation/devicetree/bindings/arm/freescale/m4if.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/freescale/tigerp.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/fsl.txt
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/imx31-lite.dts [new file with mode: 0644]
arch/arm/boot/dts/imx31.dtsi
arch/arm/boot/dts/imx50-evk.dts
arch/arm/boot/dts/imx50-pinfunc.h
arch/arm/boot/dts/imx50.dtsi
arch/arm/boot/dts/imx51-babbage.dts
arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
arch/arm/boot/dts/imx51-zii-rdu1.dts
arch/arm/boot/dts/imx51-zii-scu2-mezz.dts [new file with mode: 0644]
arch/arm/boot/dts/imx51-zii-scu3-esb.dts [new file with mode: 0644]
arch/arm/boot/dts/imx51.dtsi
arch/arm/boot/dts/imx53-kp-ddc.dts [new file with mode: 0644]
arch/arm/boot/dts/imx53-kp-hsc.dts [new file with mode: 0644]
arch/arm/boot/dts/imx53-kp.dtsi [new file with mode: 0644]
arch/arm/boot/dts/imx53-ppd.dts
arch/arm/boot/dts/imx53-qsb-common.dtsi
arch/arm/boot/dts/imx53.dtsi
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
arch/arm/boot/dts/imx6dl-icore-mipi.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6dl-mamoj.dts
arch/arm/boot/dts/imx6dl-nit6xlite.dts
arch/arm/boot/dts/imx6dl-nitrogen6x.dts
arch/arm/boot/dts/imx6dl-riotboard.dts
arch/arm/boot/dts/imx6dl.dtsi
arch/arm/boot/dts/imx6q-apalis-eval.dts
arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
arch/arm/boot/dts/imx6q-apalis-ixora.dts
arch/arm/boot/dts/imx6q-cm-fx6.dts
arch/arm/boot/dts/imx6q-icore-mipi.dts
arch/arm/boot/dts/imx6q-nitrogen6_max.dts
arch/arm/boot/dts/imx6q-nitrogen6_som2.dts
arch/arm/boot/dts/imx6q-nitrogen6x.dts
arch/arm/boot/dts/imx6q-var-dt6customboard.dts
arch/arm/boot/dts/imx6q.dtsi
arch/arm/boot/dts/imx6qdl-apalis.dtsi
arch/arm/boot/dts/imx6qdl-colibri.dtsi
arch/arm/boot/dts/imx6qdl-icore.dtsi
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
arch/arm/boot/dts/imx6qdl.dtsi
arch/arm/boot/dts/imx6qp-nitrogen6_max.dts
arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts
arch/arm/boot/dts/imx6sl-evk.dts
arch/arm/boot/dts/imx6sl.dtsi
arch/arm/boot/dts/imx6sll-evk.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6sll-pinfunc.h [new file with mode: 0644]
arch/arm/boot/dts/imx6sll.dtsi [new file with mode: 0644]
arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
arch/arm/boot/dts/imx6sx-sdb-reva.dts
arch/arm/boot/dts/imx6sx.dtsi
arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi [new file with mode: 0644]
arch/arm/boot/dts/imx6ul-pico-hobbit.dts
arch/arm/boot/dts/imx6ul.dtsi
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
arch/arm/boot/dts/imx6ull.dtsi
arch/arm/boot/dts/imx7d-nitrogen7.dts
arch/arm/boot/dts/imx7d-sdb.dts
arch/arm/boot/dts/imx7d.dtsi
arch/arm/boot/dts/imx7s.dtsi
arch/arm/boot/dts/ls1021a.dtsi
arch/arm/boot/dts/vf610-zii-cfu1.dts [new file with mode: 0644]
arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/arm/freescale/m4if.txt b/Documentation/devicetree/bindings/arm/freescale/m4if.txt
new file mode 100644 (file)
index 0000000..93bd7b8
--- /dev/null
@@ -0,0 +1,12 @@
+* Freescale Multi Master Multi Memory Interface (M4IF) module
+
+Required properties:
+- compatible : Should be "fsl,imx51-m4if"
+- reg : Address and length of the register set for the device
+
+Example:
+
+m4if: m4if@83fd8000 {
+       compatible = "fsl,imx51-m4if";
+       reg = <0x83fd8000 0x1000>;
+};
diff --git a/Documentation/devicetree/bindings/arm/freescale/tigerp.txt b/Documentation/devicetree/bindings/arm/freescale/tigerp.txt
new file mode 100644 (file)
index 0000000..19e2aad
--- /dev/null
@@ -0,0 +1,12 @@
+* Freescale Tigerp platform module
+
+Required properties:
+- compatible : Should be "fsl,imx51-tigerp"
+- reg : Address and length of the register set for the device
+
+Example:
+
+tigerp: tigerp@83fa0000 {
+       compatible = "fsl,imx51-tigerp";
+       reg = <0x83fa0000 0x28>;
+};
index cdb9dd705754a82928ffb90b7d67faf493104a24..8a1baa2b9723aa4014701260ab2597f2b8215281 100644 (file)
@@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board
 Required root node properties:
     - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
 
+i.MX6SLL EVK board
+Required root node properties:
+    - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
 Generic i.MX boards
 -------------------
 
index 992a347d51de4433b6ededc5dc259cc1495240d4..7f945eafe165a563b0c43cce8cd7ef2131606f65 100644 (file)
@@ -351,7 +351,8 @@ dtb-$(CONFIG_SOC_IMX27) += \
        imx27-phytec-phycore-rdk.dtb \
        imx27-phytec-phycard-s-rdk.dtb
 dtb-$(CONFIG_SOC_IMX31) += \
-       imx31-bug.dtb
+       imx31-bug.dtb \
+       imx31-lite.dtb
 dtb-$(CONFIG_SOC_IMX35) += \
        imx35-eukrea-mbimxsd35-baseboard.dtb \
        imx35-pdk.dtb
@@ -364,10 +365,14 @@ dtb-$(CONFIG_SOC_IMX51) += \
        imx51-digi-connectcore-jsk.dtb \
        imx51-eukrea-mbimxsd51-baseboard.dtb \
        imx51-ts4800.dtb \
-       imx51-zii-rdu1.dtb
+       imx51-zii-rdu1.dtb \
+       imx51-zii-scu2-mezz.dtb \
+       imx51-zii-scu3-esb.dtb
 dtb-$(CONFIG_SOC_IMX53) += \
        imx53-ard.dtb \
        imx53-cx9020.dtb \
+       imx53-kp-ddc.dtb \
+       imx53-kp-hsc.dtb \
        imx53-m53evk.dtb \
        imx53-mba53.dtb \
        imx53-ppd.dtb \
@@ -406,6 +411,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
        imx6dl-hummingboard2-emmc-som-v15.dtb \
        imx6dl-hummingboard2-som-v15.dtb \
        imx6dl-icore.dtb \
+       imx6dl-icore-mipi.dtb \
        imx6dl-icore-rqs.dtb \
        imx6dl-mamoj.dtb \
        imx6dl-nit6xlite.dtb \
@@ -527,6 +533,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 dtb-$(CONFIG_SOC_IMX6SL) += \
        imx6sl-evk.dtb \
        imx6sl-warp.dtb
+dtb-$(CONFIG_SOC_IMX6SLL) += \
+       imx6sll-evk.dtb
 dtb-$(CONFIG_SOC_IMX6SX) += \
        imx6sx-nitrogen6sx.dtb \
        imx6sx-sabreauto.dtb \
@@ -539,6 +547,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
        imx6sx-udoo-neo-full.dtb
 dtb-$(CONFIG_SOC_IMX6UL) += \
        imx6ul-14x14-evk.dtb \
+       imx6ul-ccimx6ulsbcexpress.dtb \
        imx6ul-geam.dtb \
        imx6ul-isiot-emmc.dtb \
        imx6ul-isiot-nand.dtb \
@@ -573,8 +582,10 @@ dtb-$(CONFIG_SOC_VF610) += \
        vf610-cosmic.dtb \
        vf610m4-cosmic.dtb \
        vf610-twr.dtb \
+       vf610-zii-cfu1.dtb \
        vf610-zii-dev-rev-b.dtb \
-       vf610-zii-dev-rev-c.dtb
+       vf610-zii-dev-rev-c.dtb \
+       vf610-zii-ssmb-spu3.dtb
 dtb-$(CONFIG_ARCH_MXS) += \
        imx23-evk.dtb \
        imx23-olinuxino.dtb \
diff --git a/arch/arm/boot/dts/imx31-lite.dts b/arch/arm/boot/dts/imx31-lite.dts
new file mode 100644 (file)
index 0000000..db52ddc
--- /dev/null
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
+
+/dts-v1/;
+
+#include "imx31.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       model = "LogicPD i.MX31 Lite";
+       compatible = "logicpd,imx31-lite", "fsl,imx31";
+
+       chosen {
+               stdout-path = &uart1;
+       };
+
+       memory@80000000 {
+               reg = <0x80000000 0x8000000>;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led0 {
+                       gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+               };
+
+               led1 {
+                       gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+               };
+       };
+};
+
+&ata {
+       status = "okay";
+};
+
+&nfc {
+       nand-bus-width = <8>;
+       nand-ecc-mode = "hw";
+       nand-on-flash-bbt;
+       status = "okay";
+};
+
+&sdhci1 {
+       bus-width = <4>;
+       cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+       wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&spi2 {
+       status = "okay";
+
+       pmic@0 {
+               compatible = "fsl,mc13783";
+               reg = <0>;
+               spi-cs-high;
+               spi-max-frequency = <1000000>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+
+               fsl,mc13xxx-uses-adc;
+               fsl,mc13xxx-uses-rtc;
+
+               regulators {
+                       sw1a {          /* QVCC */
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <1500000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       sw1b {          /* QVCC */
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <1500000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       sw2a {          /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       sw2b {          /* NVCC10 */
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       violo {         /* NVCC1 and NVCC7 */
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       viohi {         /* VIOHI */
+                               regulator-min-microvolt = <2775000>;
+                               regulator-max-microvolt = <2775000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       vaudio {        /* VAUDIO */
+                               regulator-min-microvolt = <2775000>;
+                               regulator-max-microvolt = <2775000>;
+                       };
+
+                       vcam {          /* NVCC4 */
+                               regulator-min-microvolt = <2800000>;
+                               regulator-max-microvolt = <2800000>;
+                       };
+
+                       vgen {          /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */
+                               regulator-min-microvolt = <2775000>;
+                               regulator-max-microvolt = <2775000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+
+                       vmmc2 {         /* NVCC3 */
+                               regulator-min-microvolt = <1600000>;
+                               regulator-max-microvolt = <3000000>;
+                               regulator-always-on;
+                               regulator-boot-on;
+                       };
+               };
+       };
+};
+
+&uart1 {
+       uart-has-rtscts;
+       status = "okay";
+};
+
+/* Routed to the extension board */
+&uart2 {
+       uart-has-rtscts;
+       status = "okay";
+};
+
+/* Routed to the extension board */
+&uart3 {
+       uart-has-rtscts;
+       status = "okay";
+};
+
+&weim {
+       status = "okay";
+
+       nor@0,0 {
+               compatible = "cfi-flash";
+               reg = <0 0x0 0x200000>;
+               bank-width = <2>;
+               linux,mtd-name = "physmap-flash.0";
+               fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>;
+       };
+
+       ethernet@4,0 {
+               compatible = "smsc,lan9117", "smsc,lan9115";
+               reg = <4 0x0 0x100>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+               phy-mode = "mii";
+               reg-io-width = <2>;
+               smsc,irq-push-pull;
+               fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>;
+       };
+};
index 4642c8169a65ba490a68e466b1e6e8a046719a58..ca1419ca303c3d5994a73b5bdddc9e69428dac55 100644 (file)
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 //
+// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
 // Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
 
 / {
        memory { device_type = "memory"; };
 
        aliases {
+               gpio0 = &gpio1;
+               gpio1 = &gpio2;
+               gpio2 = &gpio3;
+               i2c0 = &i2c1;
+               i2c1 = &i2c2;
+               i2c2 = &i2c3;
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
                serial3 = &uart4;
                serial4 = &uart5;
+               spi0 = &spi1;
+               spi1 = &spi2;
+               spi2 = &spi3;
        };
 
        cpus {
                interrupt-parent = <&avic>;
                ranges;
 
+               iram: iram@1fffc000 {
+                       compatible = "mmio-sram";
+                       reg = <0x1fffc000 0x4000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x1fffc000 0x4000>;
+               };
+
                aips@43f00000 { /* AIPS1 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        reg = <0x43f00000 0x100000>;
                        ranges;
 
+                       i2c1: i2c@43f80000 {
+                               compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
+                               reg = <0x43f80000 0x4000>;
+                               interrupts = <10>;
+                               clocks = <&clks 33>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       i2c3: i2c@43f84000 {
+                               compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
+                               reg = <0x43f84000 0x4000>;
+                               interrupts = <3>;
+                               clocks = <&clks 35>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       ata: ata@43f8c000 {
+                               compatible = "fsl,imx31-pata", "fsl,imx27-pata";
+                               reg = <0x43f8c000 0x4000>;
+                               interrupts = <15>;
+                               clocks = <&clks 26>;
+                               status = "disabled";
+                       };
+
                        uart1: serial@43f90000 {
                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
                                reg = <0x43f90000 0x4000>;
                                status = "disabled";
                        };
 
+                       i2c2: i2c@43f98000 {
+                               compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
+                               reg = <0x43f98000 0x4000>;
+                               interrupts = <4>;
+                               clocks = <&clks 34>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spi1: spi@43fa4000 {
+                               compatible = "fsl,imx31-cspi";
+                               reg = <0x43fa4000 0x4000>;
+                               interrupts = <14>;
+                               clocks = <&clks 10>, <&clks 53>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
+                               dma-names = "rx", "tx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
                        kpp: kpp@43fa8000 {
                                compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
                                reg = <0x43fa8000 0x4000>;
                        reg = <0x50000000 0x100000>;
                        ranges;
 
+                       sdhci1: sdhci@50004000 {
+                               compatible = "fsl,imx31-mmc";
+                               reg = <0x50004000 0x4000>;
+                               interrupts = <9>;
+                               clocks = <&clks 10>, <&clks 20>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma 20 3 0>;
+                               dma-names = "rx-tx";
+                               status = "disabled";
+                       };
+
+                       sdhci2: sdhci@50008000 {
+                               compatible = "fsl,imx31-mmc";
+                               reg = <0x50008000 0x4000>;
+                               interrupts = <8>;
+                               clocks = <&clks 10>, <&clks 21>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma 21 3 0>;
+                               dma-names = "rx-tx";
+                               status = "disabled";
+                       };
+
                        uart3: serial@5000c000 {
                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
                                reg = <0x5000c000 0x4000>;
                                status = "disabled";
                        };
 
+                       spi2: cspi@50010000 {
+                               compatible = "fsl,imx31-cspi";
+                               reg = <0x50010000 0x4000>;
+                               interrupts = <13>;
+                               clocks = <&clks 10>, <&clks 54>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
+                               dma-names = "rx", "tx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
                        iim: iim@5001c000 {
                                compatible = "fsl,imx31-iim", "fsl,imx27-iim";
                                reg = <0x5001c000 0x1000>;
                                #clock-cells = <1>;
                        };
 
+                       spi3: cspi@53f84000 {
+                               compatible = "fsl,imx31-cspi";
+                               reg = <0x53f84000 0x4000>;
+                               interrupts = <17>;
+                               clocks = <&clks 10>, <&clks 28>;
+                               clock-names = "ipg", "per";
+                               dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
+                               dma-names = "rx", "tx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
                        gpt: timer@53f90000 {
                                compatible = "fsl,imx31-gpt";
                                reg = <0x53f90000 0x4000>;
                                clocks = <&clks 10>, <&clks 22>;
                                clock-names = "ipg", "per";
                        };
+
+                       gpio3: gpio@53fa4000 {
+                               compatible = "fsl,imx31-gpio";
+                               reg = <0x53fa4000 0x4000>;
+                               interrupts = <56>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       rng@53fb0000 {
+                               compatible = "fsl,imx31-rnga";
+                               reg = <0x53fb0000 0x4000>;
+                               interrupts = <22>;
+                               clocks = <&clks 29>;
+                       };
+
+                       gpio1: gpio@53fcc000 {
+                               compatible = "fsl,imx31-gpio";
+                               reg = <0x53fcc000 0x4000>;
+                               interrupts = <52>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpio2: gpio@53fd0000 {
+                               compatible = "fsl,imx31-gpio";
+                               reg = <0x53fd0000 0x4000>;
+                               interrupts = <51>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       sdma: sdma@53fd4000 {
+                               compatible = "fsl,imx31-sdma";
+                               reg = <0x53fd4000 0x4000>;
+                               interrupts = <34>;
+                               clocks = <&clks 10>, <&clks 27>;
+                               clock-names = "ipg", "ahb";
+                               #dma-cells = <3>;
+                               fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
+                       };
+
+                       rtc: rtc@53fd8000 {
+                               compatible = "fsl,imx31-rtc", "fsl,imx21-rtc";
+                               reg = <0x53fd8000 0x4000>;
+                               interrupts = <25>;
+                               clocks = <&clks 2>, <&clks 40>;
+                               clock-names = "ref", "ipg";
+                       };
+
+                       wdog: wdog@53fdc000 {
+                               compatible = "fsl,imx31-wdt", "fsl,imx21-wdt";
+                               reg = <0x53fdc000 0x4000>;
+                               clocks = <&clks 41>;
+                       };
+
+                       pwm: pwm@53fe0000 {
+                               compatible = "fsl,imx31-pwm", "fsl,imx27-pwm";
+                               reg = <0x53fe0000 0x4000>;
+                               interrupts = <26>;
+                               clocks = <&clks 10>, <&clks 42>;
+                               clock-names = "ipg", "per";
+                               #pwm-cells = <2>;
+                               status = "disabled";
+                       };
+               };
+
+               emi@b8000000 { /* External Memory Interface */
+                       compatible = "simple-bus";
+                       reg = <0xb8000000 0x5000>;
+                       ranges;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       nfc: nand@b8000000 {
+                               compatible = "fsl,imx31-nand", "fsl,imx27-nand";
+                               reg = <0xb8000000 0x1000>;
+                               interrupts = <33>;
+                               clocks = <&clks 9>;
+                               dmas = <&sdma 30 17 0>;
+                               dma-names = "rx-tx";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               status = "disabled";
+                       };
+
+                       weim: weim@b8002000 {
+                               compatible = "fsl,imx31-weim", "fsl,imx27-weim";
+                               reg = <0xb8002000 0x1000>;
+                               clocks = <&clks 56>;
+                               #address-cells = <2>;
+                               #size-cells = <1>;
+                               ranges = <0 0 0xa0000000 0x08000000
+                                         1 0 0xa8000000 0x08000000
+                                         2 0 0xb0000000 0x02000000
+                                         3 0 0xb2000000 0x02000000
+                                         4 0 0xb4000000 0x02000000
+                                         5 0 0xb6000000 0x02000000>;
+                               status = "disabled";
+                       };
                };
        };
 };
index f0622ec4ba9c34ae636bac7fbc765a38babc240a..682a99783ee69b24485315576f3852e278ac3081 100644 (file)
        status = "okay";
 };
 
-&usbh2 {
-       status = "okay";
-};
-
-&usbh3 {
-       status = "okay";
-};
-
 &usbotg {
        status = "okay";
 };
index 97e6e7f4ebddf4a0c5cef086d4690138ee849f16..43863347362e83adefbff9ebecc018a3e3ae220c 100644 (file)
@@ -34,7 +34,7 @@
 #define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1                     0x02c 0x2d8 0x000 0x2 0x0
 #define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7                    0x02c 0x2d8 0x000 0x6 0x0
 #define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR                     0x02c 0x2d8 0x000 0x7 0x0
-#define MX50_PAD_KEY_COL2__KPP_COL_1                           0x030 0x2dc 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL2__KPP_COL_2                           0x030 0x2dc 0x000 0x0 0x0
 #define MX50_PAD_KEY_COL2__GPIO4_4                             0x030 0x2dc 0x000 0x1 0x0
 #define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2                     0x030 0x2dc 0x000 0x2 0x0
 #define MX50_PAD_KEY_COL2__CTI_TRIGOUT6                                0x030 0x2dc 0x000 0x6 0x0
@@ -44,7 +44,7 @@
 #define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3                     0x034 0x2e0 0x000 0x2 0x0
 #define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7                                0x034 0x2e0 0x000 0x6 0x0
 #define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0                 0x034 0x2e0 0x000 0x7 0x0
-#define MX50_PAD_KEY_COL3__KPP_COL_2                           0x038 0x2e4 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL3__KPP_COL_3                           0x038 0x2e4 0x000 0x0 0x0
 #define MX50_PAD_KEY_COL3__GPIO4_6                             0x038 0x2e4 0x000 0x1 0x0
 #define MX50_PAD_KEY_COL3__EIM_NANDF_READY0                    0x038 0x2e4 0x7b4 0x2 0x0
 #define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0                    0x038 0x2e4 0x7b8 0x6 0x0
index a9b712db9f6c3131158661f684ad26ae9e23efdf..7fae2ffb76fe2e63ecb4fe8a515b61a65dd99421 100644 (file)
                                status = "disabled";
                        };
 
-                       usbh2: usb@53f80400 {
-                               compatible = "fsl,imx50-usb", "fsl,imx27-usb";
-                               reg = <0x53f80400 0x0200>;
-                               interrupts = <16>;
-                               clocks = <&clks IMX5_CLK_USBOH3_GATE>;
-                               dr_mode = "host";
-                               status = "disabled";
-                       };
-
-                       usbh3: usb@53f80600 {
-                               compatible = "fsl,imx50-usb", "fsl,imx27-usb";
-                               reg = <0x53f80600 0x0200>;
-                               interrupts = <17>;
-                               clocks = <&clks IMX5_CLK_USBOH3_GATE>;
-                               dr_mode = "host";
-                               status = "disabled";
-                       };
-
                        gpio1: gpio@53f84000 {
                                compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
                                reg = <0x53f84000 0x4000>;
index b8ca73d3d379270a6621fa1ae2cf6f353cd8930d..ba60b0cb3cc13ba08c9c414d7b8c317cc936ad7e 100644 (file)
                mux-ext-port = <3>;
        };
 
-       usbphy {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               compatible = "simple-bus";
-
-               usbh1phy: usbh1phy@0 {
-                       compatible = "usb-nop-xceiv";
-                       reg = <0>;
-                       clocks = <&clk_usb>;
-                       clock-names = "main_clk";
-                       reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
-                       vcc-supply = <&vusb_reg>;
-                       #phy-cells = <0>;
-               };
+       usbphy1: usbphy1 {
+               compatible = "usb-nop-xceiv";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usbh1reg>;
+               clocks = <&clk_usb>;
+               clock-names = "main_clk";
+               reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+               vcc-supply = <&vusb_reg>;
+               #phy-cells = <0>;
        };
 };
 
        status = "okay";
 };
 
+&pmu {
+       secure-reg-access;
+};
+
 &ssi2 {
        status = "okay";
 };
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usbh1>;
        vbus-supply = <&reg_hub_reset>;
-       fsl,usbphy = <&usbh1phy>;
+       fsl,usbphy = <&usbphy1>;
        phy_type = "ulpi";
        status = "okay";
 };
index b3d952f37cdc9f35c29a9a5039fd5df5f8d9c49b..e9e819f2b0b7d72b87c05f5e6497dc5e669f7a5b 100644 (file)
                fsl,mux-ext-port = <3>;
        };
 
-       usbphy {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               compatible = "simple-bus";
-
-               usbh1phy: usbh1phy@0 {
-                       compatible = "usb-nop-xceiv";
-                       reg = <0>;
-                       clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
-                       clock-names = "main_clk";
-                       clock-frequency = <19200000>;
-                       #phy-cells = <0>;
-               };
+       usbphy1: usbphy1 {
+               compatible = "usb-nop-xceiv";
+               clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
+               clock-names = "main_clk";
+               clock-frequency = <19200000>;
+               #phy-cells = <0>;
        };
 };
 
 &usbh1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usbh1>;
-       fsl,usbphy = <&usbh1phy>;
+       fsl,usbphy = <&usbphy1>;
        dr_mode = "host";
        phy_type = "ulpi";
        status = "okay";
index df9eca94d812290afe03affd59f76663ea1ab0ee..60b4d71c0dfece528fff2edc94d0378da09da240 100644 (file)
        status = "okay";
 };
 
+&gpio1 {
+       unused-sd3-wp-gpio {
+               /*
+                * See pinctrl_esdhc1 below for more details on this
+                */
+               gpio-hog;
+               gpios = <1 GPIO_ACTIVE_HIGH>;
+               output-high;
+       };
+};
+
 &i2c2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c2>;
 
                rmi4-f11@11 {
                        reg = <0x11>;
-                       touchscreen-inverted-y;
+                       touchscreen-inverted-x;
                        touchscreen-swapped-x-y;
                        syna,sensor-type = <1>;
                };
        remote-endpoint = <&display_in>;
 };
 
+&pmu {
+       secure-reg-access;
+};
+
 &ssi2 {
        status = "okay";
 };
        rave-sp {
                compatible = "zii,rave-sp-rdu1";
                current-speed = <38400>;
+               #address-cells = <1>;
+               #size-cells = <1>;
 
                watchdog {
                        compatible = "zii,rave-sp-watchdog";
                };
+
+               backlight {
+                       compatible = "zii,rave-sp-backlight";
+               };
+
+               pwrbutton {
+                       compatible = "zii,rave-sp-pwrbutton";
+               };
+
+               eeprom@a3 {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xa3 0x2000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       zii,eeprom-name = "dds-eeprom";
+               };
+
+               eeprom@a4 {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xa4 0x4000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       zii,eeprom-name = "main-eeprom";
+               };
+
+               eeprom@ae {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xae 0x200>;
+                       zii,eeprom-name = "switch-eeprom";
+                       /*
+                        * Not all RDU1s have this functionality, so we
+                        * rely on the bootloader to enable this
+                        */
+                       status = "disabled";
+               };
        };
 };
 
        status = "okay";
 };
 
+&wdog1 {
+       status = "disabled";
+};
+
 &iomuxc {
        pinctrl_ampgpio: ampgpiogrp {
                fsl,pins = <
                        MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
                        MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
                        MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
+                       /*
+                        * GPIO1_1 is not directly used by eSDHC1 in
+                        * any capacity, but earlier versions of RDU1
+                        * used that pin as WP GPIO for eSDHC3 and
+                        * because of that that pad has an external
+                        * pull-up resistor. This is problematic
+                        * because out of reset the pad is configured
+                        * as ALT0 which serves as SD1_WP, which, when
+                        * pulled high by and external pull-up, will
+                        * inhibit execution of any write request to
+                        * attached eMMC device.
+                        *
+                        * To avoid this problem we configure the pad
+                        * to ALT1/GPIO and avoid driving SD1_WP
+                        * signal high.
+                        */
+                       MX51_PAD_GPIO1_1__GPIO1_1               0x0000
                >;
        };
 
diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
new file mode 100644 (file)
index 0000000..26cf085
--- /dev/null
@@ -0,0 +1,448 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ */
+
+/dts-v1/;
+
+#include "imx51.dtsi"
+
+/ {
+       model = "ZII SCU2 Mezz Board";
+       compatible = "zii,imx51-scu2-mezz", "fsl,imx51";
+
+       chosen {
+               stdout-path = &uart1;
+       };
+
+       /* Will be filled by the bootloader */
+       memory@90000000 {
+               reg = <0x90000000 0>;
+       };
+
+       aliases {
+               mdio-gpio0 = &mdio_gpio;
+       };
+
+       usb_vbus: regulator-usb-vbus {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usb_mmc_reset>;
+               gpio = <&gpio3 13 GPIO_ACTIVE_LOW>;
+               startup-delay-us = <150000>;
+               regulator-name = "usb_vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+       };
+
+       mdio_gpio: mdio-gpio {
+               compatible = "virtual,mdio-gpio";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_swmdio>;
+               gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */
+                       <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               switch@0 {
+                       compatible = "marvell,mv88e6085";
+                       reg = <0>;
+                       dsa,member = <0 0>;
+                       eeprom-length = <512>;
+                       interrupt-parent = <&gpio1>;
+                       interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       label = "port4";
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       label = "port5";
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+                                       label = "port6";
+                               };
+
+                               port@3 {
+                                       reg = <3>;
+                                       label = "port7";
+                               };
+
+                               port@4 {
+                                       reg = <4>;
+                                       label = "cpu";
+                                       ethernet = <&fec>;
+
+                                       fixed-link {
+                                               speed = <100>;
+                                               full-duplex;
+                                       };
+                               };
+
+                               port@5 {
+                                       reg = <5>;
+                                       label = "mezz2esb";
+                                       phy-mode = "sgmii";
+
+                                       fixed-link {
+                                               speed = <1000>;
+                                               full-duplex;
+                                       };
+                               };
+                       };
+               };
+       };
+};
+
+&cpu {
+       cpu-supply = <&sw1_reg>;
+};
+
+&ecspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi1>;
+       cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
+                  <&gpio4 25 GPIO_ACTIVE_LOW>;
+       status = "okay";
+
+       pmic@0 {
+               compatible = "fsl,mc13892";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pmic>;
+               spi-max-frequency = <6000000>;
+               spi-cs-high;
+               reg = <0>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+               fsl,mc13xxx-uses-adc;
+
+               regulators {
+                       sw1_reg: sw1 {
+                               regulator-min-microvolt = <600000>;
+                               regulator-max-microvolt = <1375000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw2_reg: sw2 {
+                               regulator-min-microvolt = <900000>;
+                               regulator-max-microvolt = <1850000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw3_reg: sw3 {
+                               regulator-min-microvolt = <1100000>;
+                               regulator-max-microvolt = <1850000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw4_reg: sw4 {
+                               regulator-min-microvolt = <1100000>;
+                               regulator-max-microvolt = <1850000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vpll_reg: vpll {
+                               regulator-min-microvolt = <1050000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vdig_reg: vdig {
+                               regulator-min-microvolt = <1650000>;
+                               regulator-max-microvolt = <1650000>;
+                               regulator-boot-on;
+                       };
+
+                       vsd_reg: vsd {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3150000>;
+                               regulator-always-on;
+                       };
+
+                       vusb_reg: vusb {
+                               regulator-always-on;
+                       };
+
+                       vusb2_reg: vusb2 {
+                               regulator-min-microvolt = <2400000>;
+                               regulator-max-microvolt = <2775000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vvideo_reg: vvideo {
+                               regulator-min-microvolt = <2775000>;
+                               regulator-max-microvolt = <2775000>;
+                       };
+
+                       vaudio_reg: vaudio {
+                               regulator-min-microvolt = <2300000>;
+                               regulator-max-microvolt = <3000000>;
+                       };
+
+                       vcam_reg: vcam {
+                               regulator-min-microvolt = <2500000>;
+                               regulator-max-microvolt = <3000000>;
+                       };
+
+                       vgen1_reg: vgen1 {
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <1200000>;
+                       };
+
+                       vgen2_reg: vgen2 {
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <3150000>;
+                               regulator-always-on;
+                       };
+
+                       vgen3_reg: vgen3 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <2900000>;
+                               regulator-always-on;
+                       };
+               };
+
+               leds {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       led-control = <0x0 0x0 0x3f83f8 0x0>;
+
+                       sysled3: led3@3 {
+                               reg = <3>;
+                               label = "system:red:power";
+                               linux,default-trigger = "default-on";
+                       };
+
+                       sysled4: led4@4 {
+                               reg = <4>;
+                               label = "system:green:act";
+                               linux,default-trigger = "heartbeat";
+                       };
+               };
+       };
+
+       flash@1 {
+               compatible = "atmel,at45", "atmel,dataflash";
+               reg = <1>;
+               spi-max-frequency = <25000000>;
+       };
+};
+
+&esdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc1>;
+       bus-width = <8>;
+       non-removable;
+       no-1-8-v;
+       no-sdio;
+       no-sd;
+       status = "okay";
+};
+
+&esdhc4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc4>;
+       bus-width = <4>;
+       no-1-8-v;
+       no-sdio;
+       cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec>;
+       phy-mode = "mii";
+       status = "okay";
+       phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <1>;
+       phy-supply = <&vgen3_reg>;
+       phy-handle = <&ethphy>;
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy: ethernet-phy@0 {
+                       reg = <0>;
+                       max-speed = <100>;
+               };
+       };
+};
+
+&i2c2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       eeprom@50 {
+               compatible = "atmel,24c04";
+               pagesize = <16>;
+               reg = <0x50>;
+       };
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       status = "okay";
+};
+
+&uart3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3>;
+       status = "okay";
+
+       rave-sp {
+               compatible = "zii,rave-sp-mezz";
+               current-speed = <57600>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               watchdog {
+                       compatible = "zii,rave-sp-watchdog-legacy";
+               };
+
+               eeprom@a4 {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xa4 0x4000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       zii,eeprom-name = "main-eeprom";
+               };
+       };
+};
+
+&usbotg {
+       dr_mode = "host";
+       disable-over-current;
+       phy_type = "utmi_wide";
+       vbus-supply = <&usb_vbus>;
+       status = "okay";
+};
+
+&usbphy0 {
+       vcc-supply = <&vusb2_reg>;
+};
+
+&iomuxc {
+       pinctrl_ecspi1: ecspi1grp {
+               fsl,pins = <
+                       MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
+                       MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
+                       MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
+                       MX51_PAD_CSPI1_SS0__GPIO4_24            0x85
+                       MX51_PAD_CSPI1_SS1__GPIO4_25            0x85
+               >;
+       };
+
+       pinctrl_esdhc1: esdhc1grp {
+               fsl,pins = <
+                       MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
+                       MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
+                       MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
+                       MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
+                       MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
+                       MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
+                       MX51_PAD_SD2_DATA0__SD1_DAT4            0x20d5
+                       MX51_PAD_SD2_DATA1__SD1_DAT5            0x20d5
+                       MX51_PAD_SD2_DATA2__SD1_DAT6            0x20d5
+                       MX51_PAD_SD2_DATA3__SD1_DAT7            0x20d5
+               >;
+       };
+
+       pinctrl_esdhc4: esdhc4grp {
+               fsl,pins = <
+                       MX51_PAD_NANDF_RB1__SD4_CMD             0x400020d5
+                       MX51_PAD_NANDF_CS2__SD4_CLK             0x20d5
+                       MX51_PAD_NANDF_CS3__SD4_DAT0            0x20d5
+                       MX51_PAD_NANDF_CS4__SD4_DAT1            0x20d5
+                       MX51_PAD_NANDF_CS5__SD4_DAT2            0x20d5
+                       MX51_PAD_NANDF_CS6__SD4_DAT3            0x20d5
+                       MX51_PAD_NANDF_D0__GPIO4_8              0x100
+               >;
+       };
+
+       pinctrl_fec: fecgrp {
+               fsl,pins = <
+                       MX51_PAD_DISP2_DAT15__FEC_TDATA0        0x2004
+                       MX51_PAD_DISP2_DAT6__FEC_TDATA1         0x2004
+                       MX51_PAD_DISP2_DAT7__FEC_TDATA2         0x2004
+                       MX51_PAD_DISP2_DAT8__FEC_TDATA3         0x2004
+                       MX51_PAD_DISP2_DAT9__FEC_TX_EN          0x2004
+                       MX51_PAD_DISP2_DAT10__FEC_COL           0x0180
+                       MX51_PAD_DISP2_DAT11__FEC_RX_CLK        0x0180
+                       MX51_PAD_DISP2_DAT12__FEC_RX_DV         0x20a4
+                       MX51_PAD_DISP2_DAT1__FEC_RX_ER          0x20a4
+                       MX51_PAD_DISP2_DAT13__FEC_TX_CLK        0x2180
+                       MX51_PAD_DI_GP3__FEC_TX_ER              0x2004
+                       MX51_PAD_DISP2_DAT14__FEC_RDATA0        0x2180
+                       MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       0x0085
+                       MX51_PAD_DI_GP4__FEC_RDATA2             0x0085
+                       MX51_PAD_DISP2_DAT0__FEC_RDATA3         0x0085
+                       MX51_PAD_DI2_PIN2__FEC_MDC              0x2004
+                       MX51_PAD_DI2_PIN3__FEC_MDIO             0x01f5
+                       MX51_PAD_DI2_PIN4__FEC_CRS              0x0180
+                       MX51_PAD_EIM_A20__GPIO2_14              0x0085
+                       MX51_PAD_EIM_A21__GPIO2_15              0x00e5
+               >;
+       };
+
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
+                       MX51_PAD_KEY_COL5__I2C2_SDA             0x400001ed
+               >;
+       };
+
+       pinctrl_pmic: pmicgrp {
+               fsl,pins = <
+                       MX51_PAD_GPIO1_4__GPIO1_4               0x85
+                       MX51_PAD_GPIO1_8__GPIO1_8               0xe5
+               >;
+       };
+
+       pinctrl_swmdio: swmdiogrp {
+               fsl,pins = <
+                       MX51_PAD_EIM_D22__GPIO2_6               0x100
+                       MX51_PAD_EIM_D23__GPIO2_7               0x100
+               >;
+       };
+
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
+                       MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
+               >;
+       };
+
+       pinctrl_uart3: uart3grp {
+               fsl,pins = <
+                       MX51_PAD_UART3_RXD__UART3_RXD           0x1c5
+                       MX51_PAD_UART3_TXD__UART3_TXD           0x1c5
+               >;
+       };
+
+       pinctrl_usb_mmc_reset: usbmmcgrp {
+               fsl,pins = <
+                       MX51_PAD_CSI1_D9__GPIO3_13              0x85
+               >;
+       };
+};
diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts
new file mode 100644 (file)
index 0000000..e6ebac8
--- /dev/null
@@ -0,0 +1,467 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ */
+
+/dts-v1/;
+
+#include "imx51.dtsi"
+
+/ {
+       model = "ZII SCU3 ESB board";
+       compatible = "zii,imx51-scu3-esb", "fsl,imx51";
+
+       chosen {
+               stdout-path = &uart1;
+       };
+
+       /* Will be filled by the bootloader */
+       memory@90000000 {
+               reg = <0x90000000 0>;
+       };
+
+       usb_vbus: regulator-usb-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "usb_vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usb_mmc_reset>;
+               gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
+               startup-delay-us = <150000>;
+       };
+};
+
+&cpu {
+       cpu-supply = <&sw1_reg>;
+};
+
+&ecspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi1>;
+       cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
+                  <&gpio4 25 GPIO_ACTIVE_LOW>;
+       status = "okay";
+
+       pmic@0 {
+               compatible = "fsl,mc13892";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pmic>;
+               spi-max-frequency = <6000000>;
+               spi-cs-high;
+               reg = <0>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+               fsl,mc13xxx-uses-adc;
+
+               regulators {
+                       sw1_reg: sw1 {
+                               regulator-min-microvolt = <600000>;
+                               regulator-max-microvolt = <1375000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw2_reg: sw2 {
+                               regulator-min-microvolt = <900000>;
+                               regulator-max-microvolt = <1850000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw3_reg: sw3 {
+                               regulator-min-microvolt = <1100000>;
+                               regulator-max-microvolt = <1850000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw4_reg: sw4 {
+                               regulator-min-microvolt = <1100000>;
+                               regulator-max-microvolt = <1850000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vpll_reg: vpll {
+                               regulator-min-microvolt = <1050000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vdig_reg: vdig {
+                               regulator-min-microvolt = <1650000>;
+                               regulator-max-microvolt = <1650000>;
+                               regulator-boot-on;
+                       };
+
+                       vsd_reg: vsd {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3150000>;
+                       };
+
+                       vusb_reg: vusb {
+                               regulator-always-on;
+                       };
+
+                       vusb2_reg: vusb2 {
+                               regulator-min-microvolt = <2400000>;
+                               regulator-max-microvolt = <2775000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vvideo_reg: vvideo {
+                               regulator-min-microvolt = <2775000>;
+                               regulator-max-microvolt = <2775000>;
+                       };
+
+                       vaudio_reg: vaudio {
+                               regulator-min-microvolt = <2300000>;
+                               regulator-max-microvolt = <3000000>;
+                       };
+
+                       vcam_reg: vcam {
+                               regulator-min-microvolt = <2500000>;
+                               regulator-max-microvolt = <3000000>;
+                       };
+
+                       vgen1_reg: vgen1 {
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <1200000>;
+                       };
+
+                       vgen2_reg: vgen2 {
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <3150000>;
+                               regulator-always-on;
+                       };
+
+                       vgen3_reg: vgen3 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <2900000>;
+                               regulator-always-on;
+                       };
+               };
+
+               leds {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       led-control = <0x0 0x0 0x3f83f8 0x0>;
+
+                       sysled3: led3@3 {
+                               reg = <3>;
+                               label = "system:red:power";
+                               linux,default-trigger = "default-on";
+                       };
+
+                       sysled4: led4@4 {
+                               reg = <4>;
+                               label = "system:green:act";
+                               linux,default-trigger = "heartbeat";
+                       };
+               };
+       };
+
+       flash@1 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "atmel,at45", "atmel,dataflash";
+               spi-max-frequency = <25000000>;
+               reg = <1>;
+       };
+};
+
+&esdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc1>;
+       bus-width = <8>;
+       non-removable;
+       no-1-8-v;
+       no-sdio;
+       no-sd;
+       status = "okay";
+};
+
+&esdhc4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_esdhc4>;
+       bus-width = <4>;
+       no-1-8-v;
+       no-sdio;
+       cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec>;
+       phy-mode = "mii";
+       status = "okay";
+
+       fixed-link {
+               speed = <100>;
+               full-duplex;
+       };
+
+       fec_mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "okay";
+
+               switch@0 {
+                       compatible = "marvell,mv88e6085";
+                       reg = <0>;
+                       dsa,member = <0 0>;
+                       eeprom-length = <512>;
+                       interrupt-parent = <&gpio4>;
+                       interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_switch>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       label = "port1";
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       label = "port2";
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+                                       label = "port3";
+                               };
+
+                               port@3 {
+                                       reg = <3>;
+                                       label = "scu2scu";
+                               };
+
+                               port@4 {
+                                       reg = <4>;
+                                       label = "esb2host";
+                               };
+
+                               port@5 {
+                                       reg = <5>;
+                                       label = "esb2mezz";
+                                       phy-mode = "sgmii";
+
+                                       fixed-link {
+                                               speed = <1000>;
+                                               full-duplex;
+                                       };
+                               };
+
+                               port@6 {
+                                       reg = <6>;
+                                       label = "cpu";
+                                       phy-mode = "mii";
+                                       ethernet = <&fec>;
+
+                                       fixed-link {
+                                               speed = <100>;
+                                               full-duplex;
+                                       };
+                               };
+                       };
+               };
+       };
+};
+
+&ipu {
+       status = "disabled";
+};
+
+&i2c2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       eeprom@50 {
+               compatible = "atmel,24c04";
+               pagesize = <16>;
+               reg = <0x50>;
+       };
+
+       lm75@48 {
+               compatible = "national,lm75";
+               reg = <0x48>;
+       };
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       status = "okay";
+};
+
+&uart3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3>;
+       status = "okay";
+
+       rave-sp {
+               compatible = "zii,rave-sp-esb";
+               current-speed = <57600>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               watchdog {
+                       compatible = "zii,rave-sp-watchdog-legacy";
+               };
+
+               eeprom@a4 {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xa4 0x4000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       zii,eeprom-name = "main-eeprom";
+               };
+       };
+};
+
+&usbotg {
+       dr_mode = "host";
+       disable-over-current;
+       phy_type = "utmi_wide";
+       vbus-supply = <&usb_vbus>;
+       status = "okay";
+};
+
+&usbphy0 {
+       vcc-supply = <&vusb2_reg>;
+};
+
+&wdog1 {
+       status = "disabled";
+};
+
+&iomuxc {
+       pinctrl_ecspi1: ecspi1grp {
+               fsl,pins = <
+                       MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
+                       MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
+                       MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
+                       MX51_PAD_CSPI1_SS0__GPIO4_24            0x85
+                       MX51_PAD_CSPI1_SS1__GPIO4_25            0x85
+               >;
+       };
+
+       pinctrl_esdhc1: esdhc1grp {
+               fsl,pins = <
+                       MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
+                       MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
+                       MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
+                       MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
+                       MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
+                       MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
+                       MX51_PAD_SD2_DATA0__SD1_DAT4            0x20d5
+                       MX51_PAD_SD2_DATA1__SD1_DAT5            0x20d5
+                       MX51_PAD_SD2_DATA2__SD1_DAT6            0x20d5
+                       MX51_PAD_SD2_DATA3__SD1_DAT7            0x20d5
+               >;
+       };
+
+       pinctrl_esdhc4: esdhc4grp {
+               fsl,pins = <
+                       MX51_PAD_NANDF_RB1__SD4_CMD             0x400020d5
+                       MX51_PAD_NANDF_CS2__SD4_CLK             0x20d5
+                       MX51_PAD_NANDF_CS3__SD4_DAT0            0x20d5
+                       MX51_PAD_NANDF_CS4__SD4_DAT1            0x20d5
+                       MX51_PAD_NANDF_CS5__SD4_DAT2            0x20d5
+                       MX51_PAD_NANDF_CS6__SD4_DAT3            0x20d5
+                       MX51_PAD_NANDF_D0__GPIO4_8              0x100
+               >;
+       };
+
+       pinctrl_fec: fecgrp {
+               fsl,pins = <
+                       MX51_PAD_DISP2_DAT15__FEC_TDATA0        0x2004
+                       MX51_PAD_DISP2_DAT6__FEC_TDATA1         0x2004
+                       MX51_PAD_DISP2_DAT7__FEC_TDATA2         0x2004
+                       MX51_PAD_DISP2_DAT8__FEC_TDATA3         0x2004
+                       MX51_PAD_DISP2_DAT9__FEC_TX_EN          0x2004
+                       MX51_PAD_DISP2_DAT10__FEC_COL           0x0180
+                       MX51_PAD_DISP2_DAT11__FEC_RX_CLK        0x0180
+                       MX51_PAD_DISP2_DAT12__FEC_RX_DV         0x20a4
+
+                       MX51_PAD_DISP2_DAT13__FEC_TX_CLK        0x2180
+                       MX51_PAD_DISP2_DAT14__FEC_RDATA0        0x2180
+                       MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       0x0085
+                       MX51_PAD_DI_GP4__FEC_RDATA2             0x0085
+                       MX51_PAD_DISP2_DAT0__FEC_RDATA3         0x0085
+                       MX51_PAD_DI2_PIN2__FEC_MDC              0x2004
+                       MX51_PAD_DI2_PIN3__FEC_MDIO             0x01f5
+                       MX51_PAD_DI2_PIN4__FEC_CRS              0x0180
+               >;
+       };
+
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
+                       MX51_PAD_KEY_COL5__I2C2_SDA             0x400001ed
+               >;
+       };
+
+       pinctrl_pmic: pmicgrp {
+               fsl,pins = <
+                       MX51_PAD_GPIO1_4__GPIO1_4               0x85
+                       MX51_PAD_GPIO1_8__GPIO1_8               0xe5
+               >;
+       };
+
+       pinctrl_switch: switchgrp {
+               fsl,pins = <
+                       MX51_PAD_AUD3_BB_CK__GPIO4_20           0xc5
+               >;
+       };
+
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
+                       MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
+                       MX51_PAD_UART1_RTS__UART1_RTS           0x1c5
+                       MX51_PAD_UART1_CTS__UART1_CTS           0x1c5
+               >;
+       };
+
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX51_PAD_UART2_RXD__UART2_RXD           0x1c5
+                       MX51_PAD_UART2_TXD__UART2_TXD           0x1c5
+                       MX51_PAD_USBH1_DATA0__UART2_CTS         0x1c5
+                       MX51_PAD_USBH1_DATA3__UART2_RTS         0x1c5
+               >;
+       };
+
+       pinctrl_uart3: uart3grp {
+               fsl,pins = <
+                       MX51_PAD_UART3_RXD__UART3_RXD           0x1c5
+                       MX51_PAD_UART3_TXD__UART3_TXD           0x1c5
+               >;
+       };
+
+       pinctrl_usb_mmc_reset: usbmmcgrp {
+               fsl,pins = <
+                       MX51_PAD_AUD3_BB_RXD__GPIO4_19          0x100
+               >;
+       };
+};
index fe01b890c715d19c7af3cd5ade82667fb3f72549..5c4ba91e43ba4b2e797d3d34dea32093f9a1f0e6 100644 (file)
                };
        };
 
-       usbphy {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               compatible = "simple-bus";
+       pmu: pmu {
+               compatible = "arm,cortex-a8-pmu";
+               interrupt-parent = <&tzic>;
+               interrupts = <77>;
+       };
 
-               usbphy0: usbphy@0 {
-                       compatible = "usb-nop-xceiv";
-                       reg = <0>;
-                       clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
-                       clock-names = "main_clk";
-                       #phy-cells = <0>;
-               };
+       usbphy0: usbphy0 {
+               compatible = "usb-nop-xceiv";
+               clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
+               clock-names = "main_clk";
+               #phy-cells = <0>;
        };
 
        display-subsystem {
                                };
                        };
 
+                       aipstz1: bridge@73f00000 {
+                               compatible = "fsl,imx51-aipstz";
+                               reg = <0x73f00000 0x60>;
+                       };
+
                        usbotg: usb@73f80000 {
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80000 0x0200>;
                        reg = <0x80000000 0x10000000>;
                        ranges;
 
+                       aipstz2: bridge@83f00000 {
+                               compatible = "fsl,imx51-aipstz";
+                               reg = <0x83f00000 0x60>;
+                       };
+
                        iim: iim@83f98000 {
                                compatible = "fsl,imx51-iim", "fsl,imx27-iim";
                                reg = <0x83f98000 0x4000>;
                                clocks = <&clks IMX5_CLK_IIM_GATE>;
                        };
 
+                       tigerp: tigerp@83fa0000 {
+                               compatible = "fsl,imx51-tigerp";
+                               reg = <0x83fa0000 0x28>;
+                       };
+
                        owire: owire@83fa4000 {
                                compatible = "fsl,imx51-owire", "fsl,imx21-owire";
                                reg = <0x83fa4000 0x4000>;
                                status = "disabled";
                        };
 
+                       m4if: m4if@83fd8000 {
+                               compatible = "fsl,imx51-m4if";
+                               reg = <0x83fd8000 0x1000>;
+                       };
+
                        weim: weim@83fda000 {
                                #address-cells = <2>;
                                #size-cells = <1>;
                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
                        };
+
+                       vpu@83ff4000 {
+                               compatible = "fsl,imx51-vpu", "cnm,codahx4";
+                               reg = <0x83ff4000 0x1000>;
+                               interrupts = <9>;
+                               clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
+                                        <&clks IMX5_CLK_VPU_GATE>;
+                               clock-names = "per", "ahb";
+                               resets = <&src 1>;
+                               iram = <&iram>;
+                       };
+
+                       sahara: crypto@83ff8000 {
+                               compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
+                               reg = <0x83ff8000 0x4000>;
+                               interrupts = <19 20>;
+                               clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
+                                        <&clks IMX5_CLK_SAHARA_IPG_GATE>;
+                               clock-names = "ipg", "ahb";
+                       };
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx53-kp-ddc.dts b/arch/arm/boot/dts/imx53-kp-ddc.dts
new file mode 100644 (file)
index 0000000..0e7f071
--- /dev/null
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/dts-v1/;
+#include "imx53-kp.dtsi"
+
+/ {
+       model = "K+P imx53 DDC";
+       compatible = "kiebackpeter,imx53-ddc", "fsl,imx53";
+
+       backlight_lcd: backlight {
+               compatible = "pwm-backlight";
+               pwms = <&pwm2 0 50000>;
+               power-supply = <&reg_backlight>;
+               brightness-levels = <0 24 28 32 36
+                                    40 44 48 52 56
+                                    60 64 68 72 76
+                                    80 84 88 92 96 100>;
+               default-brightness-level = <20>;
+       };
+
+       lcd_display: display {
+               compatible = "fsl,imx-parallel-display";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               interface-pix-fmt = "rgb24";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_disp>;
+
+               port@0 {
+                       reg = <0>;
+
+                       display1_in: endpoint {
+                               remote-endpoint = <&ipu_di1_disp1>;
+                       };
+               };
+
+               port@1 {
+                       reg = <1>;
+
+                       lcd_display_out: endpoint {
+                               remote-endpoint = <&lcd_panel_in>;
+                       };
+               };
+       };
+
+       lcd_panel: lcd-panel {
+               compatible = "koe,tx14d24vm1bpa";
+               backlight = <&backlight_lcd>;
+               power-supply = <&reg_3v3>;
+
+               port {
+                       lcd_panel_in: endpoint {
+                               remote-endpoint = <&lcd_display_out>;
+                       };
+               };
+       };
+
+       reg_backlight: regulator-backlight {
+               compatible = "regulator-fixed";
+               regulator-name = "backlight-supply";
+               regulator-min-microvolt = <15000000>;
+               regulator-max-microvolt = <15000000>;
+               regulator-always-on;
+       };
+};
+
+&fec {
+       status = "okay";
+};
+
+&i2c3 {
+       adc@48 {
+               compatible = "ti,ads1015";
+               reg = <0x48>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               channel@4 {
+                       reg = <4>;
+                       ti,gain = <2>;
+                       ti,datarate = <4>;
+               };
+
+               channel@6 {
+                       reg = <6>;
+                       ti,gain = <2>;
+                       ti,datarate = <4>;
+               };
+       };
+
+       gpio-expander2@21 {
+               compatible = "nxp,pcf8574";
+               reg = <0x21>;
+               interrupts = <109>;
+               #gpio-cells = <2>;
+               gpio-controller;
+       };
+};
+
+&iomuxc {
+       imx53-kp-ddc {
+               pinctrl_disp: dispgrp {
+                       fsl,pins = <
+                               MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x4
+                               MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x4
+                               MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x4
+                               MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x4
+                               MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x4
+                               MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x4
+                               MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x4
+                               MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x4
+                               MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x4
+                               MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x4
+                               MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x4
+                               MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x4
+                               MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x4
+                               MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x4
+                               MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x4
+                               MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x4
+                               MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x4
+                               MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x4
+                               MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x4
+                               MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x4
+                               MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x4
+                               MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x4
+                               MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x4
+                               MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x4
+                               MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x4
+                               MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x4
+                               MX53_PAD_GPIO_1__PWM2_PWMO 0x4
+                       >;
+               };
+       };
+};
+
+&ipu_di1_disp1 {
+       remote-endpoint = <&display1_in>;
+};
+
+&pmic {
+       fsl,mc13xxx-uses-touch;
+};
diff --git a/arch/arm/boot/dts/imx53-kp-hsc.dts b/arch/arm/boot/dts/imx53-kp-hsc.dts
new file mode 100644 (file)
index 0000000..6e3d71b
--- /dev/null
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/dts-v1/;
+#include "imx53-kp.dtsi"
+
+/ {
+       model = "K+P imx53 HSC";
+       compatible = "kiebackpeter,imx53-hsc", "fsl,imx53";
+};
+
+&fec {
+       status = "okay";
+
+       fixed-link { /* RMII fixed link to LAN9303 */
+               speed = <100>;
+               full-duplex;
+       };
+};
+
+&i2c3 {
+       switch: switch@a {
+               compatible = "smsc,lan9303-i2c";
+               reg = <0xa>;
+               reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+               reset-duration = <400>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 { /* RMII fixed link to master */
+                               reg = <0>;
+                               label = "cpu";
+                               ethernet = <&fec>;
+                       };
+
+                       port@1 { /* external port 1 */
+                               reg = <1>;
+                               label = "lan1";
+                       };
+
+                       port@2 { /* external port 2 */
+                               reg = <2>;
+                               label = "lan2";
+                       };
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/imx53-kp.dtsi b/arch/arm/boot/dts/imx53-kp.dtsi
new file mode 100644 (file)
index 0000000..8b25416
--- /dev/null
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/dts-v1/;
+#include "imx53-tqma53.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+       buzzer {
+               compatible = "pwm-beeper";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_buzzer>;
+               pwms = <&pwm1 0 500000>;
+       };
+
+       gpio-buttons {
+               compatible = "gpio-keys";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpiobuttons>;
+
+               button-kalt {
+                       label = "Kaltstart";
+                       linux,code = <KEY_F6>;
+                       gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+               };
+
+               button-pwr {
+                       label = "PowerFailInterrupt";
+                       linux,code = <KEY_F7>;
+                       gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_leds>;
+
+               led-bus {
+                       label = "bus";
+                       gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "gpio";
+                       default-state = "off";
+               };
+
+               led-error {
+                       label = "error";
+                       gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "gpio";
+                       default-state = "off";
+               };
+
+               led-flash {
+                       label = "flash";
+                       gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       reg_3v3: regulator-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+};
+
+&can1 {
+       status = "okay";
+};
+
+&can2 {
+       status = "okay";
+};
+
+&i2c3 {
+       status = "okay";
+
+       gpio-expander1@22 {
+               compatible = "nxp,pcf8574";
+               reg = <0x22>;
+               interrupts = <109>;
+               #gpio-cells = <2>;
+               gpio-controller;
+       };
+
+       rtc@51 {
+               compatible = "nxp,pcf8563";
+               reg = <0x51>;
+       };
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_kp_common>;
+
+       imx53-kp-common {
+               pinctrl_buzzer: buzzergrp {
+                       fsl,pins = <
+                               MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4
+                       >;
+               };
+
+               pinctrl_gpiobuttons: gpiobuttonsgrp {
+                       fsl,pins = <
+                               MX53_PAD_EIM_RW__GPIO2_26 0x1e4
+                               MX53_PAD_EIM_D22__GPIO3_22 0x1e4
+                       >;
+               };
+
+               pinctrl_kp_common: kpcommongrp {
+                       fsl,pins = <
+                               MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
+                               MX53_PAD_GPIO_19__GPIO4_5  0x1e4
+                               MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4
+                               MX53_PAD_PATA_DATA7__GPIO2_7 0xe0
+                               MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4
+                               MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4
+                               MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4
+                               MX53_PAD_EIM_D17__GPIO3_17 0x1e4
+                               MX53_PAD_EIM_D18__GPIO3_18 0x1e4
+                               MX53_PAD_EIM_D21__GPIO3_21 0x1e4
+                               MX53_PAD_EIM_D29__GPIO3_29 0x1e4
+                               MX53_PAD_EIM_DA11__GPIO3_11 0x1e4
+                               MX53_PAD_EIM_DA13__GPIO3_13 0x1e4
+                               MX53_PAD_EIM_DA14__GPIO3_14 0x1e4
+                               MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4
+                               MX53_PAD_SD1_CMD__GPIO1_18 0x1e4
+                               MX53_PAD_SD1_CLK__GPIO1_20 0x1e4
+                       >;
+               };
+
+               pinctrl_leds: ledgrp {
+                       fsl,pins = <
+                               MX53_PAD_EIM_EB2__GPIO2_30 0x1d4
+                               MX53_PAD_EIM_D28__GPIO3_28 0x1d4
+                               MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4
+                       >;
+               };
+
+               pinctrl_uart4: uart4grp {
+                       fsl,pins = <
+                               MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4
+                               MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4
+                       >;
+               };
+       };
+};
+
+&pinctrl_uart1 {
+       fsl,pins = <
+               MX53_PAD_EIM_D23__GPIO3_23 0x1e4
+               MX53_PAD_EIM_EB3__GPIO2_31 0x1e4
+               MX53_PAD_EIM_D24__GPIO3_24 0x1e4
+               MX53_PAD_EIM_D25__GPIO3_25 0x1e4
+               MX53_PAD_EIM_D19__GPIO3_19 0x1e4
+               MX53_PAD_EIM_D20__GPIO3_20 0x1e4
+       >;
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&uart2 {
+       status = "okay";
+};
+
+&uart3 {
+       status = "okay";
+};
+
+&uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart4>;
+       status = "okay";
+};
+
+&usbh1 {
+       status = "okay";
+};
+
+&usbphy0 {
+       status = "disabled";
+};
index 3aa6f693fa9fb51a02c2c1300849f979bf2b56c3..cdb90bee7b4a2b3d4d68681cc68c0c0efea7efae 100644 (file)
                regulator-always-on;
        };
 
+       reg_3v3: regulator-3v3 {
+               /* TPS54320 */
+               compatible = "regulator-fixed";
+               regulator-name = "3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+
+       reg_3v3_lcd: regulator-3v3-lcd {
+               /* MIC2009 */
+               compatible = "regulator-fixed";
+               regulator-name = "LCD_3V3";
+               vin-supply = <&reg_3v3>;
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+
        pwm_bl: backlight {
                compatible = "pwm-backlight";
                pwms = <&pwm2 0 50000>;
                                     234 237 239 242 244 247 249 252 255>;
                default-brightness-level = <0>;
                enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+               power-supply = <&reg_3v3_lcd>;
        };
 
        leds {
                };
        };
 
-       usbphy2: usbphy2 {
+       usbphy2: usbphy-2 {
                compatible = "usb-nop-xceiv";
+               vcc-supply = <&reg_3v3>;
                reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
                clock-names = "main_clk";
                clock-frequency = <24000000>;
                assigned-clock-parents = <&clks IMX5_CLK_OSC>;
        };
 
-       usbphy3: usbphy3 {
+       usbphy3: usbphy-3 {
                compatible = "usb-nop-xceiv";
+               vcc-supply = <&reg_3v3>;
                reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
                clock-names = "main_clk";
 
 
        panel-lvds0 {
                compatible = "nvd,9128";
+               power-supply = <&reg_3v3_lcd>;
 
                port {
                        panel_in_lvds0: endpoint {
        };
 };
 
+&usbphy0 {
+       vcc-supply = <&reg_3v3>;
+};
+
+&usbphy1 {
+       vcc-supply = <&reg_3v3>;
+};
+
 &audmux {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_audmux>;
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec>;
+       phy-supply = <&reg_3v3>;
        phy-mode = "rmii";
        phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
        status = "okay";
        };
 };
 
+&pmu {
+       secure-reg-access;
+};
+
 &pwm1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm1>;
index ef7658a788364dfff3d3f2a36cf3f0c4582218ef..7423d462d1e4229699f755a75e8237a06a51465c 100644 (file)
        imx53-qsb {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
-                               MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
                                MX53_PAD_GPIO_8__GPIO1_8          0x80000000
                                MX53_PAD_PATA_DATA14__GPIO2_14    0x80000000
                                MX53_PAD_PATA_DATA15__GPIO2_15    0x80000000
                        >;
                };
 
+               pinctrl_codec: codecgrp {
+                       fsl,pins = <
+                               MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK       0x1c4
+                       >;
+               };
+
                pinctrl_esdhc1: esdhc1grp {
                        fsl,pins = <
                                MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
        sgtl5000: codec@a {
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_codec>;
                #sound-dai-cells = <0>;
                VDDA-supply = <&reg_3p2v>;
                VDDIO-supply = <&reg_3p2v>;
index 1a7a7bb3df45f3d7854e41b5a654688fe9159fcc..6386185ae23403089e4cb9a5a7e6c559d5637750 100644 (file)
                };
        };
 
-       pmu {
+       pmu: pmu {
                compatible = "arm,cortex-a8-pmu";
                interrupt-parent = <&tzic>;
                interrupts = <77>;
                                status = "disabled";
                        };
 
+                       tigerp: tigerp@63fa0000 {
+                               compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp";
+                               reg = <0x63fa0000 0x28>;
+                       };
+
                        owire: owire@63fa4000 {
                                compatible = "fsl,imx53-owire", "fsl,imx21-owire";
                                reg = <0x63fa4000 0x4000>;
index 3dee3af1a4c1628fdad7613fdb75b3a38d427b16..9de45a7173561949a095a22a1cfcff7c9c459c25 100644 (file)
 
 /* Colibri MMC */
 &usdhc1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_mmc_cd>;
-       cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
        status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6dl-icore-mipi.dts b/arch/arm/boot/dts/imx6dl-icore-mipi.dts
new file mode 100644 (file)
index 0000000..bf53f05
--- /dev/null
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Engicam S.r.l.
+ * Copyright (C) 2018 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+       model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit";
+       compatible = "engicam,imx6-icore", "fsl,imx6dl";
+};
+
+&hdmi {
+       ddc-i2c-bus = <&i2c2>;
+       status = "okay";
+};
+
+&usdhc3 {
+       status = "okay";
+};
index 6b2d29138bedee1482198c9b3ff88b03910428fc..df8607fe414238cb0b1ca5562cba3e686d64fe51 100644 (file)
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include "imx6dl.dtsi"
 
 / {
        model = "BTicino i.MX6DL Mamoj board";
        compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
+
+       backlight_lcd: backlight-lcd {
+               compatible = "pwm-backlight";
+               pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */
+               brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>;
+               default-brightness-level = <7>;
+       };
+
+       display: disp0 {
+               compatible = "fsl,imx-parallel-display";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               interface-pix-fmt = "rgb24";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+               status = "okay";
+
+               port@0 {
+                       reg = <0>;
+
+                       lcd_display_in: endpoint {
+                               remote-endpoint = <&ipu1_di0_disp0>;
+                       };
+               };
+
+               port@1 {
+                       reg = <1>;
+
+                       lcd_display_out: endpoint {
+                               remote-endpoint = <&lcd_panel_in>;
+                       };
+               };
+       };
+
+       panel-lcd {
+               compatible = "rocktech,rk070er9427";
+               backlight = <&backlight_lcd>;
+               power-supply = <&reg_lcd_lr>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>;
+
+               port {
+                       lcd_panel_in: endpoint {
+                               remote-endpoint = <&lcd_display_out>;
+                       };
+               };
+       };
+
+       reg_lcd_3v3: regulator-lcd-dvdd {
+               compatible = "regulator-fixed";
+               regulator-name = "lcd-dvdd";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio3 1 0>;
+               enable-active-high;
+               startup-delay-us = <21000>;
+       };
+
+       reg_lcd_power: regulator-lcd-power {
+               compatible = "regulator-fixed";
+               regulator-name = "lcd-enable";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio3 6 0>;
+               enable-active-high;
+               vin-supply = <&reg_lcd_3v3>;
+       };
+
+       reg_lcd_vgl: regulator-lcd-vgl {
+               compatible = "regulator-fixed";
+               regulator-name = "lcd-vgl";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+               startup-delay-us = <6000>;
+               enable-active-high;
+               vin-supply = <&reg_lcd_power>;
+       };
+
+       reg_lcd_vgh: regulator-lcd-vgh {
+               compatible = "regulator-fixed";
+               regulator-name = "lcd-vgh";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
+               startup-delay-us = <6000>;
+               enable-active-high;
+               vin-supply = <&reg_lcd_avdd>;
+       };
+
+       reg_lcd_vcom: regulator-lcd-vcom {
+               compatible = "regulator-fixed";
+               regulator-name = "lcd-vcom";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>;
+               startup-delay-us = <11000>;
+               enable-active-high;
+               vin-supply = <&reg_lcd_vgh>;
+       };
+
+       reg_lcd_lr: regulator-lcd-lr {
+               compatible = "regulator-fixed";
+               regulator-name = "lcd-lr";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               vin-supply = <&reg_lcd_vcom>;
+       };
+
+       reg_lcd_avdd: regulator-lcd-avdd {
+               compatible = "regulator-fixed";
+               regulator-name = "lcd-avdd";
+               regulator-min-microvolt = <10280000>;
+               regulator-max-microvolt = <10280000>;
+               gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+               startup-delay-us = <6000>;
+               enable-active-high;
+               vin-supply = <&reg_lcd_vgl>;
+       };
+
+       reg_usb_host: regulator-usb-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "usbhost-vbus";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usbhost>;
+               regulator-min-microvolt = <50000000>;
+               regulator-max-microvolt = <50000000>;
+               gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_wl18xx_vmmc:  regulator-wl18xx-vmcc {
+               compatible = "regulator-fixed";
+               regulator-name = "vwl1807";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_wlan>;
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
+               startup-delay-us = <70000>;
+               enable-active-high;
+       };
 };
 
 &fec {
        };
 };
 
+&ipu1_di0_disp0 {
+       remote-endpoint = <&lcd_display_in>;
+};
+
+&pwm3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm3>;
+       status = "okay";
+};
+
 &uart3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart3>;
        status = "okay";
 };
 
+&usbh1 {
+       vbus-supply = <&reg_usb_host>;
+       status = "okay";
+};
+
+&usbotg {
+       dr_mode = "peripheral";
+       status = "okay";
+};
+
+&usdhc1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       bus-width = <4>;
+       vmmc-supply = <&reg_wl18xx_vmmc>;
+       no-1-8-v;
+       non-removable;
+       wakeup-source;
+       keep-power-in-suspend;
+       cap-power-off-card;
+       max-frequency = <25000000>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       wlcore: wlcore@2 {
+               compatible = "ti,wl1837";
+               reg = <2>;
+               interrupt-parent = <&gpio6>;
+               interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+               tcxo-clock-frequency = <26000000>;
+       };
+};
+
 &usdhc3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc3>;
                >;
        };
 
+       pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */
+               fsl,pins = <
+                       MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */
+                       MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
+                       MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10 /* VDOUT_HSYNC */
+                       MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10 /* VDOUT_VSYNC */
+                       MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x10 /* VDOUT_RESET */
+                       MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
+                       MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
+                       MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
+                       MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
+                       MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
+                       MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
+                       MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
+                       MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
+                       MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
+                       MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
+                       MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
+                       MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
+                       MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
+                       MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
+                       MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
+                       MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
+                       MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
+                       MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
+                       MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
+                       MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
+                       MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
+                       MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
+                       MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
+                       MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
+               >;
+       };
+
+       pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_DA1__GPIO3_IO01          0x40013058 /* EN_LCD33V */
+                       MX6QDL_PAD_SD4_DAT5__GPIO2_IO13         0x4001b0b0 /* EN_AVDD */
+                       MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x40013058 /* ENVGH */
+                       MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x40013058 /* ENVGL */
+                       MX6QDL_PAD_EIM_DA6__GPIO3_IO06          0x40013058 /* LCD_POWER */
+                       MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x40013058 /* EN_VCOM_LCD */
+                       MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x40013058 /* LCD_L_R */
+                       MX6QDL_PAD_EIM_DA2__GPIO3_IO02          0x40013058 /* LCD_U_D */
+               >;
+       };
+
+       pinctrl_pwm3: pwm3grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+               >;
+       };
+
        pinctrl_uart3: uart3grp {
                fsl,pins = <
                        MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
                >;
        };
 
+       pinctrl_usbhost: usbhostgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_A23__GPIO6_IO06          0x4001b0b0
+               >;
+       };
+
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17069
+                       MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10079
+                       MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069
+                       MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069
+                       MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069
+                       MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069
+               >;
+       };
+
        pinctrl_usdhc3: usdhc3grp {
                fsl,pins = <
                        MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
                >;
        };
+
+       pinctrl_wlan: wlangrp {
+               fsl,pins = <
+                       MX6QDL_PAD_RGMII_TD1__GPIO6_IO21        0x4001b0b0
+               >;
+       };
 };
index 30ce2c0cec2b4ff524a5a75ed67949a98e42270a..61fa30991d675b7c42f0e2c2e4c038fc800192cf 100644 (file)
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2015 Boundary Devices, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 
index ec53d7a09572f79f77b2cebdf353d966bdceea6b..ef58d3b0ea0d4063002429be6847d146b64f532b 100644 (file)
@@ -1,44 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2013 Boundary Devices, Inc.
  * Copyright 2012 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
index 2e98c92adff748c2724001c0fabb37e66586ebe2..dd3226fe5ecd57e606b6b1eca6090c9634b43837 100644 (file)
                reg = <0x10000000 0x40000000>;
        };
 
-       regulators {
-               compatible = "simple-bus";
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               reg_2p5v: regulator@0 {
-                       compatible = "regulator-fixed";
-                       reg = <0>;
-                       regulator-name = "2P5V";
-                       regulator-min-microvolt = <2500000>;
-                       regulator-max-microvolt = <2500000>;
-               };
-
-               reg_3p3v: regulator@1 {
-                       compatible = "regulator-fixed";
-                       reg = <1>;
-                       regulator-name = "3P3V";
-                       regulator-min-microvolt = <3300000>;
-                       regulator-max-microvolt = <3300000>;
-               };
-
-               reg_usb_otg_vbus: regulator@2 {
-                       compatible = "regulator-fixed";
-                       reg = <2>;
-                       regulator-name = "usb_otg_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       gpio = <&gpio3 22 0>;
-                       enable-active-high;
-               };
+       chosen {
+               stdout-path = "serial1:115200n8";
        };
 
        leds {
                        mux-int-port = <1>;
                        mux-ext-port = <3>;
        };
+
+       reg_2p5v: regulator-2p5v {
+               compatible = "regulator-fixed";
+               regulator-name = "2P5V";
+               regulator-min-microvolt = <2500000>;
+               regulator-max-microvolt = <2500000>;
+       };
+
+       reg_3p3v: regulator-3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "3P3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       reg_usb_otg_vbus: regulator-usbotgvbus {
+               compatible = "regulator-fixed";
+               regulator-name = "usb_otg_vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+       };
 };
 
 &audmux {
index b384913c34ddaf4ed6df751b083abd35d15b454d..f0607eb41df42ae00cb517878c347f50f37b9640 100644 (file)
@@ -33,6 +33,7 @@
                                396000  1175000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
                        clocks = <&clks IMX6QDL_CLK_ARM>,
                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
                                 <&clks IMX6QDL_CLK_STEP>,
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
+                       operating-points = <
+                               /* kHz    uV */
+                               996000  1250000
+                               792000  1175000
+                               396000  1150000
+                       >;
+                       fsl,soc-operating-points = <
+                               /* ARM kHz  SOC-PU uV */
+                               996000  1175000
+                               792000  1175000
+                               396000  1175000
+                       >;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clks IMX6QDL_CLK_ARM>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                <&clks IMX6QDL_CLK_STEP>,
+                                <&clks IMX6QDL_CLK_PLL1_SW>,
+                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                       clock-names = "arm", "pll2_pfd2_396m", "step",
+                                     "pll1_sw", "pll1_sys";
+                       arm-supply = <&reg_arm>;
+                       pu-supply = <&reg_pu>;
+                       soc-supply = <&reg_soc>;
                };
        };
 
index aa0e631f3c0aa07ca1bf7b490a09b2efdf2878a2..707ac9a46115f02bd6307413a1bbd7935a7d7799 100644 (file)
                rtc1 = &snvs_rtc;
        };
 
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                pinctrl-names = "default";
                 */
                compatible = "edt,et057090dhu";
                backlight = <&backlight>;
+               power-supply = <&reg_3v3_sw>;
 
                port {
                        lcd_panel_in: endpoint {
                enable-active-high;
                status = "okay";
        };
+
+       reg_3v3_sw: regulator-3v3-sw {
+               compatible = "regulator-fixed";
+               regulator-name = "3.3V_SW";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
 };
 
 &backlight {
        brightness-levels = <0 127 191 223 239 247 251 255>;
        default-brightness-level = <1>;
+       power-supply = <&reg_3v3_sw>;
        status = "okay";
 };
 
 &can1 {
+       xceiver-supply = <&reg_3v3_sw>;
        status = "okay";
 };
 
 &can2 {
+       xceiver-supply = <&reg_3v3_sw>;
        status = "okay";
 };
 
index e8dccf5521224629bc8451557cd5be111d0d464c..4e1c8feaef82207805d102d0aa724db06ae4e39e 100644 (file)
                rtc1 = &snvs_rtc;
        };
 
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                pinctrl-names = "default";
index 6831dfd24cc1db89f873f63e4f99c196f6e60334..469e3d0e28276e78c26a000ae3f9cda004706bd1 100644 (file)
                rtc1 = &snvs_rtc;
        };
 
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
                pinctrl-names = "default";
index 65ef4cacbc7152497cf5a04c07609ce4ff39e1e2..18ae4f3be6e38f93a9421ca4152e7a11bf43ad23 100644 (file)
        >;
 };
 
+&cpu1 {
+       /*
+        * Although the imx6q fuse indicates that 1.2GHz operation is possible,
+        * the module behaves unstable at this frequency. Hence, remove the
+        * 1.2GHz operation point here.
+        */
+       operating-points = <
+               /* kHz  uV */
+               996000  1250000
+               852000  1250000
+               792000  1175000
+               396000  975000
+       >;
+       fsl,soc-operating-points = <
+               /* ARM kHz      SOC-PU uV */
+               996000          1250000
+               852000          1250000
+               792000          1175000
+               396000          1175000
+       >;
+};
+
+&cpu2 {
+       /*
+        * Although the imx6q fuse indicates that 1.2GHz operation is possible,
+        * the module behaves unstable at this frequency. Hence, remove the
+        * 1.2GHz operation point here.
+        */
+       operating-points = <
+               /* kHz  uV */
+               996000  1250000
+               852000  1250000
+               792000  1175000
+               396000  975000
+       >;
+       fsl,soc-operating-points = <
+               /* ARM kHz      SOC-PU uV */
+               996000          1250000
+               852000          1250000
+               792000          1175000
+               396000          1175000
+       >;
+};
+
+&cpu3 {
+       /*
+        * Although the imx6q fuse indicates that 1.2GHz operation is possible,
+        * the module behaves unstable at this frequency. Hence, remove the
+        * 1.2GHz operation point here.
+        */
+       operating-points = <
+               /* kHz  uV */
+               996000  1250000
+               852000  1250000
+               792000  1175000
+               396000  975000
+       >;
+       fsl,soc-operating-points = <
+               /* ARM kHz      SOC-PU uV */
+               996000          1250000
+               852000          1250000
+               792000          1175000
+               396000          1175000
+       >;
+};
+
 &ecspi1 {
        cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
        pinctrl-names = "default";
index acd3d33476d42e4e332ec7d6a5c21ab9d6ee867f..95b2efda17b42ebb6cb0203a941c8ebd3b4be8b7 100644 (file)
        status = "okay";
 };
 
+&mipi_csi {
+       status = "okay";
+};
+
+&ov5640 {
+       status = "okay";
+};
+
 &usdhc3 {
        status = "okay";
 };
index 2a3c44f98eed8fc415290be719a616c6e12450d5..03bec0c53063733b4313e7b19498f8c340ea5aa1 100644 (file)
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2015 Boundary Devices, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 
index c5d59baa1a07e17ba22bdc884de8391a11289807..eb4eecb6ed22167daa4075af326d38cbe68e8638 100644 (file)
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2016 Boundary Devices, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 /dts-v1/;
 
index df8ff397a91421374a51eb5a479b3540f5ca8330..435445a34ad026c0ae623b32d14b29348c352f63 100644 (file)
@@ -1,44 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2013 Boundary Devices, Inc.
  * Copyright 2012 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
index f2368a073d07ecd73430dd3870d75291dfe73c3b..c54362fcc508118421c505ea67ccad8449f40e7d 100644 (file)
                touchscreen-size-y = <480>;
                touchscreen-inverted-x;
                touchscreen-inverted-y;
+               wakeup-source;
        };
 
        rtc@68 {
index 77f8f030dd0772aba631f57b704a7e60a9bd0532..0193ee6fe964a4be2a12e1b56374272293f16d2c 100644 (file)
@@ -38,6 +38,7 @@
                                396000  1175000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
                        clocks = <&clks IMX6QDL_CLK_ARM>,
                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
                                 <&clks IMX6QDL_CLK_STEP>,
                        soc-supply = <&reg_soc>;
                };
 
-               cpu@1 {
+               cpu1: cpu@1 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
+                       operating-points = <
+                               /* kHz    uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  975000
+                       >;
+                       fsl,soc-operating-points = <
+                               /* ARM kHz  SOC-PU uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  1175000
+                       >;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clks IMX6QDL_CLK_ARM>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                <&clks IMX6QDL_CLK_STEP>,
+                                <&clks IMX6QDL_CLK_PLL1_SW>,
+                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                       clock-names = "arm", "pll2_pfd2_396m", "step",
+                                     "pll1_sw", "pll1_sys";
+                       arm-supply = <&reg_arm>;
+                       pu-supply = <&reg_pu>;
+                       soc-supply = <&reg_soc>;
                };
 
-               cpu@2 {
+               cpu2: cpu@2 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <2>;
                        next-level-cache = <&L2>;
+                       operating-points = <
+                               /* kHz    uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  975000
+                       >;
+                       fsl,soc-operating-points = <
+                               /* ARM kHz  SOC-PU uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  1175000
+                       >;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clks IMX6QDL_CLK_ARM>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                <&clks IMX6QDL_CLK_STEP>,
+                                <&clks IMX6QDL_CLK_PLL1_SW>,
+                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                       clock-names = "arm", "pll2_pfd2_396m", "step",
+                                     "pll1_sw", "pll1_sys";
+                       arm-supply = <&reg_arm>;
+                       pu-supply = <&reg_pu>;
+                       soc-supply = <&reg_soc>;
                };
 
-               cpu@3 {
+               cpu3: cpu@3 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <3>;
                        next-level-cache = <&L2>;
+                       operating-points = <
+                               /* kHz    uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  975000
+                       >;
+                       fsl,soc-operating-points = <
+                               /* ARM kHz  SOC-PU uV */
+                               1200000 1275000
+                               996000  1250000
+                               852000  1250000
+                               792000  1175000
+                               396000  1175000
+                       >;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clks IMX6QDL_CLK_ARM>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                <&clks IMX6QDL_CLK_STEP>,
+                                <&clks IMX6QDL_CLK_PLL1_SW>,
+                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                       clock-names = "arm", "pll2_pfd2_396m", "step",
+                                     "pll1_sw", "pll1_sys";
+                       arm-supply = <&reg_arm>;
+                       pu-supply = <&reg_pu>;
+                       soc-supply = <&reg_soc>;
                };
        };
 
index 64fbee61de4492d733d236e0cc6cf667e6a1cee1..05f07ea3e8c8051338dfec9db3977e095ae19431 100644 (file)
                status = "disabled";
        };
 
-       reg_1p8v: regulator-1p8v {
+       reg_module_3v3: regulator-module-3v3 {
                compatible = "regulator-fixed";
-               regulator-name = "1P8V";
-               regulator-min-microvolt = <1800000>;
-               regulator-max-microvolt = <1800000>;
-               regulator-always-on;
-       };
-
-       reg_2p5v: regulator-2p5v {
-               compatible = "regulator-fixed";
-               regulator-name = "2P5V";
-               regulator-min-microvolt = <2500000>;
-               regulator-max-microvolt = <2500000>;
+               regulator-name = "+V3.3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
                regulator-always-on;
        };
 
-       reg_3p3v: regulator-3p3v {
+       reg_module_3v3_audio: regulator-module-3v3-audio {
                compatible = "regulator-fixed";
-               regulator-name = "3P3V";
+               regulator-name = "+V3.3_AUDIO";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
                regulator-always-on;
 
                        vgen4_reg: vgen4 {
                                regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
+                               regulator-max-microvolt = <1800000>;
                                regulator-boot-on;
                                regulator-always-on;
                        };
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
                clocks = <&clks IMX6QDL_CLK_CKO>;
-               VDDA-supply = <&reg_2p5v>;
-               VDDIO-supply = <&reg_3p3v>;
+               VDDA-supply = <&reg_module_3v3_audio>;
+               VDDIO-supply = <&reg_module_3v3>;
+               VDDD-supply = <&vgen4_reg>;
        };
 
        /* STMPE811 touch screen controller */
 &usdhc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
-       vqmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_module_3v3>;
        bus-width = <8>;
-       voltage-ranges = <3300 3300>;
+       disable-wp;
+       no-1-8-v;
        status = "disabled";
 };
 
 &usdhc2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc2>;
-       vqmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_module_3v3>;
        bus-width = <4>;
-       voltage-ranges = <3300 3300>;
+       disable-wp;
+       no-1-8-v;
        status = "disabled";
 };
 
 &usdhc3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc3>;
-       vqmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_module_3v3>;
        bus-width = <8>;
-       voltage-ranges = <3300 3300>;
+       no-1-8-v;
        non-removable;
        status = "okay";
 };
                        MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059
                >;
        };
-
-       pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
-               fsl,pins = <
-                       MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170b9
-                       MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100b9
-                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
-                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
-                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
-                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
-                       MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
-                       MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
-                       MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
-                       MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
-                       /* eMMC reset */
-                       MX6QDL_PAD_SD3_RST__SD3_RESET  0x170b9
-               >;
-       };
-
-       pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
-               fsl,pins = <
-                       MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170f9
-                       MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100f9
-                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
-                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
-                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
-                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
-                       MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
-                       MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
-                       MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
-                       MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
-                       /* eMMC reset */
-                       MX6QDL_PAD_SD3_RST__SD3_RESET  0x170f9
-               >;
-       };
 };
index 76035db96f67831bc576cbea7f50f4b6ffe6d5b4..87e15e7cb32b1e7ea3305faf0d233f129d8eb0b0 100644 (file)
                status = "disabled";
        };
 
-       reg_1p8v: regulator-1p8v {
+       reg_module_3v3: regulator-module-3v3 {
                compatible = "regulator-fixed";
-               regulator-name = "1P8V";
-               regulator-min-microvolt = <1800000>;
-               regulator-max-microvolt = <1800000>;
-               regulator-always-on;
-       };
-
-       reg_2p5v: regulator-2p5v {
-               compatible = "regulator-fixed";
-               regulator-name = "2P5V";
-               regulator-min-microvolt = <2500000>;
-               regulator-max-microvolt = <2500000>;
+               regulator-name = "+V3.3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
                regulator-always-on;
        };
 
-       reg_3p3v: regulator-3p3v {
+       reg_module_3v3_audio: regulator-module-3v3-audio {
                compatible = "regulator-fixed";
-               regulator-name = "3P3V";
+               regulator-name = "+V3.3_AUDIO";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
                regulator-always-on;
 
                        vgen4_reg: vgen4 {
                                regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
+                               regulator-max-microvolt = <1800000>;
                                regulator-boot-on;
                                regulator-always-on;
                        };
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
                clocks = <&clks IMX6QDL_CLK_CKO>;
-               VDDA-supply = <&reg_2p5v>;
-               VDDIO-supply = <&reg_3p3v>;
+               VDDA-supply = <&reg_module_3v3_audio>;
+               VDDIO-supply = <&reg_module_3v3>;
+               VDDD-supply = <&vgen4_reg>;
                lrclk-strength = <3>;
        };
 
 /* Colibri MMC */
 &usdhc1 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usdhc1>;
-       vqmmc-supply = <&reg_3p3v>;
+       pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
+       cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
+       disable-wp;
+       vqmmc-supply = <&reg_module_3v3>;
        bus-width = <4>;
-       voltage-ranges = <3300 3300>;
+       no-1-8-v;
        status = "disabled";
 };
 
 &usdhc3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc3>;
-       vqmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_module_3v3>;
        bus-width = <8>;
-       voltage-ranges = <3300 3300>;
+       no-1-8-v;
        non-removable;
        status = "okay";
 };
 
        pinctrl_gpio_keys: gpiokeys {
                fsl,pins = <
-                       /* Power button */
-                       MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0
+                       MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x130b0
                >;
        };
 
 
        pinctrl_mmc_cd: gpiommccd {
                fsl,pins = <
-                       MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000
+                       MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
                >;
        };
 
                >;
        };
 
-       pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
-               fsl,pins = <
-                       MX6QDL_PAD_SD3_CMD__SD3_CMD     0x170b9
-                       MX6QDL_PAD_SD3_CLK__SD3_CLK     0x100b9
-                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x170b9
-                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x170b9
-                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x170b9
-                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x170b9
-                       MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x170b9
-                       MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x170b9
-                       MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x170b9
-                       MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x170b9
-                       /* eMMC reset */
-                       MX6QDL_PAD_SD3_RST__SD3_RESET   0x170b9
-               >;
-       };
-
-       pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
-               fsl,pins = <
-                       MX6QDL_PAD_SD3_CMD__SD3_CMD     0x170f9
-                       MX6QDL_PAD_SD3_CLK__SD3_CLK     0x100f9
-                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x170f9
-                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x170f9
-                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x170f9
-                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x170f9
-                       MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x170f9
-                       MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x170f9
-                       MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x170f9
-                       MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x170f9
-                       /* eMMC reset */
-                       MX6QDL_PAD_SD3_RST__SD3_RESET   0x170f9
-               >;
-       };
-
        pinctrl_weim_cs0: weimcs0grp {
                fsl,pins = <
                        /* nEXT_CS0 */
index 0a1574998fc6a89a423b706f143c4376e75c337c..9ce993776160df74623b6e20e568b4945bc85eaf 100644 (file)
@@ -65,8 +65,7 @@
                regulator-always-on;
        };
 
-
-       reg_2p5v: regulator-3p3v {
+       reg_2p5v: regulator-2p5v {
                compatible = "regulator-fixed";
                regulator-name = "2P5V";
                regulator-min-microvolt = <2500000>;
        pinctrl-0 = <&pinctrl_i2c3>;
        status = "okay";
 
+       ov5640: camera@3c {
+               compatible = "ovti,ov5640";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_ov5640>;
+               reg = <0x3c>;
+               clocks = <&clks IMX6QDL_CLK_CKO>;
+               clock-names = "xclk";
+               DOVDD-supply = <&reg_1p8v>;
+               AVDD-supply = <&reg_3p3v>;
+               DVDD-supply = <&reg_3p3v>;
+               powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
+               reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
+               status = "disabled";
+
+               port {
+                       ov5640_to_mipi_csi2: endpoint {
+                               remote-endpoint = <&mipi_csi2_in>;
+                               clock-lanes = <0>;
+                               data-lanes = <1 2>;
+                       };
+               };
+       };
+
        sgtl5000: codec@a {
                #sound-dai-cells = <0>;
                compatible = "fsl,sgtl5000";
        };
 };
 
+&mipi_csi {
+       status = "disabled";
+
+       port@0 {
+               reg = <0>;
+
+               mipi_csi2_in: endpoint {
+                       remote-endpoint = <&ov5640_to_mipi_csi2>;
+                       clock-lanes = <0>;
+                       data-lanes = <1 2>;
+               };
+       };
+};
+
 &pwm3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm3>;
                fsl,pins = <
                        MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
                        MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
-                       MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
+               >;
+       };
+
+       pinctrl_ov5640: ov5640grp {
+               fsl,pins = <
+                       MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0
+                       MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
+                       MX6QDL_PAD_GPIO_0__CCM_CLKO1      0x130b0
                >;
        };
 
index aab088f318e8d202537b6ee566dcb6cf46b4b88f..29baf25ae5d04cab3fb123529a3389ea05b5099d 100644 (file)
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2015 Boundary Devices, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
                reg = <0x38>;
                interrupt-parent = <&gpio1>;
                interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+               wakeup-source;
        };
 
        rtc@6f {
index 87ca6ead4098052ae1044c223e23284c25dc3677..39200e5dc896568978172c8d3075139b375546a2 100644 (file)
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2015 Boundary Devices, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
                reg = <0x38>;
                interrupt-parent = <&gpio1>;
                interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+               wakeup-source;
        };
 };
 
index f5b763d392853dc0d59b09b940012032754ab918..572abd7499b174ae431b7f788b85c7c35eeb536b 100644 (file)
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2016 Boundary Devices, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
                reg = <0x38>;
                interrupt-parent = <&gpio1>;
                interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+               wakeup-source;
        };
 };
 
index 596866b0a0d2ceebc010beb4d1104e2832f5f63f..98384a6c5d1295eadd103eabd0ca8f9ce7c4da26 100644 (file)
@@ -1,44 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2013 Boundary Devices, Inc.
  * Copyright 2011 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
                reg = <0x38>;
                interrupt-parent = <&gpio1>;
                interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+               wakeup-source;
        };
 };
 
index 0e28e36ddbb2d2431c8c815a0bdd6c4ac116481f..9f11f1fcc3e6caac35c38c5b81038b3a1a152078 100644 (file)
@@ -6,6 +6,10 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
+       chosen {
+               stdout-path = &uart4;
+       };
+
        memory@10000000 {
                reg = <0x10000000 0x80000000>;
        };
                                gpio-controller;
                                #gpio-cells = <2>;
                        };
+
+                       light-sensor@44 {
+                               compatible = "isil,isl29023";
+                               reg = <0x44>;
+                               interrupt-parent = <&gpio5>;
+                               interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+                       };
+
+                       magnetometer@e {
+                               compatible = "fsl,mag3110";
+                               reg = <0x0e>;
+                               interrupt-parent = <&gpio2>;
+                               interrupts = <29 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       accelerometer@1c {
+                               compatible = "fsl,mma8451";
+                               reg = <0x1c>;
+                               interrupt-parent = <&gpio6>;
+                               interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+                       };
                };
        };
 };
index 15744ad52535cae0ebec5fba5f14bdab52e87136..6e46a195b3997f86800462746299f7c7d9924a25 100644 (file)
                        sw4_reg: sw4 {
                                regulator-min-microvolt = <800000>;
                                regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
                        };
 
                        swbst_reg: swbst {
index e1afa54404d0f2afa473045acc9b0b3898501bd3..381bf61fcd284ad3c7052e799f9051901af0c6d8 100644 (file)
@@ -8,30 +8,6 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-       regulators {
-               compatible = "simple-bus";
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               reg_2p5v: regulator@0 {
-                       compatible = "regulator-fixed";
-                       reg = <0>;
-                       regulator-name = "2P5V";
-                       regulator-min-microvolt = <2500000>;
-                       regulator-max-microvolt = <2500000>;
-                       regulator-always-on;
-               };
-
-               reg_3p3v: regulator@1 {
-                       compatible = "regulator-fixed";
-                       reg = <1>;
-                       regulator-name = "3P3V";
-                       regulator-min-microvolt = <3300000>;
-                       regulator-max-microvolt = <3300000>;
-                       regulator-always-on;
-               };
-       };
-
        sound {
                compatible = "fsl,imx6-wandboard-sgtl5000",
                             "fsl,imx-audio-sgtl5000";
                spdif-controller = <&spdif>;
                spdif-out;
        };
+
+       reg_2p5v: regulator-2p5v {
+               compatible = "regulator-fixed";
+               regulator-name = "2P5V";
+               regulator-min-microvolt = <2500000>;
+               regulator-max-microvolt = <2500000>;
+               regulator-always-on;
+       };
+
+       reg_3p3v: regulator-3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "3P3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+       };
+
+       reg_usb_otg_vbus: regulator-usbotgvbus {
+               compatible = "regulator-fixed";
+               regulator-name = "usb_otg_vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usbotgvbus>;
+               gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+       };
 };
 
 &audmux {
                        >;
                };
 
+               pinctrl_usbotgvbus: usbotgvbusgrp {
+                       fsl,pins = <
+                               MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x130b0
+                       >;
+               };
+
                pinctrl_usdhc1: usdhc1grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD1_CMD__SD1_CMD             0x17059
 };
 
 &usbotg {
+       vbus-supply = <&reg_usb_otg_vbus>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usbotg>;
        disable-over-current;
-       dr_mode = "peripheral";
+       dr_mode = "otg";
        status = "okay";
 };
 
index 19a075aee19eabfb5ac2b127db45199bca2f0d6a..87c60a853f8bc62aa879d759b9bf3df9c34cee08 100644 (file)
        rave-sp {
                compatible = "zii,rave-sp-rdu2";
                current-speed = <1000000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
 
                watchdog {
                        compatible = "zii,rave-sp-watchdog";
                };
+
+               backlight {
+                       compatible = "zii,rave-sp-backlight";
+               };
+
+               pwrbutton {
+                       compatible = "zii,rave-sp-pwrbutton";
+               };
+
+               eeprom@a3 {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xa3 0x4000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       zii,eeprom-name = "dds-eeprom";
+               };
+
+               eeprom@a4 {
+                       compatible = "zii,rave-sp-eeprom";
+                       reg = <0xa4 0x4000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       zii,eeprom-name = "main-eeprom";
+               };
        };
 };
 
 
                rmi4-f11@11 {
                        reg = <0x11>;
-                       touchscreen-inverted-y;
+                       touchscreen-inverted-x;
                        touchscreen-swapped-x-y;
                        syna,sensor-type = <1>;
                };
 
                rmi4-f12@12 {
                        reg = <0x12>;
-                       touchscreen-inverted-y;
+                       touchscreen-inverted-x;
                        touchscreen-swapped-x-y;
                        syna,sensor-type = <1>;
                };
index 911141e246810fe654db3d44dd147afca7122569..61d2d26afbf4d90474dcae54930bb036ba13412b 100644 (file)
 
                        crypto: caam@2100000 {
                                compatible = "fsl,sec-v4.0";
-                               fsl,sec-era = <4>;
                                #address-cells = <1>;
                                #size-cells = <1>;
                                reg = <0x2100000 0x10000>;
index a39b8603658189bf2369066427bfd11ca0bea7cc..741d1ed338ca24b0e3c95e6882cb7482903ce8b3 100644 (file)
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2016 Boundary Devices, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
index 011726c836cdae683bc94ebd27c724873e73cf64..1593ac86b2a4c52f48c480b9984a3543810c9194 100644 (file)
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright 2017 Boundary Devices, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
index 92ad01f676e345f4f7e97f602026c50135c97039..679b4482ab13aca4bcaa0506f73b3c3a04233134 100644 (file)
        model = "Freescale i.MX6 SoloLite EVK Board";
        compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
 
+       chosen {
+               stdout-path = &uart1;
+       };
+
        memory@80000000 {
                reg = <0x80000000 0x40000000>;
        };
@@ -73,6 +77,8 @@
 
        reg_lcd_3v3: regulator-lcd-3v3 {
                compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
                regulator-name = "lcd-3v3";
                gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
                enable-active-high;
                        sw4_reg: sw4 {
                                regulator-min-microvolt = <800000>;
                                regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
                        };
 
                        swbst_reg: swbst {
                        >;
                };
 
+               pinctrl_reg_lcd_3v3: reglcd3v3grp {
+                       fsl,pins = <
+                               MX6SL_PAD_KEY_ROW5__GPIO4_IO03    0x17059
+                       >;
+               };
+
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
                                MX6SL_PAD_UART1_RXD__UART1_RX_DATA      0x1b0b1
index 994e48dc1df0a01e1be33c2bc8750e453b83ddb4..7a4f5dace9026b0075507f46107c95bba1ab6397 100644 (file)
@@ -60,6 +60,7 @@
                                396000          1175000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
                        clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
                                        <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
                                        <&clks IMX6SL_CLK_PLL1_SYS>;
                                regulator-1p1 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd1p1";
-                                       regulator-min-microvolt = <800000>;
-                                       regulator-max-microvolt = <1375000>;
+                                       regulator-min-microvolt = <1000000>;
+                                       regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                        anatop-reg-offset = <0x110>;
                                        anatop-vol-bit-shift = <8>;
                                regulator-2p5 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd2p5";
-                                       regulator-min-microvolt = <2100000>;
-                                       regulator-max-microvolt = <2850000>;
+                                       regulator-min-microvolt = <2250000>;
+                                       regulator-max-microvolt = <2750000>;
                                        regulator-always-on;
                                        anatop-reg-offset = <0x130>;
                                        anatop-vol-bit-shift = <8>;
                                #interrupt-cells = <3>;
                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-parent = <&intc>;
-                               pu-supply = <&reg_pu>;
-                               clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
-                                        <&clks IMX6SL_CLK_GPU2D_PODF>;
-                               #power-domain-cells = <1>;
+                               clocks = <&clks IMX6SL_CLK_IPG>;
+                               clock-names = "ipg";
+
+                               pgc {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       power-domain@0 {
+                                               reg = <0>;
+                                               #power-domain-cells = <0>;
+                                       };
+
+                                       pd_pu: power-domain@1 {
+                                               reg = <1>;
+                                               #power-domain-cells = <0>;
+                                               power-supply = <&reg_pu>;
+                                               clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
+                                                        <&clks IMX6SL_CLK_GPU2D_PODF>;
+                                       };
+
+                                       pd_disp: power-domain@2 {
+                                               reg = <2>;
+                                               #power-domain-cells = <0>;
+                                               clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
+                                                        <&clks IMX6SL_CLK_LCDIF_PIX>,
+                                                        <&clks IMX6SL_CLK_EPDC_AXI>,
+                                                        <&clks IMX6SL_CLK_EPDC_PIX>,
+                                                        <&clks IMX6SL_CLK_PXP_AXI>;
+                                       };
+                               };
                        };
 
                        gpr: iomuxc-gpr@20e0000 {
                                         <&clks IMX6SL_CLK_DUMMY>;
                                clock-names = "pix", "axi", "disp_axi";
                                status = "disabled";
+                               power-domains = <&pd_disp>;
                        };
 
                        dcp: dcp@20fc000 {
                                status = "disabled";
                        };
                };
+
+               gpu_2d: gpu@2200000 {
+                       compatible = "vivante,gc";
+                       reg = <0x02200000 0x4000>;
+                       interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
+                                <&clks IMX6SL_CLK_GPU2D_OVG>;
+                       clock-names = "bus", "core";
+                       power-domains = <&pd_pu>;
+               };
+
+               gpu_vg: gpu@2204000 {
+                       compatible = "vivante,gc";
+                       reg = <0x02204000 0x4000>;
+                       interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
+                                <&clks IMX6SL_CLK_GPU2D_OVG>;
+                       clock-names = "bus", "core";
+                       power-domains = <&pd_pu>;
+               };
        };
 };
diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts
new file mode 100644 (file)
index 0000000..c8e1155
--- /dev/null
@@ -0,0 +1,463 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sll.dtsi"
+
+/ {
+       model = "Freescale i.MX6SLL EVK Board";
+       compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
+       chosen {
+               stdout-path = &uart1;
+       };
+
+       memory@80000000 {
+               reg = <0x80000000 0x80000000>;
+       };
+
+       backlight_display: backlight-display {
+               compatible = "pwm-backlight";
+               pwms = <&pwm1 0 5000000>;
+               brightness-levels = <0 4 8 16 32 64 128 255>;
+               default-brightness-level = <6>;
+               status = "okay";
+       };
+
+       reg_usb_otg1_vbus: regulator-otg1-vbus {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
+               regulator-name = "usb_otg1_vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_usb_otg2_vbus: regulator-otg2-vbus {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usb_otg2_vbus>;
+               regulator-name = "usb_otg2_vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_aud3v: regulator-aud3v {
+               compatible = "regulator-fixed";
+               regulator-name = "wm8962-supply-3v15";
+               regulator-min-microvolt = <3150000>;
+               regulator-max-microvolt = <3150000>;
+               regulator-boot-on;
+       };
+
+       reg_aud4v: regulator-aud4v {
+               compatible = "regulator-fixed";
+               regulator-name = "wm8962-supply-4v2";
+               regulator-min-microvolt = <4325000>;
+               regulator-max-microvolt = <4325000>;
+               regulator-boot-on;
+       };
+
+       reg_lcd_3v3: regulator-lcd-3v3 {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
+               regulator-name = "lcd-3v3";
+               gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_lcd_5v: regulator-lcd-5v {
+               compatible = "regulator-fixed";
+               regulator-name = "lcd-5v0";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+       };
+
+       reg_sd1_vmmc: regulator-sd1-vmmc {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_sd1_vmmc>;
+               regulator-name = "SD1_SPWR";
+               regulator-min-microvolt = <3000000>;
+               regulator-max-microvolt = <3000000>;
+               gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_sd3_vmmc: regulator-sd3-vmmc {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_sd3_vmmc>;
+               regulator-name = "SD3_WIFI";
+               regulator-min-microvolt = <3000000>;
+               regulator-max-microvolt = <3000000>;
+               gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       panel {
+               compatible = "sii,43wvf1g";
+               backlight = <&backlight_display>;
+               dvdd-supply = <&reg_lcd_3v3>;
+               avdd-supply = <&reg_lcd_5v>;
+
+               port {
+                       panel_in: endpoint {
+                               remote-endpoint = <&display_out>;
+                       };
+               };
+       };
+};
+
+&cpu0 {
+       arm-supply = <&sw1a_reg>;
+       soc-supply = <&sw1c_reg>;
+};
+
+&i2c1 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       pfuze100: pmic@8 {
+               compatible = "fsl,pfuze100";
+               reg = <0x08>;
+
+               regulators {
+                       sw1a_reg: sw1ab {
+                               regulator-min-microvolt = <300000>;
+                               regulator-max-microvolt = <1875000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <6250>;
+                       };
+
+                       sw1c_reg: sw1c {
+                               regulator-min-microvolt = <300000>;
+                               regulator-max-microvolt = <1875000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <6250>;
+                       };
+
+                       sw2_reg: sw2 {
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw3a_reg: sw3a {
+                               regulator-min-microvolt = <400000>;
+                               regulator-max-microvolt = <1975000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw3b_reg: sw3b {
+                               regulator-min-microvolt = <400000>;
+                               regulator-max-microvolt = <1975000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw4_reg: sw4 {
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       swbst_reg: swbst {
+                               regulator-min-microvolt = <5000000>;
+                               regulator-max-microvolt = <5150000>;
+                       };
+
+                       snvs_reg: vsnvs {
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <3000000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vref_reg: vrefddr {
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vgen1_reg: vgen1 {
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1550000>;
+                               regulator-always-on;
+                       };
+
+                       vgen2_reg: vgen2 {
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1550000>;
+                       };
+
+                       vgen3_reg: vgen3 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                       };
+
+                       vgen4_reg: vgen4 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen5_reg: vgen5 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen6_reg: vgen6 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+               };
+       };
+};
+
+&lcdif {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lcd>;
+       status = "okay";
+
+       port {
+               display_out: endpoint {
+                       remote-endpoint = <&panel_in>;
+               };
+       };
+};
+
+&pwm1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm1>;
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       status = "okay";
+};
+
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+       cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+       keep-power-in-suspend;
+       wakeup-source;
+       vmmc-supply = <&reg_sd1_vmmc>;
+       status = "okay";
+};
+
+&usbotg1 {
+       vbus-supply = <&reg_usb_otg1_vbus>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usbotg1>;
+       disable-over-current;
+       srp-disable;
+       hnp-disable;
+       adp-disable;
+       status = "okay";
+};
+
+&usbotg2 {
+       vbus-supply = <&reg_usb_otg2_vbus>;
+       dr_mode = "host";
+       disable-over-current;
+       status = "okay";
+};
+
+&usdhc3 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+       keep-power-in-suspend;
+       enable-sdio-wakeup;
+       vmmc-supply = <&reg_sd3_vmmc>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_reg_sd3_vmmc: sd3vmmcgrp {
+               fsl,pins = <
+                       MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059
+               >;
+       };
+
+       pinctrl_usb_otg1_vbus: vbus1grp {
+               fsl,pins = <
+                       MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
+               >;
+       };
+
+       pinctrl_usb_otg2_vbus: vbus2grp {
+               fsl,pins = <
+                       MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
+               >;
+       };
+
+       pinctrl_reg_lcd_3v3: reglcd3v3grp {
+               fsl,pins = <
+                       MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059
+               >;
+       };
+
+       pinctrl_reg_sd1_vmmc: sd1vmmcgrp {
+               fsl,pins = <
+                       MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
+               >;
+       };
+
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+                       MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+               >;
+       };
+
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX6SLL_PAD_SD1_CMD__SD1_CMD     0x17059
+                       MX6SLL_PAD_SD1_CLK__SD1_CLK     0x13059
+                       MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
+                       MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
+                       MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
+                       MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
+               >;
+       };
+
+       pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+               fsl,pins = <
+                       MX6SLL_PAD_SD1_CMD__SD1_CMD     0x170b9
+                       MX6SLL_PAD_SD1_CLK__SD1_CLK     0x130b9
+                       MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
+                       MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
+                       MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
+                       MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
+               >;
+       };
+
+       pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+               fsl,pins = <
+                       MX6SLL_PAD_SD1_CMD__SD1_CMD     0x170f9
+                       MX6SLL_PAD_SD1_CLK__SD1_CLK     0x130f9
+                       MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
+                       MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
+                       MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
+                       MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
+               >;
+       };
+
+       pinctrl_usbotg1: usbotg1grp {
+               fsl,pins = <
+                       MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+               >;
+       };
+
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX6SLL_PAD_SD3_CMD__SD3_CMD             0x17061
+                       MX6SLL_PAD_SD3_CLK__SD3_CLK             0x13061
+                       MX6SLL_PAD_SD3_DATA0__SD3_DATA0         0x17061
+                       MX6SLL_PAD_SD3_DATA1__SD3_DATA1         0x17061
+                       MX6SLL_PAD_SD3_DATA2__SD3_DATA2         0x17061
+                       MX6SLL_PAD_SD3_DATA3__SD3_DATA3         0x17061
+                       MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22      0x17059
+               >;
+       };
+
+       pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+               fsl,pins = <
+                       MX6SLL_PAD_SD3_CMD__SD3_CMD             0x170a1
+                       MX6SLL_PAD_SD3_CLK__SD3_CLK             0x130a1
+                       MX6SLL_PAD_SD3_DATA0__SD3_DATA0         0x170a1
+                       MX6SLL_PAD_SD3_DATA1__SD3_DATA1         0x170a1
+                       MX6SLL_PAD_SD3_DATA2__SD3_DATA2         0x170a1
+                       MX6SLL_PAD_SD3_DATA3__SD3_DATA3         0x170a1
+                       MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22      0x17059
+               >;
+       };
+
+       pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+               fsl,pins = <
+                       MX6SLL_PAD_SD3_CMD__SD3_CMD             0x170e9
+                       MX6SLL_PAD_SD3_CLK__SD3_CLK             0x130f9
+                       MX6SLL_PAD_SD3_DATA0__SD3_DATA0         0x170e9
+                       MX6SLL_PAD_SD3_DATA1__SD3_DATA1         0x170e9
+                       MX6SLL_PAD_SD3_DATA2__SD3_DATA2         0x170e9
+                       MX6SLL_PAD_SD3_DATA3__SD3_DATA3         0x170e9
+                       MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22      0x17059
+               >;
+       };
+
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX6SLL_PAD_I2C1_SCL__I2C1_SCL    0x4001b8b1
+                       MX6SLL_PAD_I2C1_SDA__I2C1_SDA    0x4001b8b1
+               >;
+       };
+
+       pinctrl_lcd: lcdgrp {
+               fsl,pins = <
+                       MX6SLL_PAD_LCD_DATA00__LCD_DATA00       0x79
+                       MX6SLL_PAD_LCD_DATA01__LCD_DATA01       0x79
+                       MX6SLL_PAD_LCD_DATA02__LCD_DATA02       0x79
+                       MX6SLL_PAD_LCD_DATA03__LCD_DATA03       0x79
+                       MX6SLL_PAD_LCD_DATA04__LCD_DATA04       0x79
+                       MX6SLL_PAD_LCD_DATA05__LCD_DATA05       0x79
+                       MX6SLL_PAD_LCD_DATA06__LCD_DATA06       0x79
+                       MX6SLL_PAD_LCD_DATA07__LCD_DATA07       0x79
+                       MX6SLL_PAD_LCD_DATA08__LCD_DATA08       0x79
+                       MX6SLL_PAD_LCD_DATA09__LCD_DATA09       0x79
+                       MX6SLL_PAD_LCD_DATA10__LCD_DATA10       0x79
+                       MX6SLL_PAD_LCD_DATA11__LCD_DATA11       0x79
+                       MX6SLL_PAD_LCD_DATA12__LCD_DATA12       0x79
+                       MX6SLL_PAD_LCD_DATA13__LCD_DATA13       0x79
+                       MX6SLL_PAD_LCD_DATA14__LCD_DATA14       0x79
+                       MX6SLL_PAD_LCD_DATA15__LCD_DATA15       0x79
+                       MX6SLL_PAD_LCD_DATA16__LCD_DATA16       0x79
+                       MX6SLL_PAD_LCD_DATA17__LCD_DATA17       0x79
+                       MX6SLL_PAD_LCD_DATA18__LCD_DATA18       0x79
+                       MX6SLL_PAD_LCD_DATA19__LCD_DATA19       0x79
+                       MX6SLL_PAD_LCD_DATA20__LCD_DATA20       0x79
+                       MX6SLL_PAD_LCD_DATA21__LCD_DATA21       0x79
+                       MX6SLL_PAD_LCD_DATA22__LCD_DATA22       0x79
+                       MX6SLL_PAD_LCD_DATA23__LCD_DATA23       0x79
+                       MX6SLL_PAD_LCD_CLK__LCD_CLK             0x79
+                       MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE       0x79
+                       MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC         0x79
+                       MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC         0x79
+                       MX6SLL_PAD_LCD_RESET__LCD_RESET         0x79
+               >;
+       };
+
+       pinctrl_pwm1: pmw1grp {
+               fsl,pins = <
+                       MX6SLL_PAD_PWM1__PWM1_OUT   0x110b0
+               >;
+       };
+};
diff --git a/arch/arm/boot/dts/imx6sll-pinfunc.h b/arch/arm/boot/dts/imx6sll-pinfunc.h
new file mode 100644 (file)
index 0000000..713a346
--- /dev/null
@@ -0,0 +1,880 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
+ *
+ */
+
+#ifndef __DTS_IMX6SLL_PINFUNC_H
+#define __DTS_IMX6SLL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6SLL_PAD_WDOG_B__WDOG1_B                                0x0014 0x02DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB                      0x0014 0x02DC 0x0000 0x1 0x0
+#define MX6SLL_PAD_WDOG_B__UART5_RI_B                             0x0014 0x02DC 0x0000 0x2 0x0
+#define MX6SLL_PAD_WDOG_B__GPIO3_IO18                             0x0014 0x02DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M               0x0018 0x02E0 0x0000 0x0 0x0
+#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL                          0x0018 0x02E0 0x068C 0x1 0x0
+#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT                          0x0018 0x02E0 0x0000 0x2 0x0
+#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID                       0x0018 0x02E0 0x0560 0x3 0x0
+#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY                    0x0018 0x02E0 0x05AC 0x4 0x0
+#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21                        0x0018 0x02E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_24M__SD3_WP                            0x0018 0x02E0 0x0794 0x6 0x0
+#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K               0x001C 0x02E4 0x0000 0x0 0x0
+#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA                          0x001C 0x02E4 0x0690 0x1 0x0
+#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT                          0x001C 0x02E4 0x0000 0x2 0x0
+#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID                       0x001C 0x02E4 0x055C 0x3 0x0
+#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL                          0x001C 0x02E4 0x0000 0x4 0x0
+#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22                        0x001C 0x02E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B                          0x001C 0x02E4 0x0780 0x6 0x0
+#define MX6SLL_PAD_PWM1__PWM1_OUT                                 0x0020 0x02E8 0x0000 0x0 0x0
+#define MX6SLL_PAD_PWM1__CCM_CLKO                                 0x0020 0x02E8 0x0000 0x1 0x0
+#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT                            0x0020 0x02E8 0x0000 0x2 0x0
+#define MX6SLL_PAD_PWM1__CSI_MCLK                                 0x0020 0x02E8 0x0000 0x4 0x0
+#define MX6SLL_PAD_PWM1__GPIO3_IO23                               0x0020 0x02E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_PWM1__EPIT1_OUT                                0x0020 0x02E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL0__KEY_COL0                             0x0024 0x02EC 0x06A0 0x0 0x0
+#define MX6SLL_PAD_KEY_COL0__I2C2_SCL                             0x0024 0x02EC 0x0684 0x1 0x0
+#define MX6SLL_PAD_KEY_COL0__LCD_DATA00                           0x0024 0x02EC 0x06D8 0x2 0x0
+#define MX6SLL_PAD_KEY_COL0__SD1_CD_B                             0x0024 0x02EC 0x0770 0x4 0x1
+#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24                           0x0024 0x02EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0                             0x0028 0x02F0 0x06C0 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA                             0x0028 0x02F0 0x0688 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01                           0x0028 0x02F0 0x06DC 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW0__SD1_WP                               0x0028 0x02F0 0x0774 0x4 0x1
+#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25                           0x0028 0x02F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL1__KEY_COL1                             0x002C 0x02F4 0x06A4 0x0 0x0
+#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI                          0x002C 0x02F4 0x0658 0x1 0x1
+#define MX6SLL_PAD_KEY_COL1__LCD_DATA02                           0x002C 0x02F4 0x06E0 0x2 0x0
+#define MX6SLL_PAD_KEY_COL1__SD3_DATA4                            0x002C 0x02F4 0x0784 0x4 0x0
+#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26                           0x002C 0x02F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1                             0x0030 0x02F8 0x06C4 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO                          0x0030 0x02F8 0x0654 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03                           0x0030 0x02F8 0x06E4 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD                            0x0030 0x02F8 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5                            0x0030 0x02F8 0x0788 0x4 0x0
+#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27                           0x0030 0x02F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL2__KEY_COL2                             0x0034 0x02FC 0x06A8 0x0 0x0
+#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0                           0x0034 0x02FC 0x065C 0x1 0x1
+#define MX6SLL_PAD_KEY_COL2__LCD_DATA04                           0x0034 0x02FC 0x06E8 0x2 0x0
+#define MX6SLL_PAD_KEY_COL2__CSI_DATA12                           0x0034 0x02FC 0x05B8 0x3 0x1
+#define MX6SLL_PAD_KEY_COL2__SD3_DATA6                            0x0034 0x02FC 0x078C 0x4 0x0
+#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28                           0x0034 0x02FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2                             0x0038 0x0300 0x06C8 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK                          0x0038 0x0300 0x0650 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05                           0x0038 0x0300 0x06EC 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13                           0x0038 0x0300 0x05BC 0x3 0x1
+#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7                            0x0038 0x0300 0x0790 0x4 0x0
+#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29                           0x0038 0x0300 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL3__KEY_COL3                             0x003C 0x0304 0x06AC 0x0 0x0
+#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS                            0x003C 0x0304 0x05A0 0x1 0x1
+#define MX6SLL_PAD_KEY_COL3__LCD_DATA06                           0x003C 0x0304 0x06F0 0x2 0x0
+#define MX6SLL_PAD_KEY_COL3__CSI_DATA14                           0x003C 0x0304 0x05C0 0x3 0x1
+#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30                           0x003C 0x0304 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL3__SD1_RESET                            0x003C 0x0304 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3                             0x0040 0x0308 0x06CC 0x0 0x1
+#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC                             0x0040 0x0308 0x059C 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07                           0x0040 0x0308 0x06F4 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15                           0x0040 0x0308 0x05C4 0x3 0x2
+#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31                           0x0040 0x0308 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT                          0x0040 0x0308 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL4__KEY_COL4                             0x0044 0x030C 0x06B0 0x0 0x1
+#define MX6SLL_PAD_KEY_COL4__AUD6_RXD                             0x0044 0x030C 0x0594 0x1 0x1
+#define MX6SLL_PAD_KEY_COL4__LCD_DATA08                           0x0044 0x030C 0x06F8 0x2 0x1
+#define MX6SLL_PAD_KEY_COL4__CSI_DATA16                           0x0044 0x030C 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00                           0x0044 0x030C 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR                         0x0044 0x030C 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4                             0x0048 0x0310 0x06D0 0x0 0x1
+#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC                             0x0048 0x0310 0x05A4 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09                           0x0048 0x0310 0x06FC 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17                           0x0048 0x0310 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01                           0x0048 0x0310 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC                          0x0048 0x0310 0x076C 0x6 0x2
+#define MX6SLL_PAD_KEY_COL5__KEY_COL5                             0x004C 0x0314 0x0694 0x0 0x1
+#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS                            0x004C 0x0314 0x05A8 0x1 0x1
+#define MX6SLL_PAD_KEY_COL5__LCD_DATA10                           0x004C 0x0314 0x0700 0x2 0x0
+#define MX6SLL_PAD_KEY_COL5__CSI_DATA18                           0x004C 0x0314 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02                           0x004C 0x0314 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR                         0x004C 0x0314 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5                             0x0050 0x0318 0x06B4 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD                             0x0050 0x0318 0x0598 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11                           0x0050 0x0318 0x0704 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19                           0x0050 0x0318 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03                           0x0050 0x0318 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC                          0x0050 0x0318 0x0768 0x6 0x3
+#define MX6SLL_PAD_KEY_COL6__KEY_COL6                             0x0054 0x031C 0x0698 0x0 0x2
+#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX                         0x0054 0x031C 0x075C 0x1 0x2
+#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX                         0x0054 0x031C 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_COL6__LCD_DATA12                           0x0054 0x031C 0x0708 0x2 0x1
+#define MX6SLL_PAD_KEY_COL6__CSI_DATA20                           0x0054 0x031C 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04                           0x0054 0x031C 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL6__SD3_RESET                            0x0054 0x031C 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6                             0x0058 0x0320 0x06B8 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX                         0x0058 0x0320 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX                         0x0058 0x0320 0x075C 0x1 0x3
+#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13                           0x0058 0x0320 0x070C 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21                           0x0058 0x0320 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05                           0x0058 0x0320 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT                          0x0058 0x0320 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL7__KEY_COL7                             0x005C 0x0324 0x069C 0x0 0x2
+#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS                        0x005C 0x0324 0x0758 0x1 0x2
+#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS                        0x005C 0x0324 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_COL7__LCD_DATA14                           0x005C 0x0324 0x0710 0x2 0x1
+#define MX6SLL_PAD_KEY_COL7__CSI_DATA22                           0x005C 0x0324 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06                           0x005C 0x0324 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL7__SD1_WP                               0x005C 0x0324 0x0774 0x6 0x3
+#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7                             0x0060 0x0328 0x06BC 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS                        0x0060 0x0328 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS                        0x0060 0x0328 0x0758 0x1 0x3
+#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15                           0x0060 0x0328 0x0714 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23                           0x0060 0x0328 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07                           0x0060 0x0328 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B                             0x0060 0x0328 0x0770 0x6 0x3
+#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00                       0x0064 0x032C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI                       0x0064 0x032C 0x0658 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24                        0x0064 0x032C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00                        0x0064 0x032C 0x05C8 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07                        0x0064 0x032C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01                       0x0068 0x0330 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO                       0x0068 0x0330 0x0654 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25                        0x0068 0x0330 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01                        0x0068 0x0330 0x05CC 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08                        0x0068 0x0330 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02                       0x006C 0x0334 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0                        0x006C 0x0334 0x065C 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26                        0x006C 0x0334 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02                        0x006C 0x0334 0x05D0 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09                        0x006C 0x0334 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03                       0x0070 0x0338 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK                       0x0070 0x0338 0x0650 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27                        0x0070 0x0338 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03                        0x0070 0x0338 0x05D4 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10                        0x0070 0x0338 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04                       0x0074 0x033C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1                        0x0074 0x033C 0x0660 0x1 0x1
+#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28                        0x0074 0x033C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04                        0x0074 0x033C 0x05D8 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11                        0x0074 0x033C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05                       0x0078 0x0340 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2                        0x0078 0x0340 0x0664 0x1 0x1
+#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29                        0x0078 0x0340 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05                        0x0078 0x0340 0x05DC 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12                        0x0078 0x0340 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06                       0x007C 0x0344 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3                        0x007C 0x0344 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30                        0x007C 0x0344 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06                        0x007C 0x0344 0x05E0 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13                        0x007C 0x0344 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07                       0x0080 0x0348 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY                        0x0080 0x0348 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31                        0x0080 0x0348 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07                        0x0080 0x0348 0x05E4 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14                        0x0080 0x0348 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08                       0x0084 0x034C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI                       0x0084 0x034C 0x063C 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0                    0x0084 0x034C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15                        0x0084 0x034C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09                       0x0088 0x0350 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO                       0x0088 0x0350 0x0638 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1                    0x0088 0x0350 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16                        0x0088 0x0350 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10                       0x008C 0x0354 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0                        0x008C 0x0354 0x0648 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2                    0x008C 0x0354 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17                        0x008C 0x0354 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11                       0x0090 0x0358 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK                       0x0090 0x0358 0x0630 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3                    0x0090 0x0358 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18                        0x0090 0x0358 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12                       0x0094 0x035C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX                      0x0094 0x035C 0x074C 0x1 0x4
+#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX                      0x0094 0x035C 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM                      0x0094 0x035C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19                        0x0094 0x035C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1                        0x0094 0x035C 0x064C 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13                       0x0098 0x0360 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX                      0x0098 0x0360 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX                      0x0098 0x0360 0x074C 0x1 0x5
+#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ                      0x0098 0x0360 0x0668 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20                        0x0098 0x0360 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2                        0x0098 0x0360 0x0640 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14                       0x009C 0x0364 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS                     0x009C 0x0364 0x0748 0x1 0x4
+#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS                     0x009C 0x0364 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT                     0x009C 0x0364 0x066C 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21                        0x009C 0x0364 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3                        0x009C 0x0364 0x0644 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15                       0x00A0 0x0368 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS                     0x00A0 0x0368 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS                     0x00A0 0x0368 0x0748 0x1 0x5
+#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE                     0x00A0 0x0368 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22                        0x00A0 0x0368 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY                        0x00A0 0x0368 0x0634 0x6 0x1
+#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P                       0x00A4 0x036C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI                        0x00A4 0x036C 0x0624 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL                           0x00A4 0x036C 0x0684 0x2 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08                         0x00A4 0x036C 0x05E8 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23                         0x00A4 0x036C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE                           0x00A8 0x0370 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO                         0x00A8 0x0370 0x0620 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA                            0x00A8 0x0370 0x0688 0x2 0x2
+#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09                          0x00A8 0x0370 0x05EC 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24                          0x00A8 0x0370 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE                           0x00AC 0x0374 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0                          0x00AC 0x0374 0x0628 0x1 0x1
+#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10                          0x00AC 0x0374 0x05B0 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25                          0x00AC 0x0374 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR                         0x00B0 0x0378 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK                        0x00B0 0x0378 0x061C 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4                         0x00B0 0x0378 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11                         0x00B0 0x0378 0x05B4 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26                         0x00B0 0x0378 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0                         0x00B4 0x037C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1                         0x00B4 0x037C 0x062C 0x1 0x1
+#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT                           0x00B4 0x037C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27                         0x00B4 0x037C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1                         0x00B8 0x0380 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B                            0x00B8 0x0380 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT                           0x00B8 0x0380 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28                         0x00B8 0x0380 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2                         0x00BC 0x0384 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL                           0x00BC 0x0384 0x068C 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT                           0x00BC 0x0384 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29                         0x00BC 0x0384 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3                         0x00C0 0x0388 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA                           0x00C0 0x0388 0x0690 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT                           0x00C0 0x0388 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30                         0x00C0 0x0388 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK                         0x00C4 0x038C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2                         0x00C4 0x038C 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK                         0x00C4 0x038C 0x05F4 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31                         0x00C4 0x038C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET                          0x00C4 0x038C 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE                           0x00C8 0x0390 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3                          0x00C8 0x0390 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC                           0x00C8 0x0390 0x05F0 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00                          0x00C8 0x0390 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT                         0x00C8 0x0390 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL                           0x00CC 0x0394 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY                          0x00CC 0x0394 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK                            0x00CC 0x0394 0x0000 0x3 0x0
+#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01                          0x00CC 0x0394 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDRL__SD2_WP                              0x00CC 0x0394 0x077C 0x6 0x2
+#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP                           0x00D0 0x0398 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT                            0x00D0 0x0398 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC                           0x00D0 0x0398 0x05F8 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02                          0x00D0 0x0398 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B                            0x00D0 0x0398 0x0778 0x6 0x2
+#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0                         0x00D4 0x039C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS                          0x00D4 0x039C 0x0588 0x1 0x1
+#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX                       0x00D4 0x039C 0x0754 0x2 0x4
+#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX                       0x00D4 0x039C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03                         0x00D4 0x039C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5                         0x00D4 0x039C 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1                         0x00D8 0x03A0 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD                           0x00D8 0x03A0 0x057C 0x1 0x1
+#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX                       0x00D8 0x03A0 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX                       0x00D8 0x03A0 0x0754 0x2 0x5
+#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04                         0x00D8 0x03A0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6                         0x00D8 0x03A0 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0                           0x00DC 0x03A4 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS                       0x00DC 0x03A4 0x0750 0x2 0x2
+#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS                       0x00DC 0x03A4 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05                          0x00DC 0x03A4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7                          0x00DC 0x03A4 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1                           0x00E0 0x03A8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS                       0x00E0 0x03A8 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS                       0x00E0 0x03A8 0x0750 0x2 0x3
+#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06                          0x00E0 0x03A8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8                          0x00E0 0x03A8 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0                 0x00E4 0x03AC 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC                       0x00E4 0x03AC 0x0584 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16                     0x00E4 0x03AC 0x0718 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07                     0x00E4 0x03AC 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1                 0x00E8 0x03B0 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS                      0x00E8 0x03B0 0x0590 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17                     0x00E8 0x03B0 0x071C 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08                     0x00E8 0x03B0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2                 0x00EC 0x03B4 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD                       0x00EC 0x03B4 0x0580 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18                     0x00EC 0x03B4 0x0720 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09                     0x00EC 0x03B4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3                 0x00F0 0x03B8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC                       0x00F0 0x03B8 0x058C 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19                     0x00F0 0x03B8 0x0724 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10                     0x00F0 0x03B8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM                     0x00F4 0x03BC 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20                       0x00F4 0x03BC 0x0728 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID                      0x00F4 0x03BC 0x055C 0x4 0x4
+#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11                       0x00F4 0x03BC 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET                        0x00F4 0x03BC 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ                     0x00F8 0x03C0 0x0668 0x0 0x1
+#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21                       0x00F8 0x03C0 0x072C 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID                      0x00F8 0x03C0 0x0560 0x4 0x3
+#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12                       0x00F8 0x03C0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT                      0x00F8 0x03C0 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT                   0x00FC 0x03C4 0x066C 0x0 0x1
+#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22                      0x00FC 0x03C4 0x0730 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI                      0x00FC 0x03C4 0x0000 0x4 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13                      0x00FC 0x03C4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP                          0x00FC 0x03C4 0x0794 0x6 0x2
+#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE                   0x0100 0x03C8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23                      0x0100 0x03C8 0x0734 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO                      0x0100 0x03C8 0x0000 0x4 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14                      0x0100 0x03C8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B                        0x0100 0x03C8 0x0780 0x6 0x2
+#define MX6SLL_PAD_LCD_CLK__LCD_CLK                               0x0104 0x03CC 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN                            0x0104 0x03CC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_CLK__PWM4_OUT                              0x0104 0x03CC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15                            0x0104 0x03CC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE                         0x0108 0x03D0 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E                           0x0108 0x03D0 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX                       0x0108 0x03D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX                       0x0108 0x03D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16                         0x0108 0x03D0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC                           0x010C 0x03D4 0x06D4 0x0 0x0
+#define MX6SLL_PAD_LCD_HSYNC__LCD_CS                              0x010C 0x03D4 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX                        0x010C 0x03D4 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX                        0x010C 0x03D4 0x074C 0x4 0x1
+#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17                          0x010C 0x03D4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK                       0x010C 0x03D4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC                           0x0110 0x03D8 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_VSYNC__LCD_RS                              0x0110 0x03D8 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS                       0x0110 0x03D8 0x0748 0x4 0x0
+#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS                       0x0110 0x03D8 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18                          0x0110 0x03D8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL                       0x0110 0x03D8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_RESET__LCD_RESET                           0x0114 0x03DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_RESET__LCD_BUSY                            0x0114 0x03DC 0x06D4 0x2 0x1
+#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS                       0x0114 0x03DC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS                       0x0114 0x03DC 0x0748 0x4 0x1
+#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19                          0x0114 0x03DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY                      0x0114 0x03DC 0x05AC 0x6 0x2
+#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00                         0x0118 0x03E0 0x06D8 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI                        0x0118 0x03E0 0x0608 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID                        0x0118 0x03E0 0x0560 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT                           0x0118 0x03E0 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B                        0x0118 0x03E0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20                         0x0118 0x03E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00                        0x0118 0x03E0 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00                     0x0118 0x03E0 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01                         0x011C 0x03E4 0x06DC 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO                        0x011C 0x03E4 0x0604 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID                        0x011C 0x03E4 0x055C 0x2 0x3
+#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT                           0x011C 0x03E4 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS                          0x011C 0x03E4 0x0570 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21                         0x011C 0x03E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01                        0x011C 0x03E4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01                     0x011C 0x03E4 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02                         0x0120 0x03E8 0x06E0 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0                         0x0120 0x03E8 0x0614 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT                          0x0120 0x03E8 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT                           0x0120 0x03E8 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC                           0x0120 0x03E8 0x056C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22                         0x0120 0x03E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02                        0x0120 0x03E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02                     0x0120 0x03E8 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03                         0x0124 0x03EC 0x06E4 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK                        0x0124 0x03EC 0x05FC 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B                        0x0124 0x03EC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT                           0x0124 0x03EC 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD                           0x0124 0x03EC 0x0564 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23                         0x0124 0x03EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03                        0x0124 0x03EC 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03                     0x0124 0x03EC 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04                         0x0128 0x03F0 0x06E8 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1                         0x0128 0x03F0 0x060C 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC                          0x0128 0x03F0 0x05F8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB                  0x0128 0x03F0 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC                           0x0128 0x03F0 0x0574 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24                         0x0128 0x03F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04                        0x0128 0x03F0 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04                     0x0128 0x03F0 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05                         0x012C 0x03F4 0x06EC 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2                         0x012C 0x03F4 0x0610 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC                          0x012C 0x03F4 0x05F0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS                          0x012C 0x03F4 0x0578 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25                         0x012C 0x03F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05                        0x012C 0x03F4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05                     0x012C 0x03F4 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06                         0x0130 0x03F8 0x06F0 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3                         0x0130 0x03F8 0x0618 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK                         0x0130 0x03F8 0x05F4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD                           0x0130 0x03F8 0x0568 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26                         0x0130 0x03F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06                        0x0130 0x03F8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06                     0x0130 0x03F8 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07                         0x0134 0x03FC 0x06F4 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY                         0x0134 0x03FC 0x0600 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK                           0x0134 0x03FC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT                      0x0134 0x03FC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27                         0x0134 0x03FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07                        0x0134 0x03FC 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07                     0x0134 0x03FC 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08                         0x0138 0x0400 0x06F8 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA08__KEY_COL0                           0x0138 0x0400 0x06A0 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09                         0x0138 0x0400 0x05EC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK                        0x0138 0x0400 0x061C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28                         0x0138 0x0400 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08                        0x0138 0x0400 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08                     0x0138 0x0400 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09                         0x013C 0x0404 0x06FC 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0                           0x013C 0x0404 0x06C0 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08                         0x013C 0x0404 0x05E8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI                        0x013C 0x0404 0x0624 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29                         0x013C 0x0404 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09                        0x013C 0x0404 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09                     0x013C 0x0404 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10                         0x0140 0x0408 0x0700 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA10__KEY_COL1                           0x0140 0x0408 0x06A4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07                         0x0140 0x0408 0x05E4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO                        0x0140 0x0408 0x0620 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30                         0x0140 0x0408 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10                        0x0140 0x0408 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10                     0x0140 0x0408 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11                         0x0144 0x040C 0x0704 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1                           0x0144 0x040C 0x06C4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06                         0x0144 0x040C 0x05E0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1                         0x0144 0x040C 0x062C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31                         0x0144 0x040C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11                        0x0144 0x040C 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11                     0x0144 0x040C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12                         0x0148 0x0410 0x0708 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA12__KEY_COL2                           0x0148 0x0410 0x06A8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05                         0x0148 0x0410 0x05DC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS                      0x0148 0x0410 0x0760 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS                      0x0148 0x0410 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00                         0x0148 0x0410 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12                        0x0148 0x0410 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12                     0x0148 0x0410 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13                         0x014C 0x0414 0x070C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2                           0x014C 0x0414 0x06C8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04                         0x014C 0x0414 0x05D8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS                      0x014C 0x0414 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS                      0x014C 0x0414 0x0760 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01                         0x014C 0x0414 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13                        0x014C 0x0414 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13                     0x014C 0x0414 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14                         0x0150 0x0418 0x0710 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA14__KEY_COL3                           0x0150 0x0418 0x06AC 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03                         0x0150 0x0418 0x05D4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX                       0x0150 0x0418 0x0764 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX                       0x0150 0x0418 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02                         0x0150 0x0418 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14                        0x0150 0x0418 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14                     0x0150 0x0418 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15                         0x0154 0x041C 0x0714 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3                           0x0154 0x041C 0x06CC 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02                         0x0154 0x041C 0x05D0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX                       0x0154 0x041C 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX                       0x0154 0x041C 0x0764 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03                         0x0154 0x041C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15                        0x0154 0x041C 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15                     0x0154 0x041C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16                         0x0158 0x0420 0x0718 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA16__KEY_COL4                           0x0158 0x0420 0x06B0 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01                         0x0158 0x0420 0x05CC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL                           0x0158 0x0420 0x0684 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04                         0x0158 0x0420 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24                     0x0158 0x0420 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17                         0x015C 0x0424 0x071C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4                           0x015C 0x0424 0x06D0 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00                         0x015C 0x0424 0x05C8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA                           0x015C 0x0424 0x0688 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05                         0x015C 0x0424 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25                     0x015C 0x0424 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18                         0x0160 0x0428 0x0720 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA18__KEY_COL5                           0x0160 0x0428 0x0694 0x1 0x2
+#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15                         0x0160 0x0428 0x05C4 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1                       0x0160 0x0428 0x0670 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06                         0x0160 0x0428 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26                     0x0160 0x0428 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19                         0x0164 0x042C 0x0724 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5                           0x0164 0x042C 0x06B4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14                         0x0164 0x042C 0x05C0 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2                       0x0164 0x042C 0x0674 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07                         0x0164 0x042C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27                     0x0164 0x042C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20                         0x0168 0x0430 0x0728 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA20__KEY_COL6                           0x0168 0x0430 0x0698 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13                         0x0168 0x0430 0x05BC 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1                       0x0168 0x0430 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08                         0x0168 0x0430 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28                     0x0168 0x0430 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21                         0x016C 0x0434 0x072C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6                           0x016C 0x0434 0x06B8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12                         0x016C 0x0434 0x05B8 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2                       0x016C 0x0434 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09                         0x016C 0x0434 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29                     0x016C 0x0434 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22                         0x0170 0x0438 0x0730 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA22__KEY_COL7                           0x0170 0x0438 0x069C 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11                         0x0170 0x0438 0x05B4 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3                       0x0170 0x0438 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10                         0x0170 0x0438 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30                     0x0170 0x0438 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23                         0x0174 0x043C 0x0734 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7                           0x0174 0x043C 0x06BC 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10                         0x0174 0x043C 0x05B0 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN                          0x0174 0x043C 0x0678 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11                         0x0174 0x043C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31                     0x0174 0x043C 0x0000 0x7 0x0
+#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS                            0x0178 0x0440 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL                             0x0178 0x0440 0x067C 0x1 0x1
+#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX                         0x0178 0x0440 0x0754 0x2 0x0
+#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX                         0x0178 0x0440 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL                             0x0178 0x0440 0x068C 0x4 0x1
+#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00                           0x0178 0x0440 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0                           0x0178 0x0440 0x0648 0x6 0x0
+#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND                           0x0178 0x0440 0x0000 0x7 0x0
+#define MX6SLL_PAD_AUD_RXC__AUD3_RXC                              0x017C 0x0444 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXC__I2C1_SDA                              0x017C 0x0444 0x0680 0x1 0x1
+#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX                          0x017C 0x0444 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX                          0x017C 0x0444 0x0754 0x2 0x1
+#define MX6SLL_PAD_AUD_RXC__I2C3_SDA                              0x017C 0x0444 0x0690 0x4 0x1
+#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01                            0x017C 0x0444 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1                            0x017C 0x0444 0x064C 0x6 0x0
+#define MX6SLL_PAD_AUD_RXD__AUD3_RXD                              0x0180 0x0448 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI                           0x0180 0x0448 0x063C 0x1 0x0
+#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX                          0x0180 0x0448 0x075C 0x2 0x0
+#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX                          0x0180 0x0448 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXD__SD1_LCTL                              0x0180 0x0448 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02                            0x0180 0x0448 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXC__AUD3_TXC                              0x0184 0x044C 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO                           0x0184 0x044C 0x0638 0x1 0x0
+#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX                          0x0184 0x044C 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX                          0x0184 0x044C 0x075C 0x2 0x1
+#define MX6SLL_PAD_AUD_TXC__SD2_LCTL                              0x0184 0x044C 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03                            0x0184 0x044C 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS                            0x0188 0x0450 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT                             0x0188 0x0450 0x0000 0x1 0x0
+#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS                        0x0188 0x0450 0x0758 0x2 0x0
+#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS                        0x0188 0x0450 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL                             0x0188 0x0450 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04                           0x0188 0x0450 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXD__AUD3_TXD                              0x018C 0x0454 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK                           0x018C 0x0454 0x0630 0x1 0x0
+#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS                         0x018C 0x0454 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS                         0x018C 0x0454 0x0758 0x2 0x1
+#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05                            0x018C 0x0454 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT                        0x0190 0x0458 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT                             0x0190 0x0458 0x0000 0x1 0x0
+#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY                           0x0190 0x0458 0x0634 0x2 0x0
+#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB                    0x0190 0x0458 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06                           0x0190 0x0458 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK                        0x0190 0x0458 0x073C 0x6 0x1
+#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX                        0x0194 0x045C 0x0744 0x0 0x0
+#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX                        0x0194 0x045C 0x0000 0x0 0x0
+#define MX6SLL_PAD_UART1_RXD__PWM1_OUT             &n