Merge tag 'devicetree-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorLinus Torvalds <torvalds@linux-foundation.org>
Thu, 7 Jun 2018 21:06:31 +0000 (14:06 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Thu, 7 Jun 2018 21:06:31 +0000 (14:06 -0700)
Pull DeviceTree updates from Rob Herring:

 - Sync dtc with upstream version v1.4.6-21-g84e414b0b5bc. This adds new
   warnings which are either fixed or disabled by default (enabled with
   W=1).

 - Validate an untrusted offset in DT overlay function
   update_usages_of_a_phandle_reference

 - Fix a use after free error of_platform_device_destroy

 - Fix an off by 1 string errors in unittest

 - Avoid creating a struct device for OPP nodes

 - Update DT specific submitting-patches.txt with patch content and
   subject requirements.

 - Move some bindings to their proper subsystem locations

 - Add vendor prefixes for Kaohsiung, SiFive, Avnet, Wi2Wi, Logic PD,
   and ArcherMind

 - Add documentation for "no-gpio-delays" property in FSI bus GPIO
   master

 - Add compatible for r8a77990 SoC ravb ethernet block

 - More wack-a-mole removal of 'status' property in examples

* tag 'devicetree-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (25 commits)
  dt-bindings: submitting-patches: add guidance on patch content and subject
  of: platform: stop accessing invalid dev in of_platform_device_destroy
  dt-bindings: net: ravb: Add support for r8a77990 SoC
  dt-bindings: Add vendor prefix for ArcherMind
  dt-bindings: fsi-master-gpio: Document "no-gpio-delays" property
  dt-bindings: Add vendor prefix for Logic PD
  of: overlay: validate offset from property fixups
  of: unittest: for strings, account for trailing \0 in property length field
  drm: rcar-du: disable dtc graph-endpoint warnings on DT overlays
  kbuild: disable new dtc graph and unit-address warnings
  scripts/dtc: Update to upstream version v1.4.6-21-g84e414b0b5bc
  MAINTAINERS: add keyword for devicetree overlay notifiers
  dt-bindings: define vendor prefix for Wi2Wi, Inc.
  dt-bindings: Add vendor prefix for Avnet, Inc.
  dt-bindings: Relocate Tegra20 memory controller bindings
  dt-bindings: Add "sifive" vendor prefix
  dt-bindings: exynos: move ADC binding to iio/adc/ directory
  dt-bindings: powerpc/4xx: move 4xx NDFC and EMAC bindings to subsystem directories
  dt-bindings: move various RNG bindings to rng/ directory
  dt-bindings: move various timer bindings to timer/ directory
  ...

63 files changed:
Documentation/devicetree/bindings/arm/arch_timer.txt [deleted file]
Documentation/devicetree/bindings/arm/armv7m_systick.txt [deleted file]
Documentation/devicetree/bindings/arm/global_timer.txt [deleted file]
Documentation/devicetree/bindings/arm/mrvl/timer.txt [deleted file]
Documentation/devicetree/bindings/arm/msm/timer.txt [deleted file]
Documentation/devicetree/bindings/arm/omap/timer.txt [deleted file]
Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt [deleted file]
Documentation/devicetree/bindings/arm/spear-timer.txt [deleted file]
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt [deleted file]
Documentation/devicetree/bindings/arm/twd.txt [deleted file]
Documentation/devicetree/bindings/arm/ux500/boards.txt
Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt [deleted file]
Documentation/devicetree/bindings/c6x/timer64.txt [deleted file]
Documentation/devicetree/bindings/crypto/samsung,exynos-rng4.txt [deleted file]
Documentation/devicetree/bindings/dma/k3dma.txt
Documentation/devicetree/bindings/dma/ti-edma.txt
Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt
Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt [new file with mode: 0644]
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt [new file with mode: 0644]
Documentation/devicetree/bindings/mips/lantiq/rcu.txt
Documentation/devicetree/bindings/mmc/tmio_mmc.txt
Documentation/devicetree/bindings/mtd/ibm,ndfc.txt [new file with mode: 0644]
Documentation/devicetree/bindings/mtd/mtk-nand.txt
Documentation/devicetree/bindings/net/ibm,emac.txt [new file with mode: 0644]
Documentation/devicetree/bindings/net/renesas,ravb.txt
Documentation/devicetree/bindings/nios2/timer.txt [deleted file]
Documentation/devicetree/bindings/pci/xgene-pci.txt
Documentation/devicetree/bindings/powerpc/4xx/emac.txt [deleted file]
Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt [deleted file]
Documentation/devicetree/bindings/powerpc/fsl/gtm.txt [deleted file]
Documentation/devicetree/bindings/pps/pps-gpio.txt
Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt [new file with mode: 0644]
Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt [new file with mode: 0644]
Documentation/devicetree/bindings/sparc_sun_oracle_rng.txt [deleted file]
Documentation/devicetree/bindings/submitting-patches.txt
Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.txt
Documentation/devicetree/bindings/timer/altr,timer-1.0.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/arm,arch_timer.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/arm,armv7m-systick.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/arm,global_timer.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/arm,twd.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/fsl,gtm.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/qcom,msm-timer.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/st,spear-timer.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/ti,c64x+timer64.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/ti,timer.txt [new file with mode: 0644]
Documentation/devicetree/bindings/timer/via,vt8500-timer.txt [new file with mode: 0644]
Documentation/devicetree/bindings/vendor-prefixes.txt
MAINTAINERS
drivers/gpu/drm/rcar-du/Makefile
drivers/of/of_numa.c
drivers/of/platform.c
drivers/of/resolver.c
drivers/of/unittest.c
scripts/Makefile.lib
scripts/dtc/checks.c
scripts/dtc/dtc-lexer.l
scripts/dtc/dtc-parser.y
scripts/dtc/dtc.h
scripts/dtc/livetree.c
scripts/dtc/version_gen.h

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
deleted file mode 100644 (file)
index 68301b7..0000000
+++ /dev/null
@@ -1,112 +0,0 @@
-* ARM architected timer
-
-ARM cores may have a per-core architected timer, which provides per-cpu timers,
-or a memory mapped architected timer, which provides up to 8 frames with a
-physical and optional virtual timer per frame.
-
-The per-core architected timer is attached to a GIC to deliver its
-per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
-to deliver its interrupts via SPIs.
-
-** CP15 Timer node properties:
-
-- compatible : Should at least contain one of
-       "arm,armv7-timer"
-       "arm,armv8-timer"
-
-- interrupts : Interrupt list for secure, non-secure, virtual and
-  hypervisor timers, in that order.
-
-- clock-frequency : The frequency of the main counter, in Hz. Should be present
-  only where necessary to work around broken firmware which does not configure
-  CNTFRQ on all CPUs to a uniform correct value. Use of this property is
-  strongly discouraged; fix your firmware unless absolutely impossible.
-
-- always-on : a boolean property. If present, the timer is powered through an
-  always-on power domain, therefore it never loses context.
-
-- fsl,erratum-a008585 : A boolean property. Indicates the presence of
-  QorIQ erratum A-008585, which says that reading the counter is
-  unreliable unless the same value is returned by back-to-back reads.
-  This also affects writes to the tval register, due to the implicit
-  counter read.
-
-- hisilicon,erratum-161010101 : A boolean property. Indicates the
-  presence of Hisilicon erratum 161010101, which says that reading the
-  counters is unreliable in some cases, and reads may return a value 32
-  beyond the correct value. This also affects writes to the tval
-  registers, due to the implicit counter read.
-
-** Optional properties:
-
-- arm,cpu-registers-not-fw-configured : Firmware does not initialize
-  any of the generic timer CPU registers, which contain their
-  architecturally-defined reset values. Only supported for 32-bit
-  systems which follow the ARMv7 architected reset values.
-
-- arm,no-tick-in-suspend : The main counter does not tick when the system is in
-  low-power system suspend on some SoCs. This behavior does not match the
-  Architecture Reference Manual's specification that the system counter "must
-  be implemented in an always-on power domain."
-
-
-Example:
-
-       timer {
-               compatible = "arm,cortex-a15-timer",
-                            "arm,armv7-timer";
-               interrupts = <1 13 0xf08>,
-                            <1 14 0xf08>,
-                            <1 11 0xf08>,
-                            <1 10 0xf08>;
-               clock-frequency = <100000000>;
-       };
-
-** Memory mapped timer node properties:
-
-- compatible : Should at least contain "arm,armv7-timer-mem".
-
-- clock-frequency : The frequency of the main counter, in Hz. Should be present
-  only when firmware has not configured the MMIO CNTFRQ registers.
-
-- reg : The control frame base address.
-
-Note that #address-cells, #size-cells, and ranges shall be present to ensure
-the CPU can address a frame's registers.
-
-A timer node has up to 8 frame sub-nodes, each with the following properties:
-
-- frame-number: 0 to 7.
-
-- interrupts : Interrupt list for physical and virtual timers in that order.
-  The virtual timer interrupt is optional.
-
-- reg : The first and second view base addresses in that order. The second view
-  base address is optional.
-
-- status : "disabled" indicates the frame is not available for use. Optional.
-
-Example:
-
-       timer@f0000000 {
-               compatible = "arm,armv7-timer-mem";
-               #address-cells = <1>;
-               #size-cells = <1>;
-               ranges;
-               reg = <0xf0000000 0x1000>;
-               clock-frequency = <50000000>;
-
-               frame@f0001000 {
-                       frame-number = <0>
-                       interrupts = <0 13 0x8>,
-                                    <0 14 0x8>;
-                       reg = <0xf0001000 0x1000>,
-                             <0xf0002000 0x1000>;
-               };
-
-               frame@f0003000 {
-                       frame-number = <1>
-                       interrupts = <0 15 0x8>;
-                       reg = <0xf0003000 0x1000>;
-               };
-       };
diff --git a/Documentation/devicetree/bindings/arm/armv7m_systick.txt b/Documentation/devicetree/bindings/arm/armv7m_systick.txt
deleted file mode 100644 (file)
index 7cf4a24..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-* ARMv7M System Timer
-
-ARMv7-M includes a system timer, known as SysTick. Current driver only
-implements the clocksource feature.
-
-Required properties:
-- compatible     : Should be "arm,armv7m-systick"
-- reg            : The address range of the timer
-
-Required clocking property, have to be one of:
-- clocks         : The input clock of the timer
-- clock-frequency : The rate in HZ in input of the ARM SysTick
-
-Examples:
-
-systick: timer@e000e010 {
-       compatible = "arm,armv7m-systick";
-       reg = <0xe000e010 0x10>;
-       clocks = <&clk_systick>;
-};
-
-systick: timer@e000e010 {
-       compatible = "arm,armv7m-systick";
-       reg = <0xe000e010 0x10>;
-       clock-frequency = <90000000>;
-};
diff --git a/Documentation/devicetree/bindings/arm/global_timer.txt b/Documentation/devicetree/bindings/arm/global_timer.txt
deleted file mode 100644 (file)
index bdae3a8..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-
-* ARM Global Timer
-       Cortex-A9 are often associated with a per-core Global timer.
-
-** Timer node required properties:
-
-- compatible : should contain
-            * "arm,cortex-a5-global-timer" for Cortex-A5 global timers.
-            * "arm,cortex-a9-global-timer" for Cortex-A9 global
-                timers or any compatible implementation. Note: driver
-                supports versions r2p0 and above.
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the GT timer
-       register window.
-
-- clocks : Should be phandle to a clock.
-
-Example:
-
-       timer@2c000600 {
-               compatible = "arm,cortex-a9-global-timer";
-               reg = <0x2c000600 0x20>;
-               interrupts = <1 13 0xf01>;
-               clocks = <&arm_periph_clk>;
-       };
diff --git a/Documentation/devicetree/bindings/arm/mrvl/timer.txt b/Documentation/devicetree/bindings/arm/mrvl/timer.txt
deleted file mode 100644 (file)
index 9a6e251..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-* Marvell MMP Timer controller
-
-Required properties:
-- compatible : Should be "mrvl,mmp-timer".
-- reg : Address and length of the register set of timer controller.
-- interrupts : Should be the interrupt number.
-
-Example:
-       timer0: timer@d4014000 {
-               compatible = "mrvl,mmp-timer";
-               reg = <0xd4014000 0x100>;
-               interrupts = <13>;
-       };
diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt
deleted file mode 100644 (file)
index 5e10c34..0000000
+++ /dev/null
@@ -1,47 +0,0 @@
-* MSM Timer
-
-Properties:
-
-- compatible : Should at least contain "qcom,msm-timer". More specific
-               properties specify which subsystem the timers are paired with.
-
-               "qcom,kpss-timer" - krait subsystem
-               "qcom,scss-timer" - scorpion subsystem
-
-- interrupts : Interrupts for the debug timer, the first general purpose
-               timer, and optionally a second general purpose timer, and
-               optionally as well, 2 watchdog interrupts, in that order.
-
-- reg : Specifies the base address of the timer registers.
-
-- clocks: Reference to the parent clocks, one per output clock. The parents
-          must appear in the same order as the clock names.
-
-- clock-names: The name of the clocks as free-form strings. They should be in
-               the same order as the clocks.
-
-- clock-frequency : The frequency of the debug timer and the general purpose
-                    timer(s) in Hz in that order.
-
-Optional:
-
-- cpu-offset : per-cpu offset used when the timer is accessed without the
-               CPU remapping facilities. The offset is
-               cpu-offset + (0x10000 * cpu-nr).
-
-Example:
-
-       timer@200a000 {
-               compatible = "qcom,scss-timer", "qcom,msm-timer";
-               interrupts = <1 1 0x301>,
-                            <1 2 0x301>,
-                            <1 3 0x301>,
-                            <1 4 0x301>,
-                            <1 5 0x301>;
-               reg = <0x0200a000 0x100>;
-               clock-frequency = <19200000>,
-                                 <32768>;
-               clocks = <&sleep_clk>;
-               clock-names = "sleep";
-               cpu-offset = <0x40000>;
-       };
diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt
deleted file mode 100644 (file)
index d02e27c..0000000
+++ /dev/null
@@ -1,44 +0,0 @@
-OMAP Timer bindings
-
-Required properties:
-- compatible:          Should be set to one of the below. Please note that
-                       OMAP44xx devices have timer instances that are 100%
-                       register compatible with OMAP3xxx devices as well as
-                       newer timers that are not 100% register compatible.
-                       So for OMAP44xx devices timer instances may use
-                       different compatible strings.
-
-                       ti,omap2420-timer (applicable to OMAP24xx devices)
-                       ti,omap3430-timer (applicable to OMAP3xxx/44xx devices)
-                       ti,omap4430-timer (applicable to OMAP44xx devices)
-                       ti,omap5430-timer (applicable to OMAP543x devices)
-                       ti,am335x-timer (applicable to AM335x devices)
-                       ti,am335x-timer-1ms (applicable to AM335x devices)
-
-- reg:                 Contains timer register address range (base address and
-                       length).
-- interrupts:          Contains the interrupt information for the timer. The
-                       format is being dependent on which interrupt controller
-                       the OMAP device uses.
-- ti,hwmods:           Name of the hwmod associated to the timer, "timer<X>",
-                       where <X> is the instance number of the timer from the
-                       HW spec.
-
-Optional properties:
-- ti,timer-alwon:      Indicates the timer is in an alway-on power domain.
-- ti,timer-dsp:                Indicates the timer can interrupt the on-chip DSP in
-                       addition to the ARM CPU.
-- ti,timer-pwm:        Indicates the timer can generate a PWM output.
-- ti,timer-secure:     Indicates the timer is reserved on a secure OMAP device
-                       and therefore cannot be used by the kernel.
-
-Example:
-
-timer12: timer@48304000 {
-       compatible = "ti,omap3430-timer";
-       reg = <0x48304000 0x400>;
-       interrupts = <95>;
-       ti,hwmods = "timer12"
-       ti,timer-alwon;
-       ti,timer-secure;
-};
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
deleted file mode 100644 (file)
index 6c49db7..0000000
+++ /dev/null
@@ -1,103 +0,0 @@
-Samsung Exynos Analog to Digital Converter bindings
-
-The devicetree bindings are for the new ADC driver written for
-Exynos4 and upward SoCs from Samsung.
-
-New driver handles the following
-1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
-   and future SoCs from Samsung
-2. Add ADC driver under iio/adc framework
-3. Also adds the Documentation for device tree bindings
-
-Required properties:
-- compatible:          Must be "samsung,exynos-adc-v1"
-                               for exynos4412/5250 and s5pv210 controllers.
-                       Must be "samsung,exynos-adc-v2" for
-                               future controllers.
-                       Must be "samsung,exynos3250-adc" for
-                               controllers compatible with ADC of Exynos3250.
-                       Must be "samsung,exynos7-adc" for
-                               the ADC in Exynos7 and compatibles
-                       Must be "samsung,s3c2410-adc" for
-                               the ADC in s3c2410 and compatibles
-                       Must be "samsung,s3c2416-adc" for
-                               the ADC in s3c2416 and compatibles
-                       Must be "samsung,s3c2440-adc" for
-                               the ADC in s3c2440 and compatibles
-                       Must be "samsung,s3c2443-adc" for
-                               the ADC in s3c2443 and compatibles
-                       Must be "samsung,s3c6410-adc" for
-                               the ADC in s3c6410 and compatibles
-- reg:                 List of ADC register address range
-                       - The base address and range of ADC register
-                       - The base address and range of ADC_PHY register (every
-                         SoC except for s3c24xx/s3c64xx ADC)
-- interrupts:          Contains the interrupt information for the timer. The
-                       format is being dependent on which interrupt controller
-                       the Samsung device uses.
-- #io-channel-cells = <1>; As ADC has multiple outputs
-- clocks               From common clock bindings: handles to clocks specified
-                       in "clock-names" property, in the same order.
-- clock-names          From common clock bindings: list of clock input names
-                       used by ADC block:
-                       - "adc" : ADC bus clock
-                       - "sclk" : ADC special clock (only for Exynos3250 and
-                                  compatible ADC block)
-- vdd-supply           VDD input supply.
-
-- samsung,syscon-phandle Contains the PMU system controller node
-                       (To access the ADC_PHY register on Exynos5250/5420/5800/3250)
-Optional properties:
-- has-touchscreen:     If present, indicates that a touchscreen is
-                       connected an usable.
-
-Note: child nodes can be added for auto probing from device tree.
-
-Example: adding device info in dtsi file
-
-adc: adc@12d10000 {
-       compatible = "samsung,exynos-adc-v1";
-       reg = <0x12D10000 0x100>;
-       interrupts = <0 106 0>;
-       #io-channel-cells = <1>;
-       io-channel-ranges;
-
-       clocks = <&clock 303>;
-       clock-names = "adc";
-
-       vdd-supply = <&buck5_reg>;
-       samsung,syscon-phandle = <&pmu_system_controller>;
-};
-
-Example: adding device info in dtsi file for Exynos3250 with additional sclk
-
-adc: adc@126c0000 {
-       compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
-       reg = <0x126C0000 0x100>;
-       interrupts = <0 137 0>;
-       #io-channel-cells = <1>;
-       io-channel-ranges;
-
-       clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
-       clock-names = "adc", "sclk";
-
-       vdd-supply = <&buck5_reg>;
-       samsung,syscon-phandle = <&pmu_system_controller>;
-};
-
-Example: Adding child nodes in dts file
-
-adc@12d10000 {
-
-       /* NTC thermistor is a hwmon device */
-       ncp15wb473@0 {
-               compatible = "murata,ncp15wb473";
-               pullup-uv = <1800000>;
-               pullup-ohm = <47000>;
-               pulldown-ohm = <0>;
-               io-channels = <&adc 4>;
-       };
-};
-
-Note: Does not apply to ADC driver under arch/arm/plat-samsung/
-Note: The child node can be added under the adc node or separately.
diff --git a/Documentation/devicetree/bindings/arm/spear-timer.txt b/Documentation/devicetree/bindings/arm/spear-timer.txt
deleted file mode 100644 (file)
index c001722..0000000
+++ /dev/null
@@ -1,18 +0,0 @@
-* SPEAr ARM Timer
-
-** Timer node required properties:
-
-- compatible : Should be:
-       "st,spear-timer"
-- reg: Address range of the timer registers
-- interrupt-parent: Should be the phandle for the interrupt controller
-  that services interrupts for this device
-- interrupt: Should contain the timer interrupt number
-
-Example:
-
-       timer@f0000000 {
-               compatible = "st,spear-timer";
-               reg = <0xf0000000 0x400>;
-               interrupts = <2>;
-       };
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt
deleted file mode 100644 (file)
index f9632ba..0000000
+++ /dev/null
@@ -1,16 +0,0 @@
-NVIDIA Tegra20 MC(Memory Controller)
-
-Required properties:
-- compatible : "nvidia,tegra20-mc"
-- reg : Should contain 2 register ranges(address and length); see the
-  example below. Note that the MC registers are interleaved with the
-  GART registers, and hence must be represented as multiple ranges.
-- interrupts : Should contain MC General interrupt.
-
-Example:
-       memory-controller@7000f000 {
-               compatible = "nvidia,tegra20-mc";
-               reg = <0x7000f000 0x024
-                      0x7000f03c 0x3c4>;
-               interrupts = <0 77 0x04>;
-       };
diff --git a/Documentation/devicetree/bindings/arm/twd.txt b/Documentation/devicetree/bindings/arm/twd.txt
deleted file mode 100644 (file)
index 383ea19..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-* ARM Timer Watchdog
-
-ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
-Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
-and watchdog.
-
-The TWD is usually attached to a GIC to deliver its two per-processor
-interrupts.
-
-** Timer node required properties:
-
-- compatible : Should be one of:
-       "arm,cortex-a9-twd-timer"
-       "arm,cortex-a5-twd-timer"
-       "arm,arm11mp-twd-timer"
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the TWD timer
-       register window.
-
-Optional
-
-- always-on : a boolean property. If present, the timer is powered through
-  an always-on power domain, therefore it never loses context.
-
-Example:
-
-       twd-timer@2c000600 {
-               compatible = "arm,arm11mp-twd-timer"";
-               reg = <0x2c000600 0x20>;
-               interrupts = <1 13 0xf01>;
-       };
-
-** Watchdog node properties:
-
-- compatible : Should be one of:
-       "arm,cortex-a9-twd-wdt"
-       "arm,cortex-a5-twd-wdt"
-       "arm,arm11mp-twd-wdt"
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the TWD watchdog
-       register window.
-
-Example:
-
-       twd-watchdog@2c000620 {
-               compatible = "arm,arm11mp-twd-wdt";
-               reg = <0x2c000620 0x20>;
-               interrupts = <1 14 0xf01>;
-       };
index 7334c24625fccf309c5a3708e3e0c1facd0344e5..0fa429534f4910f79193ed177d8da974ee9caf24 100644 (file)
@@ -26,7 +26,7 @@ interrupt-controller:
        see binding for interrupt-controller/arm,gic.txt
 
 timer:
-       see binding for arm/twd.txt
+       see binding for timer/arm,twd.txt
 
 clocks:
        see binding for clocks/ux500.txt
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
deleted file mode 100644 (file)
index 901c73f..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-VIA/Wondermedia VT8500 Timer
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-timer"
-- reg : Should contain 1 register ranges(address and length)
-- interrupts : interrupt for the timer
-
-Example:
-
-       timer@d8130100 {
-               compatible = "via,vt8500-timer";
-               reg = <0xd8130100 0x28>;
-               interrupts = <36>;
-       };
diff --git a/Documentation/devicetree/bindings/c6x/timer64.txt b/Documentation/devicetree/bindings/c6x/timer64.txt
deleted file mode 100644 (file)
index 95911fe..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-Timer64
--------
-
-The timer64 node describes C6X event timers.
-
-Required properties:
-
-- compatible: must be "ti,c64x+timer64"
-- reg: base address and size of register region
-- interrupt-parent: interrupt controller
-- interrupts: interrupt id
-
-Optional properties:
-
-- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
-
-- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
-
-Example:
-       timer0: timer@25e0000 {
-               compatible = "ti,c64x+timer64";
-               ti,core-mask = < 0x01 >;
-               reg = <0x25e0000 0x40>;
-               interrupt-parent = <&megamod_pic>;
-               interrupts = < 16 >;
-       };
diff --git a/Documentation/devicetree/bindings/crypto/samsung,exynos-rng4.txt b/Documentation/devicetree/bindings/crypto/samsung,exynos-rng4.txt
deleted file mode 100644 (file)
index a13fbdb..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-Exynos Pseudo Random Number Generator
-
-Required properties:
-
-- compatible  : One of:
-                - "samsung,exynos4-rng" for Exynos4210 and Exynos4412
-                - "samsung,exynos5250-prng" for Exynos5250+
-- reg         : Specifies base physical address and size of the registers map.
-- clocks      : Phandle to clock-controller plus clock-specifier pair.
-- clock-names : "secss" as a clock name.
-
-Example:
-
-       rng@10830400 {
-               compatible = "samsung,exynos4-rng";
-               reg = <0x10830400 0x200>;
-               clocks = <&clock CLK_SSS>;
-               clock-names = "secss";
-       };
index 23f8d712c3ce531c31023c21cffde12470212ffc..4945aeac4dc4f0b12499a6b947227fcf785325f5 100644 (file)
@@ -23,7 +23,6 @@ Controller:
                        dma-requests = <27>;
                        interrupts = <0 12 4>;
                        clocks = <&pclk>;
-                       status = "disable";
                };
 
 Client:
index 66026dcf53e12cfa8077a60480cefe7a8c6cff18..3f15f6644527313057e2ca8d90bf5e2f51296a3e 100644 (file)
@@ -190,7 +190,6 @@ mmc0: mmc@23000000 {
        power-domains = <&k2g_pds 0xb>;
        clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
        clock-names = "fck", "mmchsdb_fck";
-       status = "disabled";
 };
 
 ------------------------------------------------------------------------------
index a767259dedadc51cd333c284f121902858046e5a..1e442450747f9c9c9c68a2a71893255359acabdf 100644 (file)
@@ -11,6 +11,10 @@ Optional properties:
  - trans-gpios = <gpio-descriptor>;    : GPIO for voltage translator enable
  - mux-gpios = <gpio-descriptor>;      : GPIO for pin multiplexing with other
                                           functions (eg, external FSI masters)
+ - no-gpio-delays;                     : Don't add extra delays between GPIO
+                                          accesses. This is useful when the HW
+                                         GPIO block is running at a low enough
+                                         frequency.
 
 Examples:
 
diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt
new file mode 100644 (file)
index 0000000..6c49db7
--- /dev/null
@@ -0,0 +1,103 @@
+Samsung Exynos Analog to Digital Converter bindings
+
+The devicetree bindings are for the new ADC driver written for
+Exynos4 and upward SoCs from Samsung.
+
+New driver handles the following
+1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
+   and future SoCs from Samsung
+2. Add ADC driver under iio/adc framework
+3. Also adds the Documentation for device tree bindings
+
+Required properties:
+- compatible:          Must be "samsung,exynos-adc-v1"
+                               for exynos4412/5250 and s5pv210 controllers.
+                       Must be "samsung,exynos-adc-v2" for
+                               future controllers.
+                       Must be "samsung,exynos3250-adc" for
+                               controllers compatible with ADC of Exynos3250.
+                       Must be "samsung,exynos7-adc" for
+                               the ADC in Exynos7 and compatibles
+                       Must be "samsung,s3c2410-adc" for
+                               the ADC in s3c2410 and compatibles
+                       Must be "samsung,s3c2416-adc" for
+                               the ADC in s3c2416 and compatibles
+                       Must be "samsung,s3c2440-adc" for
+                               the ADC in s3c2440 and compatibles
+                       Must be "samsung,s3c2443-adc" for
+                               the ADC in s3c2443 and compatibles
+                       Must be "samsung,s3c6410-adc" for
+                               the ADC in s3c6410 and compatibles
+- reg:                 List of ADC register address range
+                       - The base address and range of ADC register
+                       - The base address and range of ADC_PHY register (every
+                         SoC except for s3c24xx/s3c64xx ADC)
+- interrupts:          Contains the interrupt information for the timer. The
+                       format is being dependent on which interrupt controller
+                       the Samsung device uses.
+- #io-channel-cells = <1>; As ADC has multiple outputs
+- clocks               From common clock bindings: handles to clocks specified
+                       in "clock-names" property, in the same order.
+- clock-names          From common clock bindings: list of clock input names
+                       used by ADC block:
+                       - "adc" : ADC bus clock
+                       - "sclk" : ADC special clock (only for Exynos3250 and
+                                  compatible ADC block)
+- vdd-supply           VDD input supply.
+
+- samsung,syscon-phandle Contains the PMU system controller node
+                       (To access the ADC_PHY register on Exynos5250/5420/5800/3250)
+Optional properties:
+- has-touchscreen:     If present, indicates that a touchscreen is
+                       connected an usable.
+
+Note: child nodes can be added for auto probing from device tree.
+
+Example: adding device info in dtsi file
+
+adc: adc@12d10000 {
+       compatible = "samsung,exynos-adc-v1";
+       reg = <0x12D10000 0x100>;
+       interrupts = <0 106 0>;
+       #io-channel-cells = <1>;
+       io-channel-ranges;
+
+       clocks = <&clock 303>;
+       clock-names = "adc";
+
+       vdd-supply = <&buck5_reg>;
+       samsung,syscon-phandle = <&pmu_system_controller>;
+};
+
+Example: adding device info in dtsi file for Exynos3250 with additional sclk
+
+adc: adc@126c0000 {
+       compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
+       reg = <0x126C0000 0x100>;
+       interrupts = <0 137 0>;
+       #io-channel-cells = <1>;
+       io-channel-ranges;
+
+       clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
+       clock-names = "adc", "sclk";
+
+       vdd-supply = <&buck5_reg>;
+       samsung,syscon-phandle = <&pmu_system_controller>;
+};
+
+Example: Adding child nodes in dts file
+
+adc@12d10000 {
+
+       /* NTC thermistor is a hwmon device */
+       ncp15wb473@0 {
+               compatible = "murata,ncp15wb473";
+               pullup-uv = <1800000>;
+               pullup-ohm = <47000>;
+               pulldown-ohm = <0>;
+               io-channels = <&adc 4>;
+       };
+};
+
+Note: Does not apply to ADC driver under arch/arm/plat-samsung/
+Note: The child node can be added under the adc node or separately.
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
new file mode 100644 (file)
index 0000000..f9632ba
--- /dev/null
@@ -0,0 +1,16 @@
+NVIDIA Tegra20 MC(Memory Controller)
+
+Required properties:
+- compatible : "nvidia,tegra20-mc"
+- reg : Should contain 2 register ranges(address and length); see the
+  example below. Note that the MC registers are interleaved with the
+  GART registers, and hence must be represented as multiple ranges.
+- interrupts : Should contain MC General interrupt.
+
+Example:
+       memory-controller@7000f000 {
+               compatible = "nvidia,tegra20-mc";
+               reg = <0x7000f000 0x024
+                      0x7000f03c 0x3c4>;
+               interrupts = <0 77 0x04>;
+       };
index a086f1e1cdd78809f87f145dba13adaf68849602..7f0822b4beae404f630ba9d222b8560d5440fcec 100644 (file)
@@ -61,7 +61,6 @@ Example of the RCU bindings on a xRX200 SoC:
                usb_phy0: usb2-phy@18 {
                        compatible = "lantiq,xrx200-usb2-phy";
                        reg = <0x18 4>, <0x38 4>;
-                       status = "disabled";
 
                        resets = <&reset1 4 4>, <&reset0 4 4>;
                        reset-names = "phy", "ctrl";
@@ -71,7 +70,6 @@ Example of the RCU bindings on a xRX200 SoC:
                usb_phy1: usb2-phy@34 {
                        compatible = "lantiq,xrx200-usb2-phy";
                        reg = <0x34 4>, <0x3C 4>;
-                       status = "disabled";
 
                        resets = <&reset1 5 4>, <&reset0 4 4>;
                        reset-names = "phy", "ctrl";
index ee978c95189d729447b18dc7d075cf1a2a71fd3e..839f469f4525bbe2799c41798e30a22d0377b34d 100644 (file)
@@ -69,7 +69,6 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
                max-frequency = <195000000>;
                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                resets = <&cpg 314>;
-               status = "disabled";
        };
 
        sdhi1: sd@ee120000 {
@@ -83,7 +82,6 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
                max-frequency = <195000000>;
                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                resets = <&cpg 313>;
-               status = "disabled";
        };
 
        sdhi2: sd@ee140000 {
@@ -97,7 +95,6 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
                max-frequency = <97500000>;
                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                resets = <&cpg 312>;
-               status = "disabled";
        };
 
        sdhi3: sd@ee160000 {
@@ -111,5 +108,4 @@ Example: R8A7790 (R-Car H2) SDHI controller nodes
                max-frequency = <97500000>;
                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                resets = <&cpg 311>;
-               status = "disabled";
        };
diff --git a/Documentation/devicetree/bindings/mtd/ibm,ndfc.txt b/Documentation/devicetree/bindings/mtd/ibm,ndfc.txt
new file mode 100644 (file)
index 0000000..869f0b5
--- /dev/null
@@ -0,0 +1,39 @@
+AMCC NDFC (NanD Flash Controller)
+
+Required properties:
+- compatible : "ibm,ndfc".
+- reg : should specify chip select and size used for the chip (0x2000).
+
+Optional properties:
+- ccr : NDFC config and control register value (default 0).
+- bank-settings : NDFC bank configuration register value (default 0).
+
+Notes:
+- partition(s) - follows the OF MTD standard for partitions
+
+Example:
+
+ndfc@1,0 {
+       compatible = "ibm,ndfc";
+       reg = <0x00000001 0x00000000 0x00002000>;
+       ccr = <0x00001000>;
+       bank-settings = <0x80002222>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       nand {
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               partition@0 {
+                       label = "kernel";
+                       reg = <0x00000000 0x00200000>;
+               };
+               partition@200000 {
+                       label = "root";
+                       reg = <0x00200000 0x03E00000>;
+               };
+       };
+};
+
+
index 1c88526dedfc2a370d0a8ccf13c4247c63dacb78..c5ba6a4ba1f2f013369019f652c66d0fb0ef46ad 100644 (file)
@@ -20,7 +20,6 @@ Required NFI properties:
 - interrupts:                  Interrupts of NFI.
 - clocks:                      NFI required clocks.
 - clock-names:                 NFI clocks internal name.
-- status:                      Disabled default. Then set "okay" by platform.
 - ecc-engine:                  Required ECC Engine node.
 - #address-cells:              NAND chip index, should be 1.
 - #size-cells:                 Should be 0.
@@ -34,7 +33,6 @@ Example:
                clocks = <&pericfg CLK_PERI_NFI>,
                         <&pericfg CLK_PERI_NFI_PAD>;
                clock-names = "nfi_clk", "pad_clk";
-               status = "disabled";
                ecc-engine = <&bch>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -152,7 +150,6 @@ Required BCH properties:
 - interrupts:  Interrupts of ECC.
 - clocks:      ECC required clocks.
 - clock-names: ECC clocks internal name.
-- status:      Disabled default. Then set "okay" by platform.
 
 Example:
 
@@ -162,5 +159,4 @@ Example:
                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
                clocks = <&pericfg CLK_PERI_NFI_ECC>;
                clock-names = "nfiecc_clk";
-               status = "disabled";
        };
diff --git a/Documentation/devicetree/bindings/net/ibm,emac.txt b/Documentation/devicetree/bindings/net/ibm,emac.txt
new file mode 100644 (file)
index 0000000..44b842b
--- /dev/null
@@ -0,0 +1,206 @@
+    4xx/Axon EMAC ethernet nodes
+
+    The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
+    the Axon bridge.  To operate this needs to interact with a this
+    special McMAL DMA controller, and sometimes an RGMII or ZMII
+    interface.  In addition to the nodes and properties described
+    below, the node for the OPB bus on which the EMAC sits must have a
+    correct clock-frequency property.
+
+      i) The EMAC node itself
+
+    Required properties:
+    - device_type       : "network"
+
+    - compatible        : compatible list, contains 2 entries, first is
+                         "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
+                         405gp, Axon) and second is either "ibm,emac" or
+                         "ibm,emac4".  For Axon, thus, we have: "ibm,emac-axon",
+                         "ibm,emac4"
+    - interrupts        : <interrupt mapping for EMAC IRQ and WOL IRQ>
+    - interrupt-parent  : optional, if needed for interrupt mapping
+    - reg               : <registers mapping>
+    - local-mac-address : 6 bytes, MAC address
+    - mal-device        : phandle of the associated McMAL node
+    - mal-tx-channel    : 1 cell, index of the tx channel on McMAL associated
+                         with this EMAC
+    - mal-rx-channel    : 1 cell, index of the rx channel on McMAL associated
+                         with this EMAC
+    - cell-index        : 1 cell, hardware index of the EMAC cell on a given
+                         ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
+                         each Axon chip)
+    - max-frame-size    : 1 cell, maximum frame size supported in bytes
+    - rx-fifo-size      : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
+                         operations.
+                         For Axon, 2048
+    - tx-fifo-size      : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
+                         operations.
+                         For Axon, 2048.
+    - fifo-entry-size   : 1 cell, size of a fifo entry (used to calculate
+                         thresholds).
+                         For Axon, 0x00000010
+    - mal-burst-size    : 1 cell, MAL burst size (used to calculate thresholds)
+                         in bytes.
+                         For Axon, 0x00000100 (I think ...)
+    - phy-mode          : string, mode of operations of the PHY interface.
+                         Supported values are: "mii", "rmii", "smii", "rgmii",
+                         "tbi", "gmii", rtbi", "sgmii".
+                         For Axon on CAB, it is "rgmii"
+    - mdio-device       : 1 cell, required iff using shared MDIO registers
+                         (440EP).  phandle of the EMAC to use to drive the
+                         MDIO lines for the PHY used by this EMAC.
+    - zmii-device       : 1 cell, required iff connected to a ZMII.  phandle of
+                         the ZMII device node
+    - zmii-channel      : 1 cell, required iff connected to a ZMII.  Which ZMII
+                         channel or 0xffffffff if ZMII is only used for MDIO.
+    - rgmii-device      : 1 cell, required iff connected to an RGMII. phandle
+                         of the RGMII device node.
+                         For Axon: phandle of plb5/plb4/opb/rgmii
+    - rgmii-channel     : 1 cell, required iff connected to an RGMII.  Which
+                         RGMII channel is used by this EMAC.
+                         Fox Axon: present, whatever value is appropriate for each
+                         EMAC, that is the content of the current (bogus) "phy-port"
+                         property.
+
+    Optional properties:
+    - phy-address       : 1 cell, optional, MDIO address of the PHY. If absent,
+                         a search is performed.
+    - phy-map           : 1 cell, optional, bitmap of addresses to probe the PHY
+                         for, used if phy-address is absent. bit 0x00000001 is
+                         MDIO address 0.
+                         For Axon it can be absent, though my current driver
+                         doesn't handle phy-address yet so for now, keep
+                         0x00ffffff in it.
+    - phy-handle       : Used to describe configurations where a external PHY
+                         is used. Please refer to:
+                         Documentation/devicetree/bindings/net/ethernet.txt
+    - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
+                         operations (if absent the value is the same as
+                         rx-fifo-size).  For Axon, either absent or 2048.
+    - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
+                         operations (if absent the value is the same as
+                         tx-fifo-size). For Axon, either absent or 2048.
+    - tah-device        : 1 cell, optional. If connected to a TAH engine for
+                         offload, phandle of the TAH device node.
+    - tah-channel       : 1 cell, optional. If appropriate, channel used on the
+                         TAH engine.
+    - fixed-link       : Fixed-link subnode describing a link to a non-MDIO
+                         managed entity. See
+                         Documentation/devicetree/bindings/net/fixed-link.txt
+                         for details.
+    - mdio subnode     : When the EMAC has a phy connected to its local
+                         mdio, which us supported by the kernel's network
+                         PHY library in drivers/net/phy, there must be device
+                         tree subnode with the following required properties:
+                               - #address-cells: Must be <1>.
+                               - #size-cells: Must be <0>.
+
+                         For PHY definitions: Please refer to
+                         Documentation/devicetree/bindings/net/phy.txt and
+                         Documentation/devicetree/bindings/net/ethernet.txt
+
+    Examples:
+
+       EMAC0: ethernet@40000800 {
+               device_type = "network";
+               compatible = "ibm,emac-440gp", "ibm,emac";
+               interrupt-parent = <&UIC1>;
+               interrupts = <1c 4 1d 4>;
+               reg = <40000800 70>;
+               local-mac-address = [00 04 AC E3 1B 1E];
+               mal-device = <&MAL0>;
+               mal-tx-channel = <0 1>;
+               mal-rx-channel = <0>;
+               cell-index = <0>;
+               max-frame-size = <5dc>;
+               rx-fifo-size = <1000>;
+               tx-fifo-size = <800>;
+               phy-mode = "rmii";
+               phy-map = <00000001>;
+               zmii-device = <&ZMII0>;
+               zmii-channel = <0>;
+       };
+
+       EMAC1: ethernet@ef600c00 {
+               device_type = "network";
+               compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
+               interrupt-parent = <&EMAC1>;
+               interrupts = <0 1>;
+               #interrupt-cells = <1>;
+               #address-cells = <0>;
+               #size-cells = <0>;
+               interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */
+                                1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH /* Wake */>;
+               reg = <0xef600c00 0x000000c4>;
+               local-mac-address = [000000000000]; /* Filled in by U-Boot */
+               mal-device = <&MAL0>;
+               mal-tx-channel = <0>;
+               mal-rx-channel = <0>;
+               cell-index = <0>;
+               max-frame-size = <9000>;
+               rx-fifo-size = <16384>;
+               tx-fifo-size = <2048>;
+               fifo-entry-size = <10>;
+               phy-mode = "rgmii";
+               phy-handle = <&phy0>;
+               phy-map = <0x00000000>;
+               rgmii-device = <&RGMII0>;
+               rgmii-channel = <0>;
+               tah-device = <&TAH0>;
+               tah-channel = <0>;
+               has-inverted-stacr-oc;
+               has-new-stacr-staopc;
+
+               mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       phy0: ethernet-phy@0 {
+                               compatible = "ethernet-phy-ieee802.3-c22";
+                               reg = <0>;
+                       };
+               };
+       };
+
+
+      ii) McMAL node
+
+    Required properties:
+    - device_type        : "dma-controller"
+    - compatible         : compatible list, containing 2 entries, first is
+                          "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
+                          emac) and the second is either "ibm,mcmal" or
+                          "ibm,mcmal2".
+                          For Axon, "ibm,mcmal-axon","ibm,mcmal2"
+    - interrupts         : <interrupt mapping for the MAL interrupts sources:
+                           5 sources: tx_eob, rx_eob, serr, txde, rxde>.
+                           For Axon: This is _different_ from the current
+                          firmware.  We use the "delayed" interrupts for txeob
+                          and rxeob. Thus we end up with mapping those 5 MPIC
+                          interrupts, all level positive sensitive: 10, 11, 32,
+                          33, 34 (in decimal)
+    - dcr-reg            : < DCR registers range >
+    - dcr-parent         : if needed for dcr-reg
+    - num-tx-chans       : 1 cell, number of Tx channels
+    - num-rx-chans       : 1 cell, number of Rx channels
+
+      iii) ZMII node
+
+    Required properties:
+    - compatible         : compatible list, containing 2 entries, first is
+                          "ibm,zmii-CHIP" where CHIP is the host ASIC (like
+                          EMAC) and the second is "ibm,zmii".
+                          For Axon, there is no ZMII node.
+    - reg                : <registers mapping>
+
+      iv) RGMII node
+
+    Required properties:
+    - compatible         : compatible list, containing 2 entries, first is
+                          "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
+                          EMAC) and the second is "ibm,rgmii".
+                           For Axon, "ibm,rgmii-axon","ibm,rgmii"
+    - reg                : <registers mapping>
+    - revision           : as provided by the RGMII new version register if
+                          available.
+                          For Axon: 0x0000012a
index 890526dbfc26478f623a8e0b7f78d966509171e7..fac897d54423c11e60ce1438e3ebd68c69db9126 100644 (file)
@@ -21,6 +21,7 @@ Required properties:
       - "renesas,etheravb-r8a77965" for the R8A77965 SoC.
       - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
       - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
+      - "renesas,etheravb-r8a77990" for the R8A77990 SoC.
       - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
       - "renesas,etheravb-rcar-gen3" as a fallback for the above
                R-Car Gen3 devices.
diff --git a/Documentation/devicetree/bindings/nios2/timer.txt b/Documentation/devicetree/bindings/nios2/timer.txt
deleted file mode 100644 (file)
index 904a584..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-Altera Timer
-
-Required properties:
-
-- compatible : should be "altr,timer-1.0"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-parent: phandle of the interrupt controller
-- interrupts : Should contain the timer interrupt number
-- clock-frequency : The frequency of the clock that drives the counter, in Hz.
-
-Example:
-
-timer {
-       compatible = "altr,timer-1.0";
-       reg = <0x00400000 0x00000020>;
-       interrupt-parent = <&cpu>;
-       interrupts = <11>;
-       clock-frequency = <125000000>;
-};
index 6fd2decfa66c4b30d0de6d77f57ceef77eadd28a..92490330dc1c7e7444dfe1176944cbb06b36a97b 100644 (file)
@@ -25,8 +25,6 @@ Optional properties:
 
 Example:
 
-SoC-specific DT Entry:
-
        pcie0: pcie@1f2b0000 {
                status = "disabled";
                device_type = "pci";
@@ -50,8 +48,3 @@ SoC-specific DT Entry:
                clocks = <&pcie0clk 0>;
        };
 
-
-Board-specific DT Entry:
-       &pcie0 {
-               status = "ok";
-       };
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/emac.txt b/Documentation/devicetree/bindings/powerpc/4xx/emac.txt
deleted file mode 100644 (file)
index 44b842b..0000000
+++ /dev/null
@@ -1,206 +0,0 @@
-    4xx/Axon EMAC ethernet nodes
-
-    The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
-    the Axon bridge.  To operate this needs to interact with a this
-    special McMAL DMA controller, and sometimes an RGMII or ZMII
-    interface.  In addition to the nodes and properties described
-    below, the node for the OPB bus on which the EMAC sits must have a
-    correct clock-frequency property.
-
-      i) The EMAC node itself
-
-    Required properties:
-    - device_type       : "network"
-
-    - compatible        : compatible list, contains 2 entries, first is
-                         "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
-                         405gp, Axon) and second is either "ibm,emac" or
-                         "ibm,emac4".  For Axon, thus, we have: "ibm,emac-axon",
-                         "ibm,emac4"
-    - interrupts        : <interrupt mapping for EMAC IRQ and WOL IRQ>
-    - interrupt-parent  : optional, if needed for interrupt mapping
-    - reg               : <registers mapping>
-    - local-mac-address : 6 bytes, MAC address
-    - mal-device        : phandle of the associated McMAL node
-    - mal-tx-channel    : 1 cell, index of the tx channel on McMAL associated
-                         with this EMAC
-    - mal-rx-channel    : 1 cell, index of the rx channel on McMAL associated
-                         with this EMAC
-    - cell-index        : 1 cell, hardware index of the EMAC cell on a given
-                         ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
-                         each Axon chip)
-    - max-frame-size    : 1 cell, maximum frame size supported in bytes
-    - rx-fifo-size      : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
-                         operations.
-                         For Axon, 2048
-    - tx-fifo-size      : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
-                         operations.
-                         For Axon, 2048.
-    - fifo-entry-size   : 1 cell, size of a fifo entry (used to calculate
-                         thresholds).
-                         For Axon, 0x00000010
-    - mal-burst-size    : 1 cell, MAL burst size (used to calculate thresholds)
-                         in bytes.
-                         For Axon, 0x00000100 (I think ...)
-    - phy-mode          : string, mode of operations of the PHY interface.
-                         Supported values are: "mii", "rmii", "smii", "rgmii",
-                         "tbi", "gmii", rtbi", "sgmii".
-                         For Axon on CAB, it is "rgmii"
-    - mdio-device       : 1 cell, required iff using shared MDIO registers
-                         (440EP).  phandle of the EMAC to use to drive the
-                         MDIO lines for the PHY used by this EMAC.
-    - zmii-device       : 1 cell, required iff connected to a ZMII.  phandle of
-                         the ZMII device node
-    - zmii-channel      : 1 cell, required iff connected to a ZMII.  Which ZMII
-                         channel or 0xffffffff if ZMII is only used for MDIO.
-    - rgmii-device      : 1 cell, required iff connected to an RGMII. phandle
-                         of the RGMII device node.
-                         For Axon: phandle of plb5/plb4/opb/rgmii
-    - rgmii-channel     : 1 cell, required iff connected to an RGMII.  Which
-                         RGMII channel is used by this EMAC.
-                         Fox Axon: present, whatever value is appropriate for each
-                         EMAC, that is the content of the current (bogus) "phy-port"
-                         property.
-
-    Optional properties:
-    - phy-address       : 1 cell, optional, MDIO address of the PHY. If absent,
-                         a search is performed.
-    - phy-map           : 1 cell, optional, bitmap of addresses to probe the PHY
-                         for, used if phy-address is absent. bit 0x00000001 is
-                         MDIO address 0.
-                         For Axon it can be absent, though my current driver
-                         doesn't handle phy-address yet so for now, keep
-                         0x00ffffff in it.
-    - phy-handle       : Used to describe configurations where a external PHY
-                         is used. Please refer to:
-                         Documentation/devicetree/bindings/net/ethernet.txt
-    - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
-                         operations (if absent the value is the same as
-                         rx-fifo-size).  For Axon, either absent or 2048.
-    - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
-                         operations (if absent the value is the same as
-                         tx-fifo-size). For Axon, either absent or 2048.
-    - tah-device        : 1 cell, optional. If connected to a TAH engine for
-                         offload, phandle of the TAH device node.
-    - tah-channel       : 1 cell, optional. If appropriate, channel used on the
-                         TAH engine.
-    - fixed-link       : Fixed-link subnode describing a link to a non-MDIO
-                         managed entity. See
-                         Documentation/devicetree/bindings/net/fixed-link.txt
-                         for details.
-    - mdio subnode     : When the EMAC has a phy connected to its local
-                         mdio, which us supported by the kernel's network
-                         PHY library in drivers/net/phy, there must be device
-                         tree subnode with the following required properties:
-                               - #address-cells: Must be <1>.
-                               - #size-cells: Must be <0>.
-
-                         For PHY definitions: Please refer to
-                         Documentation/devicetree/bindings/net/phy.txt and
-                         Documentation/devicetree/bindings/net/ethernet.txt
-
-    Examples:
-
-       EMAC0: ethernet@40000800 {
-               device_type = "network";
-               compatible = "ibm,emac-440gp", "ibm,emac";
-               interrupt-parent = <&UIC1>;
-               interrupts = <1c 4 1d 4>;
-               reg = <40000800 70>;
-               local-mac-address = [00 04 AC E3 1B 1E];
-               mal-device = <&MAL0>;
-               mal-tx-channel = <0 1>;
-               mal-rx-channel = <0>;
-               cell-index = <0>;
-               max-frame-size = <5dc>;
-               rx-fifo-size = <1000>;
-               tx-fifo-size = <800>;
-               phy-mode = "rmii";
-               phy-map = <00000001>;
-               zmii-device = <&ZMII0>;
-               zmii-channel = <0>;
-       };
-
-       EMAC1: ethernet@ef600c00 {
-               device_type = "network";
-               compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
-               interrupt-parent = <&EMAC1>;
-               interrupts = <0 1>;
-               #interrupt-cells = <1>;
-               #address-cells = <0>;
-               #size-cells = <0>;
-               interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */
-                                1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH /* Wake */>;
-               reg = <0xef600c00 0x000000c4>;
-               local-mac-address = [000000000000]; /* Filled in by U-Boot */
-               mal-device = <&MAL0>;
-               mal-tx-channel = <0>;
-               mal-rx-channel = <0>;
-               cell-index = <0>;
-               max-frame-size = <9000>;
-               rx-fifo-size = <16384>;
-               tx-fifo-size = <2048>;
-               fifo-entry-size = <10>;
-               phy-mode = "rgmii";
-               phy-handle = <&phy0>;
-               phy-map = <0x00000000>;
-               rgmii-device = <&RGMII0>;
-               rgmii-channel = <0>;
-               tah-device = <&TAH0>;
-               tah-channel = <0>;
-               has-inverted-stacr-oc;
-               has-new-stacr-staopc;
-
-               mdio {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       phy0: ethernet-phy@0 {
-                               compatible = "ethernet-phy-ieee802.3-c22";
-                               reg = <0>;
-                       };
-               };
-       };
-
-
-      ii) McMAL node
-
-    Required properties:
-    - device_type        : "dma-controller"
-    - compatible         : compatible list, containing 2 entries, first is
-                          "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
-                          emac) and the second is either "ibm,mcmal" or
-                          "ibm,mcmal2".
-                          For Axon, "ibm,mcmal-axon","ibm,mcmal2"
-    - interrupts         : <interrupt mapping for the MAL interrupts sources:
-                           5 sources: tx_eob, rx_eob, serr, txde, rxde>.
-                           For Axon: This is _different_ from the current
-                          firmware.  We use the "delayed" interrupts for txeob
-                          and rxeob. Thus we end up with mapping those 5 MPIC
-                          interrupts, all level positive sensitive: 10, 11, 32,
-                          33, 34 (in decimal)
-    - dcr-reg            : < DCR registers range >
-    - dcr-parent         : if needed for dcr-reg
-    - num-tx-chans       : 1 cell, number of Tx channels
-    - num-rx-chans       : 1 cell, number of Rx channels
-
-      iii) ZMII node
-
-    Required properties:
-    - compatible         : compatible list, containing 2 entries, first is
-                          "ibm,zmii-CHIP" where CHIP is the host ASIC (like
-                          EMAC) and the second is "ibm,zmii".
-                          For Axon, there is no ZMII node.
-    - reg                : <registers mapping>
-
-      iv) RGMII node
-
-    Required properties:
-    - compatible         : compatible list, containing 2 entries, first is
-                          "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
-                          EMAC) and the second is "ibm,rgmii".
-                           For Axon, "ibm,rgmii-axon","ibm,rgmii"
-    - reg                : <registers mapping>
-    - revision           : as provided by the RGMII new version register if
-                          available.
-                          For Axon: 0x0000012a
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt b/Documentation/devicetree/bindings/powerpc/4xx/ndfc.txt
deleted file mode 100644 (file)
index 869f0b5..0000000
+++ /dev/null
@@ -1,39 +0,0 @@
-AMCC NDFC (NanD Flash Controller)
-
-Required properties:
-- compatible : "ibm,ndfc".
-- reg : should specify chip select and size used for the chip (0x2000).
-
-Optional properties:
-- ccr : NDFC config and control register value (default 0).
-- bank-settings : NDFC bank configuration register value (default 0).
-
-Notes:
-- partition(s) - follows the OF MTD standard for partitions
-
-Example:
-
-ndfc@1,0 {
-       compatible = "ibm,ndfc";
-       reg = <0x00000001 0x00000000 0x00002000>;
-       ccr = <0x00001000>;
-       bank-settings = <0x80002222>;
-       #address-cells = <1>;
-       #size-cells = <1>;
-
-       nand {
-               #address-cells = <1>;
-               #size-cells = <1>;
-
-               partition@0 {
-                       label = "kernel";
-                       reg = <0x00000000 0x00200000>;
-               };
-               partition@200000 {
-                       label = "root";
-                       reg = <0x00200000 0x03E00000>;
-               };
-       };
-};
-
-
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/gtm.txt b/Documentation/devicetree/bindings/powerpc/fsl/gtm.txt
deleted file mode 100644 (file)
index 9a33efd..0000000
+++ /dev/null
@@ -1,31 +0,0 @@
-* Freescale General-purpose Timers Module
-
-Required properties:
-  - compatible : should be
-    "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
-    "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
-    "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
-  - reg : should contain gtm registers location and length (0x40).
-  - interrupts : should contain four interrupts.
-  - interrupt-parent : interrupt source phandle.
-  - clock-frequency : specifies the frequency driving the timer.
-
-Example:
-
-timer@500 {
-       compatible = "fsl,mpc8360-gtm", "fsl,gtm";
-       reg = <0x500 0x40>;
-       interrupts = <90 8 78 8 84 8 72 8>;
-       interrupt-parent = <&ipic>;
-       /* filled by u-boot */
-       clock-frequency = <0>;
-};
-
-timer@440 {
-       compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
-       reg = <0x440 0x40>;
-       interrupts = <12 13 14 15>;
-       interrupt-parent = <&qeic>;
-       /* filled by u-boot */
-       clock-frequency = <0>;
-};
index 0de23b79365729d376a97032d76231ad70aa9b38..3683874832ae10a03c9fe842299d315e4d305d7d 100644 (file)
@@ -20,5 +20,4 @@ Example:
                assert-falling-edge;
 
                compatible = "pps-gpio";
-               status = "okay";
        };
index 2e53324fb720db9b29db0baaf6bf878ce9b9fd0e..5ccfcc82da08347e9ed073c353ad2210731c4024 100644 (file)
@@ -2,7 +2,7 @@
 
 Required properties:
 - compatible: Shall contain "ti,omap-dmtimer-pwm".
-- ti,timers: phandle to PWM capable OMAP timer. See arm/omap/timer.txt for info
+- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer.txt for info
   about these timers.
 - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
   the cells format.
diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt
new file mode 100644 (file)
index 0000000..a13fbdb
--- /dev/null
@@ -0,0 +1,19 @@
+Exynos Pseudo Random Number Generator
+
+Required properties:
+
+- compatible  : One of:
+                - "samsung,exynos4-rng" for Exynos4210 and Exynos4412
+                - "samsung,exynos5250-prng" for Exynos5250+
+- reg         : Specifies base physical address and size of the registers map.
+- clocks      : Phandle to clock-controller plus clock-specifier pair.
+- clock-names : "secss" as a clock name.
+
+Example:
+
+       rng@10830400 {
+               compatible = "samsung,exynos4-rng";
+               reg = <0x10830400 0x200>;
+               clocks = <&clock CLK_SSS>;
+               clock-names = "secss";
+       };
diff --git a/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt b/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt
new file mode 100644 (file)
index 0000000..b0b2111
--- /dev/null
@@ -0,0 +1,30 @@
+HWRNG support for the n2_rng driver
+
+Required properties:
+- reg          : base address to sample from
+- compatible   : should contain one of the following
+       RNG versions:
+       - 'SUNW,n2-rng' for Niagara 2 Platform (SUN UltraSPARC T2 CPU)
+       - 'SUNW,vf-rng' for Victoria Falls Platform (SUN UltraSPARC T2 Plus CPU)
+       - 'SUNW,kt-rng' for Rainbow/Yosemite Falls Platform (SUN SPARC T3/T4), (UltraSPARC KT/Niagara 3 - development names)
+       more recent systems (after Oracle acquisition of SUN)
+       - 'ORCL,m4-rng' for SPARC T5/M5
+       - 'ORCL,m7-rng' for SPARC T7/M7
+
+Examples:
+/* linux LDOM on SPARC T5-2 */
+Node 0xf029a4f4
+       .node:  f029a4f4
+       rng-#units:  00000002
+       compatible: 'ORCL,m4-rng'
+       reg:  0000000e
+       name: 'random-number-generator'
+
+/* solaris on SPARC M7-8 */
+Node 0xf028c08c
+       rng-#units:  00000003
+       compatible: 'ORCL,m7-rng'
+       reg:  0000000e
+       name:  'random-number-generator'
+
+PS: see as well prtconfs.git by DaveM
diff --git a/Documentation/devicetree/bindings/sparc_sun_oracle_rng.txt b/Documentation/devicetree/bindings/sparc_sun_oracle_rng.txt
deleted file mode 100644 (file)
index b0b2111..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-HWRNG support for the n2_rng driver
-
-Required properties:
-- reg          : base address to sample from
-- compatible   : should contain one of the following
-       RNG versions:
-       - 'SUNW,n2-rng' for Niagara 2 Platform (SUN UltraSPARC T2 CPU)
-       - 'SUNW,vf-rng' for Victoria Falls Platform (SUN UltraSPARC T2 Plus CPU)
-       - 'SUNW,kt-rng' for Rainbow/Yosemite Falls Platform (SUN SPARC T3/T4), (UltraSPARC KT/Niagara 3 - development names)
-       more recent systems (after Oracle acquisition of SUN)
-       - 'ORCL,m4-rng' for SPARC T5/M5
-       - 'ORCL,m7-rng' for SPARC T7/M7
-
-Examples:
-/* linux LDOM on SPARC T5-2 */
-Node 0xf029a4f4
-       .node:  f029a4f4
-       rng-#units:  00000002
-       compatible: 'ORCL,m4-rng'
-       reg:  0000000e
-       name: 'random-number-generator'
-
-/* solaris on SPARC M7-8 */
-Node 0xf028c08c
-       rng-#units:  00000003
-       compatible: 'ORCL,m7-rng'
-       reg:  0000000e
-       name:  'random-number-generator'
-
-PS: see as well prtconfs.git by DaveM
index 274058c583dde67297f800087c9e2ecaf7a57eac..de0d6090c0fd200f241aa0c71b5d208c62bde45c 100644 (file)
@@ -6,7 +6,14 @@ I. For patch submitters
   0) Normal patch submission rules from Documentation/process/submitting-patches.rst
      applies.
 
-  1) The Documentation/ portion of the patch should be a separate patch.
+  1) The Documentation/ and include/dt-bindings/ portion of the patch should
+     be a separate patch. The preferred subject prefix for binding patches is:
+
+       "dt-bindings: <binding dir>: ..."
+
+     The 80 characters of the subject are precious. It is recommended to not
+     use "Documentation" or "doc" because that is implied. All bindings are
+     docs. Repeating "binding" again should also be avoided.
 
   2) Submit the entire series to the devicetree mailinglist at
 
index fdf5caa6229b4fffe95853e061e9c62c83307364..39e7d4e61a63c038e003d739c5602f2cc97a55e7 100644 (file)
@@ -27,9 +27,9 @@ Example:
 
        tsc: thermal@e6198000 {
                compatible = "renesas,r8a7795-thermal";
-               reg = <0 0xe6198000 0 0x68>,
-                     <0 0xe61a0000 0 0x5c>,
-                     <0 0xe61a8000 0 0x5c>;
+               reg = <0 0xe6198000 0 0x100>,
+                     <0 0xe61a0000 0 0x100>,
+                     <0 0xe61a8000 0 0x100>;
                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt b/Documentation/devicetree/bindings/timer/altr,timer-1.0.txt
new file mode 100644 (file)
index 0000000..904a584
--- /dev/null
@@ -0,0 +1,19 @@
+Altera Timer
+
+Required properties:
+
+- compatible : should be "altr,timer-1.0"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-parent: phandle of the interrupt controller
+- interrupts : Should contain the timer interrupt number
+- clock-frequency : The frequency of the clock that drives the counter, in Hz.
+
+Example:
+
+timer {
+       compatible = "altr,timer-1.0";
+       reg = <0x00400000 0x00000020>;
+       interrupt-parent = <&cpu>;
+       interrupts = <11>;
+       clock-frequency = <125000000>;
+};
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt b/Documentation/devicetree/bindings/timer/arm,arch_timer.txt
new file mode 100644 (file)
index 0000000..68301b7
--- /dev/null
@@ -0,0 +1,112 @@
+* ARM architected timer
+
+ARM cores may have a per-core architected timer, which provides per-cpu timers,
+or a memory mapped architected timer, which provides up to 8 frames with a
+physical and optional virtual timer per frame.
+
+The per-core architected timer is attached to a GIC to deliver its
+per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
+to deliver its interrupts via SPIs.
+
+** CP15 Timer node properties:
+
+- compatible : Should at least contain one of
+       "arm,armv7-timer"
+       "arm,armv8-timer"
+
+- interrupts : Interrupt list for secure, non-secure, virtual and
+  hypervisor timers, in that order.
+
+- clock-frequency : The frequency of the main counter, in Hz. Should be present
+  only where necessary to work around broken firmware which does not configure
+  CNTFRQ on all CPUs to a uniform correct value. Use of this property is
+  strongly discouraged; fix your firmware unless absolutely impossible.
+
+- always-on : a boolean property. If present, the timer is powered through an
+  always-on power domain, therefore it never loses context.
+
+- fsl,erratum-a008585 : A boolean property. Indicates the presence of
+  QorIQ erratum A-008585, which says that reading the counter is
+  unreliable unless the same value is returned by back-to-back reads.
+  This also affects writes to the tval register, due to the implicit
+  counter read.
+
+- hisilicon,erratum-161010101 : A boolean property. Indicates the
+  presence of Hisilicon erratum 161010101, which says that reading the
+  counters is unreliable in some cases, and reads may return a value 32
+  beyond the correct value. This also affects writes to the tval
+  registers, due to the implicit counter read.
+
+** Optional properties:
+
+- arm,cpu-registers-not-fw-configured : Firmware does not initialize
+  any of the generic timer CPU registers, which contain their
+  architecturally-defined reset values. Only supported for 32-bit
+  systems which follow the ARMv7 architected reset values.
+
+- arm,no-tick-in-suspend : The main counter does not tick when the system is in
+  low-power system suspend on some SoCs. This behavior does not match the
+  Architecture Reference Manual's specification that the system counter "must
+  be implemented in an always-on power domain."
+
+
+Example:
+
+       timer {
+               compatible = "arm,cortex-a15-timer",
+                            "arm,armv7-timer";
+               interrupts = <1 13 0xf08>,
+                            <1 14 0xf08>,
+                            <1 11 0xf08>,
+                            <1 10 0xf08>;
+               clock-frequency = <100000000>;
+       };
+
+** Memory mapped timer node properties:
+
+- compatible : Should at least contain "arm,armv7-timer-mem".
+
+- clock-frequency : The frequency of the main counter, in Hz. Should be present
+  only when firmware has not configured the MMIO CNTFRQ registers.
+
+- reg : The control frame base address.
+
+Note that #address-cells, #size-cells, and ranges shall be present to ensure
+the CPU can address a frame's registers.
+
+A timer node has up to 8 frame sub-nodes, each with the following properties:
+
+- frame-number: 0 to 7.
+
+- interrupts : Interrupt list for physical and virtual timers in that order.
+  The virtual timer interrupt is optional.
+
+- reg : The first and second view base addresses in that order. The second view
+  base address is optional.
+
+- status : "disabled" indicates the frame is not available for use. Optional.
+
+Example:
+
+       timer@f0000000 {
+               compatible = "arm,armv7-timer-mem";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               reg = <0xf0000000 0x1000>;
+               clock-frequency = <50000000>;
+
+               frame@f0001000 {
+                       frame-number = <0>
+                       interrupts = <0 13 0x8>,
+                                    <0 14 0x8>;
+                       reg = <0xf0001000 0x1000>,
+                             <0xf0002000 0x1000>;
+               };
+
+               frame@f0003000 {
+                       frame-number = <1>
+                       interrupts = <0 15 0x8>;
+                       reg = <0xf0003000 0x1000>;
+               };
+       };
diff --git a/Documentation/devicetree/bindings/timer/arm,armv7m-systick.txt b/Documentation/devicetree/bindings/timer/arm,armv7m-systick.txt
new file mode 100644 (file)
index 0000000..7cf4a24
--- /dev/null
@@ -0,0 +1,26 @@
+* ARMv7M System Timer
+
+ARMv7-M includes a system timer, known as SysTick. Current driver only
+implements the clocksource feature.
+
+Required properties:
+- compatible     : Should be "arm,armv7m-systick"
+- reg            : The address range of the timer
+
+Required clocking property, have to be one of:
+- clocks         : The input clock of the timer
+- clock-frequency : The rate in HZ in input of the ARM SysTick
+
+Examples:
+
+systick: timer@e000e010 {
+       compatible = "arm,armv7m-systick";
+       reg = <0xe000e010 0x10>;
+       clocks = <&clk_systick>;
+};
+
+systick: timer@e000e010 {
+       compatible = "arm,armv7m-systick";
+       reg = <0xe000e010 0x10>;
+       clock-frequency = <90000000>;
+};
diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.txt b/Documentation/devicetree/bindings/timer/arm,global_timer.txt
new file mode 100644 (file)
index 0000000..bdae3a8
--- /dev/null
@@ -0,0 +1,27 @@
+
+* ARM Global Timer
+       Cortex-A9 are often associated with a per-core Global timer.
+
+** Timer node required properties:
+
+- compatible : should contain
+            * "arm,cortex-a5-global-timer" for Cortex-A5 global timers.
+            * "arm,cortex-a9-global-timer" for Cortex-A9 global
+                timers or any compatible implementation. Note: driver
+                supports versions r2p0 and above.
+
+- interrupts : One interrupt to each core
+
+- reg : Specify the base address and the size of the GT timer
+       register window.
+
+- clocks : Should be phandle to a clock.
+
+Example:
+
+       timer@2c000600 {
+               compatible = "arm,cortex-a9-global-timer";
+               reg = <0x2c000600 0x20>;
+               interrupts = <1 13 0xf01>;
+               clocks = <&arm_periph_clk>;
+       };
diff --git a/Documentation/devicetree/bindings/timer/arm,twd.txt b/Documentation/devicetree/bindings/timer/arm,twd.txt
new file mode 100644 (file)
index 0000000..383ea19
--- /dev/null
@@ -0,0 +1,53 @@
+* ARM Timer Watchdog
+
+ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
+Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
+and watchdog.
+
+The TWD is usually attached to a GIC to deliver its two per-processor
+interrupts.
+
+** Timer node required properties:
+
+- compatible : Should be one of:
+       "arm,cortex-a9-twd-timer"
+       "arm,cortex-a5-twd-timer"
+       "arm,arm11mp-twd-timer"
+
+- interrupts : One interrupt to each core
+
+- reg : Specify the base address and the size of the TWD timer
+       register window.
+
+Optional
+
+- always-on : a boolean property. If present, the timer is powered through
+  an always-on power domain, therefore it never loses context.
+
+Example:
+
+       twd-timer@2c000600 {
+               compatible = "arm,arm11mp-twd-timer"";
+               reg = <0x2c000600 0x20>;
+               interrupts = <1 13 0xf01>;
+       };
+
+** Watchdog node properties:
+
+- compatible : Should be one of:
+       "arm,cortex-a9-twd-wdt"
+       "arm,cortex-a5-twd-wdt"
+       "arm,arm11mp-twd-wdt"
+
+- interrupts : One interrupt to each core
+
+- reg : Specify the base address and the size of the TWD watchdog
+       register window.
+
+Example:
+
+       twd-watchdog@2c000620 {
+               compatible = "arm,arm11mp-twd-wdt";
+               reg = <0x2c000620 0x20>;
+               interrupts = <1 14 0xf01>;
+       };
diff --git a/Documentation/devicetree/bindings/timer/fsl,gtm.txt b/Documentation/devicetree/bindings/timer/fsl,gtm.txt
new file mode 100644 (file)
index 0000000..9a33efd
--- /dev/null
@@ -0,0 +1,31 @@
+* Freescale General-purpose Timers Module
+
+Required properties:
+  - compatible : should be
+    "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
+    "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
+    "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
+  - reg : should contain gtm registers location and length (0x40).
+  - interrupts : should contain four interrupts.
+  - interrupt-parent : interrupt source phandle.
+  - clock-frequency : specifies the frequency driving the timer.
+
+Example:
+
+timer@500 {
+       compatible = "fsl,mpc8360-gtm", "fsl,gtm";
+       reg = <0x500 0x40>;
+       interrupts = <90 8 78 8 84 8 72 8>;
+       interrupt-parent = <&ipic>;
+       /* filled by u-boot */
+       clock-frequency = <0>;
+};
+
+timer@440 {
+       compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
+       reg = <0x440 0x40>;
+       interrupts = <12 13 14 15>;
+       interrupt-parent = <&qeic>;
+       /* filled by u-boot */
+       clock-frequency = <0>;
+};
diff --git a/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt b/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt
new file mode 100644 (file)
index 0000000..9a6e251
--- /dev/null
@@ -0,0 +1,13 @@
+* Marvell MMP Timer controller
+
+Required properties:
+- compatible : Should be "mrvl,mmp-timer".
+- reg : Address and length of the register set of timer controller.
+- interrupts : Should be the interrupt number.
+
+Example:
+       timer0: timer@d4014000 {
+               compatible = "mrvl,mmp-timer";
+               reg = <0xd4014000 0x100>;
+               interrupts = <13>;
+       };
diff --git a/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt b/Documentation/devicetree/bindings/timer/qcom,msm-timer.txt
new file mode 100644 (file)
index 0000000..5e10c34
--- /dev/null
@@ -0,0 +1,47 @@
+* MSM Timer
+
+Properties:
+
+- compatible : Should at least contain "qcom,msm-timer". More specific
+               properties specify which subsystem the timers are paired with.
+
+               "qcom,kpss-timer" - krait subsystem
+               "qcom,scss-timer" - scorpion subsystem
+
+- interrupts : Interrupts for the debug timer, the first general purpose
+               timer, and optionally a second general purpose timer, and
+               optionally as well, 2 watchdog interrupts, in that order.
+
+- reg : Specifies the base address of the timer registers.
+
+- clocks: Reference to the parent clocks, one per output clock. The parents
+          must appear in the same order as the clock names.
+
+- clock-names: The name of the clocks as free-form strings. They should be in
+               the same order as the clocks.
+
+- clock-frequency : The frequency of the debug timer and the general purpose
+                    timer(s) in Hz in that order.
+
+Optional:
+
+- cpu-offset : per-cpu offset used when the timer is accessed without the
+               CPU remapping facilities. The offset is
+               cpu-offset + (0x10000 * cpu-nr).
+
+Example:
+
+       timer@200a000 {
+               compatible = "qcom,scss-timer", "qcom,msm-timer";
+               interrupts = <1 1 0x301>,
+                            <1 2 0x301>,
+                            <1 3 0x301>,
+                            <1 4 0x301>,
+                            <1 5 0x301>;
+               reg = <0x0200a000 0x100>;
+               clock-frequency = <19200000>,
+                                 <32768>;
+               clocks = <&sleep_clk>;
+               clock-names = "sleep";
+               cpu-offset = <0x40000>;
+       };
diff --git a/Documentation/devicetree/bindings/timer/st,spear-timer.txt b/Documentation/devicetree/bindings/timer/st,spear-timer.txt
new file mode 100644 (file)
index 0000000..c001722
--- /dev/null
@@ -0,0 +1,18 @@
+* SPEAr ARM Timer
+
+** Timer node required properties:
+
+- compatible : Should be:
+       "st,spear-timer"
+- reg: Address range of the timer registers
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupt: Should contain the timer interrupt number
+
+Example:
+
+       timer@f0000000 {
+               compatible = "st,spear-timer";
+               reg = <0xf0000000 0x400>;
+               interrupts = <2>;
+       };
diff --git a/Documentation/devicetree/bindings/timer/ti,c64x+timer64.txt b/Documentation/devicetree/bindings/timer/ti,c64x+timer64.txt
new file mode 100644 (file)
index 0000000..95911fe
--- /dev/null
@@ -0,0 +1,26 @@
+Timer64
+-------
+
+The timer64 node describes C6X event timers.
+
+Required properties:
+
+- compatible: must be "ti,c64x+timer64"
+- reg: base address and size of register region
+- interrupt-parent: interrupt controller
+- interrupts: interrupt id
+
+Optional properties:
+
+- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
+
+- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
+
+Example:
+       timer0: timer@25e0000 {
+               compatible = "ti,c64x+timer64";
+               ti,core-mask = < 0x01 >;
+               reg = <0x25e0000 0x40>;
+               interrupt-parent = <&megamod_pic>;
+               interrupts = < 16 >;
+       };
diff --git a/Documentation/devicetree/bindings/timer/ti,timer.txt b/Documentation/devicetree/bindings/timer/ti,timer.txt
new file mode 100644 (file)
index 0000000..d02e27c
--- /dev/null
@@ -0,0 +1,44 @@
+OMAP Timer bindings
+
+Required properties:
+- compatible:          Should be set to one of the below. Please note that
+                       OMAP44xx devices have timer instances that are 100%
+                       register compatible with OMAP3xxx devices as well as
+                       newer timers that are not 100% register compatible.
+                       So for OMAP44xx devices timer instances may use
+                       different compatible strings.
+
+                       ti,omap2420-timer (applicable to OMAP24xx devices)
+                       ti,omap3430-timer (applicable to OMAP3xxx/44xx devices)
+                       ti,omap4430-timer (applicable to OMAP44xx devices)
+                       ti,omap5430-timer (applicable to OMAP543x devices)
+                       ti,am335x-timer (applicable to AM335x devices)
+                       ti,am335x-timer-1ms (applicable to AM335x devices)
+
+- reg:                 Contains timer register address range (base address and
+                       length).
+- interrupts:          Contains the interrupt information for the timer. The
+                       format is being dependent on which interrupt controller
+                       the OMAP device uses.
+- ti,hwmods:           Name of the hwmod associated to the timer, "timer<X>",
+                       where <X> is the instance number of the timer from the
+                       HW spec.
+
+Optional properties:
+- ti,timer-alwon:      Indicates the timer is in an alway-on power domain.
+- ti,timer-dsp:                Indicates the timer can interrupt the on-chip DSP in
+                       addition to the ARM CPU.
+- ti,timer-pwm:        Indicates the timer can generate a PWM output.
+- ti,timer-secure:     Indicates the timer is reserved on a secure OMAP device
+                       and therefore cannot be used by the kernel.
+
+Example:
+
+timer12: timer@48304000 {
+       compatible = "ti,omap3430-timer";
+       reg = <0x48304000 0x400>;
+       interrupts = <95>;
+       ti,hwmods = "timer12"
+       ti,timer-alwon;
+       ti,timer-secure;
+};
diff --git a/Documentation/devicetree/bindings/timer/via,vt8500-timer.txt b/Documentation/devicetree/bindings/timer/via,vt8500-timer.txt
new file mode 100644 (file)
index 0000000..901c73f
--- /dev/null
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Timer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-timer"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : interrupt for the timer
+
+Example:
+
+       timer@d8130100 {
+               compatible = "via,vt8500-timer";
+               reg = <0xd8130100 0x28>;
+               interrupts = <36>;
+       };
index 74e9db9e90885f1e86e6f9c8261388520eedc6f9..4b38f3373f4322501a99a67d043cf7f9da3f1acb 100644 (file)
@@ -32,6 +32,7 @@ andestech     Andes Technology Corporation
 apm    Applied Micro Circuits Corporation (APM)
 aptina Aptina Imaging
 arasan Arasan Chip Systems
+archermind ArcherMind Technology (Nanjing) Co., Ltd.
 arctic Arctic Sand
 aries  Aries Embedded GmbH
 arm    ARM Ltd.
@@ -47,6 +48,7 @@ auvidea Auvidea GmbH
 avago  Avago Technologies
 avia   avia semiconductor
 avic   Shanghai AVIC Optoelectronics Co., Ltd.
+avnet  Avnet, Inc.
 axentia        Axentia Technologies AB
 axis   Axis Communications AB
 bananapi BIPAI KEJI LIMITED
@@ -186,6 +188,7 @@ khadas      Khadas
 kiebackpeter    Kieback & Peter GmbH
 kinetic Kinetic Technologies
 kingnovel      Kingnovel Technology Co., Ltd.
+koe    Kaohsiung Opto-Electronics Inc.
 kosagi Sutajio Ko-Usagi PTE Ltd.
 kyo    Kyocera Corporation
 lacie  LaCie
@@ -200,6 +203,7 @@ linaro      Linaro Limited
 linksys        Belkin International, Inc. (Linksys)
 linux  Linux-specific binding
 lltc   Linear Technology Corporation
+logicpd        Logic PD, Inc.
 lsi    LSI Corp. (LSI Logic)
 lwn    Liebherr-Werk Nenzing GmbH
 macnica        Macnica Americas
@@ -320,6 +324,7 @@ sgx SGX Sensortech
 sharp  Sharp Corporation
 shimafuji      Shimafuji Electric, Inc.
 si-en  Si-En Technology Ltd.
+sifive SiFive, Inc.
 sigma  Sigma Designs, Inc.
 sii    Seiko Instruments, Inc.
 sil    Silicon Image
@@ -395,6 +400,7 @@ vot Vision Optical Technology Co., Ltd.
 wd     Western Digital Corp.
 wetek  WeTek Electronics, limited.
 wexler Wexler
+wi2wi  Wi2Wi, Inc.
 winbond Winbond Electronics corp.
 winstar        Winstar Display Corp.
 wlf    Wolfson Microelectronics
index 5c29a7dee379cf5e95bbe165b1c3b5252d8f2f76..d325d2dc76002e3bb756bf1e9791914dc1bbe0c0 100644 (file)
@@ -10510,12 +10510,14 @@ F:    drivers/infiniband/ulp/opa_vnic
 
 OPEN FIRMWARE AND DEVICE TREE OVERLAYS
 M:     Pantelis Antoniou <pantelis.antoniou@konsulko.com>
+M:     Frank Rowand <frowand.list@gmail.com>
 L:     devicetree@vger.kernel.org
 S:     Maintained
 F:     Documentation/devicetree/dynamic-resolution-notes.txt
 F:     Documentation/devicetree/overlay-notes.txt
 F:     drivers/of/overlay.c
 F:     drivers/of/resolver.c
+K:     of_overlay_notifier_
 
 OPEN FIRMWARE AND FLATTENED DEVICE TREE
 M:     Rob Herring <robh+dt@kernel.org>
index 3e58ed93d5b1d18dfae87c8960160a0b8e9de5e5..2a3b8d7972b54131dcc280ab0d9d7e35ce21950e 100644 (file)
@@ -17,3 +17,10 @@ rcar-du-drm-$(CONFIG_DRM_RCAR_VSP)   += rcar_du_vsp.o
 obj-$(CONFIG_DRM_RCAR_DU)              += rcar-du-drm.o
 obj-$(CONFIG_DRM_RCAR_DW_HDMI)         += rcar_dw_hdmi.o
 obj-$(CONFIG_DRM_RCAR_LVDS)            += rcar_lvds.o
+
+# 'remote-endpoint' is fixed up at run-time
+DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint
+DTC_FLAGS_rcar_du_of_lvds_r8a7791 += -Wno-graph_endpoint
+DTC_FLAGS_rcar_du_of_lvds_r8a7793 += -Wno-graph_endpoint
+DTC_FLAGS_rcar_du_of_lvds_r8a7795 += -Wno-graph_endpoint
+DTC_FLAGS_rcar_du_of_lvds_r8a7796 += -Wno-graph_endpoint
index f9d5480a4ae5331dd1ce3bdd2de2ea5f66ac572c..27d9b4bba535c21181324d6652129f84ff174083 100644 (file)
@@ -177,7 +177,6 @@ int of_node_to_nid(struct device_node *device)
 
        return NUMA_NO_NODE;
 }
-EXPORT_SYMBOL(of_node_to_nid);
 
 int __init of_numa_init(void)
 {
index c00d81dfac0b848a70e0533bc851a0c28bc4114c..0b49a62b38a3800aff88b76307a294d093876dd4 100644 (file)
@@ -32,6 +32,11 @@ const struct of_device_id of_default_bus_match_table[] = {
        {} /* Empty terminated list */
 };
 
+static const struct of_device_id of_skipped_node_table[] = {
+       { .compatible = "operating-points-v2", },
+       {} /* Empty terminated list */
+};
+
 static int of_dev_node_match(struct device *dev, void *data)
 {
        return dev->of_node == data;
@@ -356,6 +361,12 @@ static int of_platform_bus_create(struct device_node *bus,
                return 0;
        }
 
+       /* Skip nodes for which we don't want to create devices */
+       if (unlikely(of_match_node(of_skipped_node_table, bus))) {
+               pr_debug("%s() - skipping %pOF node\n", __func__, bus);
+               return 0;
+       }
+
        if (of_node_check_flag(bus, OF_POPULATED_BUS)) {
                pr_debug("%s() - skipping %pOF, already populated\n",
                        __func__, bus);
@@ -537,6 +548,9 @@ int of_platform_device_destroy(struct device *dev, void *data)
        if (of_node_check_flag(dev->of_node, OF_POPULATED_BUS))
                device_for_each_child(dev, NULL, of_platform_device_destroy);
 
+       of_node_clear_flag(dev->of_node, OF_POPULATED);
+       of_node_clear_flag(dev->of_node, OF_POPULATED_BUS);
+
        if (dev->bus == &platform_bus_type)
                platform_device_unregister(to_platform_device(dev));
 #ifdef CONFIG_ARM_AMBA
@@ -544,8 +558,6 @@ int of_platform_device_destroy(struct device *dev, void *data)
                amba_device_unregister(to_amba_device(dev));
 #endif
 
-       of_node_clear_flag(dev->of_node, OF_POPULATED);
-       of_node_clear_flag(dev->of_node, OF_POPULATED_BUS);
        return 0;
 }
 EXPORT_SYMBOL_GPL(of_platform_device_destroy);
index 65d0b7adfcd4b2208521226aef8b84f6203205ea..7edfac6f1914459f135af8d96823ea338770c6a6 100644 (file)
@@ -122,6 +122,11 @@ static int update_usages_of_a_phandle_reference(struct device_node *overlay,
                        goto err_fail;
                }
 
+               if (offset < 0 || offset + sizeof(__be32) > prop->length) {
+                       err = -EINVAL;
+                       goto err_fail;
+               }
+
                *(__be32 *)(prop->value + offset) = cpu_to_be32(phandle);
        }
 
index 6bb37c18292a855c90d80c9f162dcb6ae4cfeed5..ecee50d10d149a7894d8feb274b95ea46fa7fb22 100644 (file)
@@ -165,20 +165,20 @@ static void __init of_unittest_dynamic(void)
        /* Add a new property - should pass*/
        prop->name = "new-property";
        prop->value = "new-property-data";
-       prop->length = strlen(prop->value);
+       prop->length = strlen(prop->value) + 1;
        unittest(of_add_property(np, prop) == 0, "Adding a new property failed\n");
 
        /* Try to add an existing property - should fail */
        prop++;
        prop->name = "new-property";
        prop->value = "new-property-data-should-fail";
-       prop->length = strlen(prop->value);
+       prop->length = strlen(prop->value) + 1;
        unittest(of_add_property(np, prop) != 0,
                 "Adding an existing property should have failed\n");
 
        /* Try to modify an existing property - should pass */
        prop->value = "modify-property-data-should-pass";
-       prop->length = strlen(prop->value);
+       prop->length = strlen(prop->value) + 1;
        unittest(of_update_property(np, prop) == 0,
                 "Updating an existing property should have passed\n");
 
@@ -186,7 +186,7 @@ static void __init of_unittest_dynamic(void)
        prop++;
        prop->name = "modify-property";
        prop->value = "modify-missing-property-data-should-pass";
-       prop->length = strlen(prop->value);
+       prop->length = strlen(prop->value) + 1;
        unittest(of_update_property(np, prop) == 0,
                 "Updating a missing property should have passed\n");
 
index 5af34a2b0cd9a4c116f68fb73f39e6716f3cfcb3..1bb594fcfe12ca0ee9604df66e56daed74d288e3 100644 (file)
@@ -251,6 +251,9 @@ DTC_FLAGS += -Wno-unit_address_vs_reg \
        -Wno-unit_address_format \
        -Wno-avoid_unnecessary_addr_size \
        -Wno-alias_paths \
+       -Wno-graph_child_address \
+       -Wno-graph_port \
+       -Wno-unique_unit_address \
        -Wno-pci_device_reg
 endif
 
index 815eaf140ab5c0724a27df752d92a49402022e0b..a2cc1036c9155e86d65d9a8b8de41b00fb061c13 100644 (file)
@@ -255,7 +255,7 @@ static void check_duplicate_node_names(struct check *c, struct dt_info *dti,
                     child2;
                     child2 = child2->next_sibling)
                        if (streq(child->name, child2->name))
-                               FAIL(c, dti, node, "Duplicate node name");
+                               FAIL(c, dti, child2, "Duplicate node name");
 }
 ERROR(duplicate_node_names, check_duplicate_node_names, NULL);
 
@@ -317,6 +317,11 @@ static void check_unit_address_vs_reg(struct check *c, struct dt_info *dti,
        const char *unitname = get_unitname(node);
        struct property *prop = get_property(node, "reg");
 
+       if (get_subnode(node, "__overlay__")) {
+               /* HACK: Overlay fragments are a special case */
+               return;
+       }
+
        if (!prop) {
                prop = get_property(node, "ranges");
                if (prop && !prop->val.len)
@@ -579,6 +584,8 @@ static void fixup_phandle_references(struct check *c, struct dt_info *dti,
 
                        phandle = get_node_phandle(dt, refnode);
                        *((fdt32_t *)(prop->val.val + m->offset)) = cpu_to_fdt32(phandle);
+
+                       reference_node(refnode);
                }
        }
 }
@@ -609,11 +616,21 @@ static void fixup_path_references(struct check *c, struct dt_info *dti,
                        path = refnode->fullpath;
                        prop->val = data_insert_at_marker(prop->val, m, path,
                                                          strlen(path) + 1);
+
+                       reference_node(refnode);
                }
        }
 }
 ERROR(path_references, fixup_path_references, NULL, &duplicate_node_names);
 
+static void fixup_omit_unused_nodes(struct check *c, struct dt_info *dti,
+                                   struct node *node)
+{
+       if (node->omit_if_unused && !node->is_referenced)
+               delete_node(node);
+}
+ERROR(omit_unused_nodes, fixup_omit_unused_nodes, NULL, &phandle_references, &path_references);
+
 /*
  * Semantic checks
  */
@@ -1017,6 +1034,36 @@ static void check_avoid_unnecessary_addr_size(struct check *c, struct dt_info *d
 }
 WARNING(avoid_unnecessary_addr_size, check_avoid_unnecessary_addr_size, NULL, &avoid_default_addr_size);
 
+static void check_unique_unit_address(struct check *c, struct dt_info *dti,
+                                             struct node *node)
+{
+       struct node *childa;
+
+       if (node->addr_cells < 0 || node->size_cells < 0)
+               return;
+
+       if (!node->children)
+               return;
+
+       for_each_child(node, childa) {
+               struct node *childb;
+               const char *addr_a = get_unitname(childa);
+
+               if (!strlen(addr_a))
+                       continue;
+
+               for_each_child(node, childb) {
+                       const char *addr_b = get_unitname(childb);
+                       if (childa == childb)
+                               break;
+
+                       if (streq(addr_a, addr_b))
+                               FAIL(c, dti, childb, "duplicate unit-address (also used in node %s)", childa->fullpath);
+               }
+       }
+}
+WARNING(unique_unit_address, check_unique_unit_address, NULL, &avoid_default_addr_size);
+
 static void check_obsolete_chosen_interrupt_controller(struct check *c,
                                                       struct dt_info *dti,
                                                       struct node *node)
@@ -1357,6 +1404,152 @@ static void check_interrupts_property(struct check *c,
 }
 WARNING(interrupts_property, check_interrupts_property, &phandle_references);
 
+static const struct bus_type graph_port_bus = {
+       .name = "graph-port",
+};
+
+static const struct bus_type graph_ports_bus = {
+       .name = "graph-ports",
+};
+
+static void check_graph_nodes(struct check *c, struct dt_info *dti,
+                             struct node *node)
+{
+       struct node *child;
+
+       for_each_child(node, child) {
+               if (!(strprefixeq(child->name, child->basenamelen, "endpoint") ||
+                     get_property(child, "remote-endpoint")))
+                       continue;
+
+               node->bus = &graph_port_bus;
+
+               /* The parent of 'port' nodes can be either 'ports' or a device */
+               if (!node->parent->bus &&
+                   (streq(node->parent->name, "ports") || get_property(node, "reg")))
+                       node->parent->bus = &graph_ports_bus;
+
+               break;
+       }
+
+}
+WARNING(graph_nodes, check_graph_nodes, NULL);
+
+static void check_graph_child_address(struct check *c, struct dt_info *dti,
+                                     struct node *node)
+{
+       int cnt = 0;
+       struct node *child;
+
+       if (node->bus != &graph_ports_bus && node->bus != &graph_port_bus)
+               return;
+
+       for_each_child(node, child) {
+               struct property *prop = get_property(child, "reg");
+
+               /* No error if we have any non-zero unit address */
+               if (prop && propval_cell(prop) != 0)
+                       return;
+
+               cnt++;
+       }
+
+       if (cnt == 1 && node->addr_cells != -1)
+               FAIL(c, dti, node, "graph node has single child node '%s', #address-cells/#size-cells are not necessary",
+                    node->children->name);
+}
+WARNING(graph_child_address, check_graph_child_address, NULL, &graph_nodes);
+
+static void check_graph_reg(struct check *c, struct dt_info *dti,
+                           struct node *node)
+{
+       char unit_addr[9];
+       const char *unitname = get_unitname(node);
+       struct property *prop;
+
+       prop = get_property(node, "reg");
+       if (!prop || !unitname)
+               return;
+
+       if (!(prop->val.val && prop->val.len == sizeof(cell_t))) {
+               FAIL(c, dti, node, "graph node malformed 'reg' property");
+               return;
+       }
+
+       snprintf(unit_addr, sizeof(unit_addr), "%x", propval_cell(prop));
+       if (!streq(unitname, unit_addr))
+               FAIL(c, dti, node, "graph node unit address error, expected \"%s\"",
+                    unit_addr);
+
+       if (node->parent->addr_cells != 1)
+               FAIL_PROP(c, dti, node, get_property(node, "#address-cells"),
+                         "graph node '#address-cells' is %d, must be 1",
+                         node->parent->addr_cells);
+       if (node->parent->size_cells != 0)
+               FAIL_PROP(c, dti, node, get_property(node, "#size-cells"),
+                         "graph node '#size-cells' is %d, must be 0",
+                         node->parent->size_cells);
+}
+
+static void check_graph_port(struct check *c, struct dt_info *dti,
+                            struct node *node)
+{
+       if (node->bus != &graph_port_bus)
+               return;
+
+       if (!strprefixeq(node->name, node->basenamelen, "port"))
+               FAIL(c, dti, node, "graph port node name should be 'port'");
+
+       check_graph_reg(c, dti, node);
+}
+WARNING(graph_port, check_graph_port, NULL, &graph_nodes);
+
+static struct node *get_remote_endpoint(struct check *c, struct dt_info *dti,
+                                       struct node *endpoint)
+{
+       int phandle;
+       struct node *node;
+       struct property *prop;
+
+       prop = get_property(endpoint, "remote-endpoint");
+       if (!prop)
+               return NULL;
+
+       phandle = propval_cell(prop);
+       /* Give up if this is an overlay with external references */
+       if (phandle == 0 || phandle == -1)
+               return NULL;
+
+       node = get_node_by_phandle(dti->dt, phandle);
+       if (!node)
+               FAIL_PROP(c, dti, endpoint, prop, "graph phandle is not valid");
+
+       return node;
+}
+
+static void check_graph_endpoint(struct check *c, struct dt_info *dti,
+                                struct node *node)
+{
+       struct node *remote_node;
+
+       if (!node->parent || node->parent->bus != &graph_port_bus)
+               return;
+
+       if (!strprefixeq(node->name, node->basenamelen, "endpoint"))
+               FAIL(c, dti, node, "graph endpont node name should be 'endpoint'");
+
+       check_graph_reg(c, dti, node);
+
+       remote_node = get_remote_endpoint(c, dti, node);
+       if (!remote_node)
+               return;
+
+       if (get_remote_endpoint(c, dti, remote_node) != node)
+               FAIL(c, dti, node, "graph connection to node '%s' is not bidirectional",
+                    remote_node->fullpath);
+}
+WARNING(graph_endpoint, check_graph_endpoint, NULL, &graph_nodes);
+
 static struct check *check_table[] = {
        &duplicate_node_names, &duplicate_property_names,
        &node_name_chars, &node_name_format, &property_name_chars,
@@ -1366,6 +1559,7 @@ static struct check *check_table[] = {
 
        &explicit_phandles,
        &phandle_references, &path_references,
+       &omit_unused_nodes,
 
        &address_cells_is_cell, &size_cells_is_cell, &interrupt_cells_is_cell,
        &device_type_is_string, &model_is_string, &status_is_string,
@@ -1390,6 +1584,7 @@ static struct check *check_table[] = {
 
        &avoid_default_addr_size,
        &avoid_unnecessary_addr_size,
+       &unique_unit_address,
        &obsolete_chosen_interrupt_controller,
        &chosen_node_is_root, &chosen_node_bootargs, &chosen_node_stdout_path,
 
@@ -1416,6 +1611,8 @@ static struct check *check_table[] = {
 
        &alias_paths,
 
+       &graph_nodes, &graph_child_address, &graph_port, &graph_endpoint,
+
        &always_fail,
 };
 
index fd825ebba69cb25e160e057f53bef994970093fc..615b7ec6588f12bfab0a34159ff2e9319e80f615 100644 (file)
@@ -153,6 +153,13 @@ static void PRINTF(1, 2) lexical_error(const char *fmt, ...);
                        return DT_DEL_NODE;
                }
 
+<*>"/omit-if-no-ref/"  {
+                       DPRINT("Keyword: /omit-if-no-ref/\n");
+                       DPRINT("<PROPNODENAME>\n");
+                       BEGIN(PROPNODENAME);
+                       return DT_OMIT_NO_REF;
+               }
+
 <*>{LABEL}:    {
                        DPRINT("Label: %s\n", yytext);
                        yylval.labelref = xstrdup(yytext);
index 44af170abfeaca34a94217d0cf7519568e27b72a..011a5b25539a18f3882aaadbe61b228e391b00d7 100644 (file)
@@ -63,6 +63,7 @@ extern bool treesource_error;
 %token DT_BITS
 %token DT_DEL_PROP
 %token DT_DEL_NODE
+%token DT_OMIT_NO_REF
 %token <propnodename> DT_PROPNODENAME
 %token <integer> DT_LITERAL
 %token <integer> DT_CHAR_LITERAL
@@ -190,18 +191,18 @@ devicetree:
                }
        | devicetree DT_REF nodedef
                {
-                       struct node *target = get_node_by_ref($1, $2);
-
-                       if (target) {
-                               merge_nodes(target, $3);
+                       /*
+                        * We rely on the rule being always:
+                        *   versioninfo plugindecl memreserves devicetree
+                        * so $-1 is what we want (plugindecl)
+                        */
+                       if ($<flags>-1 & DTSF_PLUGIN) {
+                               add_orphan_node($1, $3, $2);
                        } else {
-                               /*
-                                * We rely on the rule being always:
-                                *   versioninfo plugindecl memreserves devicetree
-                                * so $-1 is what we want (plugindecl)
-                                */
-                               if ($<flags>-1 & DTSF_PLUGIN)
-                                       add_orphan_node($1, $3, $2);
+                               struct node *target = get_node_by_ref($1, $2);
+
+                               if (target)
+                                       merge_nodes(target, $3);
                                else
                                        ERROR(&@2, "Label or path %s not found", $2);
                        }
@@ -217,6 +218,18 @@ devicetree:
                                ERROR(&@3, "Label or path %s not found", $3);
 
 
+                       $$ = $1;
+               }
+       | devicetree DT_OMIT_NO_REF DT_REF ';'
+               {
+                       struct node *target = get_node_by_ref($1, $3);
+
+                       if (target)
+                               omit_node_if_unused(target);
+                       else
+                               ERROR(&@3, "Label or path %s not found", $3);
+
+
                        $$ = $1;
                }
        ;
@@ -523,6 +536,10 @@ subnode:
                {
                        $$ = name_node(build_node_delete(), $2);
                }
+       | DT_OMIT_NO_REF subnode
+               {
+                       $$ = omit_node_if_unused($2);
+               }
        | DT_LABEL subnode
                {
                        add_label(&$2->labels, $1);
index 3b18a42b866e73323c0335997a79322f385312ed..6d667701ab6aa9027510b57eedc3f12ed5d9f8d5 100644 (file)
@@ -168,6 +168,8 @@ struct node {
 
        struct label *labels;
        const struct bus_type *bus;
+
+       bool omit_if_unused, is_referenced;
 };
 
 #define for_each_label_withdel(l0, l) \
@@ -202,6 +204,8 @@ struct property *reverse_properties(struct property *first);
 struct node *build_node(struct property *proplist, struct node *children);
 struct node *build_node_delete(void);
 struct node *name_node(struct node *node, char *name);
+struct node *omit_node_if_unused(struct node *node);
+struct node *reference_node(struct node *node);
 struct node *chain_node(struct node *first, struct node *list);
 struct node *merge_nodes(struct node *old_node, struct node *new_node);
 struct node *add_orphan_node(struct node *old_node, struct node *new_node, char *ref);
index 57b7db2ed1534873ea8f382c958d19038ba86916..6e4c367f54b3a8de0289d9677519a81b63ef5aa4 100644 (file)
@@ -134,6 +134,20 @@ struct node *name_node(struct node *node, char *name)
        return node;
 }
 
+struct node *omit_node_if_unused(struct node *node)
+{
+       node->omit_if_unused = 1;
+
+       return node;
+}
+
+struct node *reference_node(struct node *node)
+{
+       node->is_referenced = 1;
+
+       return node;
+}
+
 struct node *merge_nodes(struct node *old_node, struct node *new_node)
 {
        struct property *new_prop, *old_prop;
@@ -224,10 +238,16 @@ struct node * add_orphan_node(struct node *dt, struct node *new_node, char *ref)
        struct data d = empty_data;
        char *name;
 
-       d = data_add_marker(d, REF_PHANDLE, ref);
-       d = data_append_integer(d, 0xffffffff, 32);
+       if (ref[0] == '/') {
+               d = data_append_data(d, ref, strlen(ref) + 1);
 
-       p = build_property("target", d);
+               p = build_property("target-path", d);
+       } else {
+               d = data_add_marker(d, REF_PHANDLE, ref);
+               d = data_append_integer(d, 0xffffffff, 32);
+
+               p = build_property("target", d);
+       }
 
        xasprintf(&name, "fragment@%u",
                        next_orphan_fragment++);
index ad87849e333bc6e450a1b27685fd10bfe065c241..b00f14ff7a17caaf0ed92d5823a3e398386a2d9f 100644 (file)
@@ -1 +1 @@
-#define DTC_VERSION "DTC 1.4.6-gaadd0b65"
+#define DTC_VERSION "DTC 1.4.6-g84e414b0"