drm/amd/powerplay: delete SMUM_WRITE_VFPF_INDIRECT_FIELD
authorRex Zhu <Rex.Zhu@amd.com>
Wed, 20 Sep 2017 09:19:58 +0000 (17:19 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 26 Sep 2017 19:14:33 +0000 (15:14 -0400)
repeated defining in hwmgr.h

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/inc/smumgr.h
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c

index 4433e00..b1b2104 100644 (file)
@@ -185,10 +185,4 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
                SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
                        reg, field)
 
                SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
                        reg, field)
 
-
-#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
-               cgs_write_ind_register(device, port, ix##reg, \
-                       SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
-                       reg, field, fieldval))
-
 #endif
 #endif
index 0b7cb3b..ee89fd7 100644 (file)
@@ -66,7 +66,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
        /* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
                RCU_UC_EVENTS, boot_seq_done, 0); */
 
        /* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
                RCU_UC_EVENTS, boot_seq_done, 0); */
 
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
        result = smu7_upload_smu_firmware_image(hwmgr);
                        SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
        result = smu7_upload_smu_firmware_image(hwmgr);
@@ -77,11 +77,11 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixSMU_STATUS, 0);
 
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                        ixSMU_STATUS, 0);
 
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
        /* De-assert reset */
                        SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
        /* De-assert reset */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for ROM firmware to initialize interrupt hendler */
                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for ROM firmware to initialize interrupt hendler */
@@ -89,7 +89,7 @@ static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
                        SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
 
        /* Set SMU Auto Start */
                        SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
 
        /* Set SMU Auto Start */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SMU_INPUT_DATA, AUTO_START, 1);
 
        /* Clear firmware interrupt enable flag */
                        SMU_INPUT_DATA, AUTO_START, 1);
 
        /* Clear firmware interrupt enable flag */
@@ -134,7 +134,7 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
                        ixFIRMWARE_FLAGS, 0);
 
        /* Assert reset */
                        ixFIRMWARE_FLAGS, 0);
 
        /* Assert reset */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
        result = smu7_upload_smu_firmware_image(hwmgr);
                        SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
        result = smu7_upload_smu_firmware_image(hwmgr);
@@ -145,11 +145,11 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
        smu7_program_jump_on_start(hwmgr);
 
        /* Enable clock */
        smu7_program_jump_on_start(hwmgr);
 
        /* Enable clock */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
        /* De-assert reset */
                        SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
        /* De-assert reset */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */
                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */
index fd4ccd0..eefa13b 100644 (file)
@@ -223,7 +223,7 @@ static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
        /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
 
        /* Assert reset */
        /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
 
        /* Assert reset */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
        result = smu7_upload_smu_firmware_image(hwmgr);
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
        result = smu7_upload_smu_firmware_image(hwmgr);
@@ -233,11 +233,11 @@ static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
        /* Clear status */
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
 
        /* Clear status */
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
 
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                                        SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
        /* De-assert reset */
                                        SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
        /* De-assert reset */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
 
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
 
@@ -258,10 +258,10 @@ static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
 
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
 
 
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
 
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */
@@ -278,11 +278,11 @@ static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
        PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
 
        /* Clear firmware interrupt enable flag */
        PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
 
        /* Clear firmware interrupt enable flag */
-       /* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
+       /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                                ixFIRMWARE_FLAGS, 0);
 
        cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
                                ixFIRMWARE_FLAGS, 0);
 
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                                        SMC_SYSCON_RESET_CNTL,
                                        rst_reg, 1);
 
                                        SMC_SYSCON_RESET_CNTL,
                                        rst_reg, 1);
 
@@ -293,10 +293,10 @@ static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
        /* Set smc instruct start point at 0x0 */
        smu7_program_jump_on_start(hwmgr);
 
        /* Set smc instruct start point at 0x0 */
        smu7_program_jump_on_start(hwmgr);
 
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                                        SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
                                        SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */
                                        SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */
index 6a9b3cf..7ffcada 100644 (file)
@@ -42,7 +42,7 @@ static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
        int result;
 
        /* Assert reset */
        int result;
 
        /* Assert reset */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
        result = smu7_upload_smu_firmware_image(hwmgr);
                SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
        result = smu7_upload_smu_firmware_image(hwmgr);
@@ -54,15 +54,15 @@ static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
                ixSMU_STATUS, 0);
 
        /* Enable clock */
                ixSMU_STATUS, 0);
 
        /* Enable clock */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
        /* De-assert reset */
                SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
        /* De-assert reset */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Set SMU Auto Start */
                SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Set SMU Auto Start */
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                SMU_INPUT_DATA, AUTO_START, 1);
 
        /* Clear firmware interrupt enable flag */
                SMU_INPUT_DATA, AUTO_START, 1);
 
        /* Clear firmware interrupt enable flag */
@@ -109,7 +109,7 @@ static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
                ixFIRMWARE_FLAGS, 0);
 
 
                ixFIRMWARE_FLAGS, 0);
 
 
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
        result = smu7_upload_smu_firmware_image(hwmgr);
                SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 
        result = smu7_upload_smu_firmware_image(hwmgr);
@@ -121,11 +121,11 @@ static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
        smu7_program_jump_on_start(hwmgr);
 
 
        smu7_program_jump_on_start(hwmgr);
 
 
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
        /*De-assert reset*/
                SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 
        /*De-assert reset*/
-       SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+       PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
                SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */
                SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 
        /* Wait for firmware to initialize */