Merge tag 'hisi-arm64-dt-for-4.18v2' of git://github.com/hisilicon/linux-hisi into...
authorOlof Johansson <olof@lixom.net>
Fri, 25 May 2018 11:47:13 +0000 (04:47 -0700)
committerOlof Johansson <olof@lixom.net>
Fri, 25 May 2018 11:47:13 +0000 (04:47 -0700)
ARM64: DT: Hisilicon SoC DT updates for 4.18v2

- Add mailbox, stub clock, CPU frequency scaling, thermal cooling
  management and pcie msi interruption support for hi3660
- Add LPC support for hip06 and hip07
- Add PCIe, usb and emmc support for hi3798cv200

* tag 'hisi-arm64-dt-for-4.18v2' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hi3798cv200: enable emmc support for poplar board
  arm64: dts: hi3798cv200: enable usb2 support for poplar board
  arm64: dts: hi3798cv200: enable PCIe support for poplar board
  arm64: dts: hisi: Enable Hisi LPC node for hip07
  arm64: dts: hisi: Enable Hisi LPC node for hip06
  arm64: dts: hi3660: Add pcie msi interrupt attribute
  arm64: dts: hi3660: Add thermal cooling management
  arm64: dts: hi3660: Add CPU frequency scaling support
  arm64: dts: hi3660: Add stub clock node
  arm64: dts: hi3660: Add mailbox node

Signed-off-by: Olof Johansson <olof@lixom.net>
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
arch/arm64/boot/dts/hisilicon/hip06-d03.dts
arch/arm64/boot/dts/hisilicon/hip06.dtsi
arch/arm64/boot/dts/hisilicon/hip07-d05.dts
arch/arm64/boot/dts/hisilicon/hip07.dtsi
arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi [new file with mode: 0644]

index ec3eb8e33a3a528e1a78d2138762acf4aaec3cd2..8d477dcbfa5822c4b037cee7e187bd27ee045f04 100644 (file)
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/hi3660-clock.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
        compatible = "hisilicon,hi3660";
                        next-level-cache = <&A53_L2>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
                        capacity-dmips-mhz = <592>;
+                       clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+                       operating-points-v2 = <&cluster0_opp>;
+                       #cooling-cells = <2>;
+                       dynamic-power-coefficient = <110>;
                };
 
                cpu1: cpu@1 {
@@ -72,6 +77,8 @@
                        next-level-cache = <&A53_L2>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
                        capacity-dmips-mhz = <592>;
+                       clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu2: cpu@2 {
@@ -82,6 +89,8 @@
                        next-level-cache = <&A53_L2>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
                        capacity-dmips-mhz = <592>;
+                       clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu3: cpu@3 {
                        next-level-cache = <&A53_L2>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
                        capacity-dmips-mhz = <592>;
+                       clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu4: cpu@100 {
                        next-level-cache = <&A73_L2>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
                        capacity-dmips-mhz = <1024>;
+                       clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+                       operating-points-v2 = <&cluster1_opp>;
+                       #cooling-cells = <2>;
+                       dynamic-power-coefficient = <550>;
                };
 
                cpu5: cpu@101 {
                        next-level-cache = <&A73_L2>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
                        capacity-dmips-mhz = <1024>;
+                       clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                cpu6: cpu@102 {
                        next-level-cache = <&A73_L2>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
                        capacity-dmips-mhz = <1024>;
+                       clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                cpu7: cpu@103 {
                        next-level-cache = <&A73_L2>;
                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
                        capacity-dmips-mhz = <1024>;
+                       clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                idle-states {
                };
        };
 
+       cluster0_opp: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp00 {
+                       opp-hz = /bits/ 64 <533000000>;
+                       opp-microvolt = <700000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp01 {
+                       opp-hz = /bits/ 64 <999000000>;
+                       opp-microvolt = <800000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp02 {
+                       opp-hz = /bits/ 64 <1402000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp03 {
+                       opp-hz = /bits/ 64 <1709000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp04 {
+                       opp-hz = /bits/ 64 <1844000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <300000>;
+               };
+       };
+
+       cluster1_opp: opp_table1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp10 {
+                       opp-hz = /bits/ 64 <903000000>;
+                       opp-microvolt = <700000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp11 {
+                       opp-hz = /bits/ 64 <1421000000>;
+                       opp-microvolt = <800000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp12 {
+                       opp-hz = /bits/ 64 <1805000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp13 {
+                       opp-hz = /bits/ 64 <2112000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <300000>;
+               };
+
+               opp14 {
+                       opp-hz = /bits/ 64 <2362000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <300000>;
+               };
+       };
+
        gic: interrupt-controller@e82b0000 {
                compatible = "arm,gic-400";
                reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
                        #reset-cells = <2>;
                };
 
+               mailbox: mailbox@e896b000 {
+                       compatible = "hisilicon,hi3660-mbox";
+                       reg = <0x0 0xe896b000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+                       #mbox-cells = <3>;
+               };
+
+               stub_clock: stub_clock@e896b500 {
+                       compatible = "hisilicon,hi3660-stub-clk";
+                       reg = <0x0 0xe896b500 0x0 0x0100>;
+                       #clock-cells = <1>;
+                       mboxes = <&mailbox 13 3 0>;
+               };
+
                dual_timer0: timer@fff14000 {
                        compatible = "arm,sp804", "arm,primecell";
                        reg = <0x0 0xfff14000 0x0 0x1000>;
                                  0x0 0x02000000>;
                        num-lanes = <1>;
                        #interrupt-cells = <1>;
+                       interrupts = <0 283 4>;
+                       interrupt-names = "msi";
                        interrupt-map-mask = <0xf800 0 0 7>;
                        interrupt-map = <0x0 0 0 1
                                         &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
                        interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
                        #thermal-sensor-cells = <1>;
                };
+
+               thermal-zones {
+
+                       cls0: cls0 {
+                               polling-delay = <1000>;
+                               polling-delay-passive = <100>;
+                               sustainable-power = <4500>;
+
+                               /* sensor ID */
+                               thermal-sensors = <&tsensor 1>;
+
+                               trips {
+                                       threshold: trip-point@0 {
+                                               temperature = <65000>;
+                                               hysteresis = <1000>;
+                                               type = "passive";
+                                       };
+
+                                       target: trip-point@1 {
+                                               temperature = <75000>;
+                                               hysteresis = <1000>;
+                                               type = "passive";
+                                       };
+                               };
+
+                               cooling-maps {
+                                       map0 {
+                                               trip = <&target>;
+                                               contribution = <1024>;
+                                               cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       };
+                                       map1 {
+                                               trip = <&target>;
+                                               contribution = <512>;
+                                               cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       };
+                               };
+                       };
+               };
        };
 };
index 4d5d644abb126a9c4bc7e602b04ae82d80c050c0..d30f6eb8a5ee2f67fd3708f072224607f87d32fa 100644 (file)
@@ -11,6 +11,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include "hi3798cv200.dtsi"
+#include "poplar-pinctrl.dtsi"
 
 / {
        model = "HiSilicon Poplar Development Board";
                        default-state = "off";
                };
        };
+
+       reg_pcie: regulator-pcie {
+               compatible = "regulator-fixed";
+               regulator-name = "3V3_PCIE0";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio6 7 0>;
+               enable-active-high;
+       };
+};
+
+&ehci {
+       status = "okay";
+};
+
+&emmc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
+                    &emmc_pins_3 &emmc_pins_4>;
+       fifo-depth = <256>;
+       clock-frequency = <200000000>;
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       non-removable;
+       bus-width = <8>;
+       status = "okay";
 };
 
 &gmac1 {
        status = "okay";
 };
 
+&ohci {
+       status = "okay";
+};
+
+&pcie {
+       reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+       vpcie-supply = <&reg_pcie>;
+       status = "okay";
+};
+
 &sd0 {
        bus-width = <4>;
        cap-sd-highspeed;
index 962bd79139e4804ee9dc4ca18cabe5775926a7c6..7c0fddd7c8cfe97c1e8e26d77379ba8bdea8a0bc 100644 (file)
@@ -8,7 +8,9 @@
  */
 
 #include <dt-bindings/clock/histb-clock.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/reset/ti-syscon.h>
 
 / {
                        #reset-cells = <2>;
                };
 
+               perictrl: peripheral-controller@8a20000 {
+                       compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
+                                    "simple-mfd";
+                       reg = <0x8a20000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x8a20000 0x1000>;
+
+                       usb2_phy1: usb2-phy@120 {
+                               compatible = "hisilicon,hi3798cv200-usb2-phy";
+                               reg = <0x120 0x4>;
+                               clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+                               resets = <&crg 0xbc 4>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               usb2_phy1_port0: phy@0 {
+                                       reg = <0>;
+                                       #phy-cells = <0>;
+                                       resets = <&crg 0xbc 8>;
+                               };
+
+                               usb2_phy1_port1: phy@1 {
+                                       reg = <1>;
+                                       #phy-cells = <0>;
+                                       resets = <&crg 0xbc 9>;
+                               };
+                       };
+
+                       usb2_phy2: usb2-phy@124 {
+                               compatible = "hisilicon,hi3798cv200-usb2-phy";
+                               reg = <0x124 0x4>;
+                               clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
+                               resets = <&crg 0xbc 6>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               usb2_phy2_port0: phy@0 {
+                                       reg = <0>;
+                                       #phy-cells = <0>;
+                                       resets = <&crg 0xbc 10>;
+                               };
+                       };
+
+                       combphy0: phy@850 {
+                               compatible = "hisilicon,hi3798cv200-combphy";
+                               reg = <0x850 0x8>;
+                               #phy-cells = <1>;
+                               clocks = <&crg HISTB_COMBPHY0_CLK>;
+                               resets = <&crg 0x188 4>;
+                               assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
+                               assigned-clock-rates = <100000000>;
+                               hisilicon,fixed-mode = <PHY_TYPE_USB3>;
+                       };
+
+                       combphy1: phy@858 {
+                               compatible = "hisilicon,hi3798cv200-combphy";
+                               reg = <0x858 0x8>;
+                               #phy-cells = <1>;
+                               clocks = <&crg HISTB_COMBPHY1_CLK>;
+                               resets = <&crg 0x188 12>;
+                               assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
+                               assigned-clock-rates = <100000000>;
+                               hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
+                       };
+               };
+
+               pmx0: pinconf@8a21000 {
+                       compatible = "pinconf-single";
+                       reg = <0x8a21000 0x180>;
+                       pinctrl-single,register-width = <32>;
+                       pinctrl-single,function-mask = <7>;
+                       pinctrl-single,gpio-range = <
+                               &range 0  8 2  /* GPIO 0 */
+                               &range 8  1 0  /* GPIO 1 */
+                               &range 9  4 2
+                               &range 13 1 0
+                               &range 14 1 1
+                               &range 15 1 0
+                               &range 16 5 0  /* GPIO 2 */
+                               &range 21 3 1
+                               &range 24 4 1  /* GPIO 3 */
+                               &range 28 2 2
+                               &range 86 1 1
+                               &range 87 1 0
+                               &range 30 4 2  /* GPIO 4 */
+                               &range 34 3 0
+                               &range 37 1 2
+                               &range 38 3 2  /* GPIO 6 */
+                               &range 41 5 0
+                               &range 46 8 1  /* GPIO 7 */
+                               &range 54 8 1  /* GPIO 8 */
+                               &range 64 7 1  /* GPIO 9 */
+                               &range 71 1 0
+                               &range 72 6 1  /* GPIO 10 */
+                               &range 78 1 0
+                               &range 79 1 1
+                               &range 80 6 1  /* GPIO 11 */
+                               &range 70 2 1
+                               &range 88 8 0  /* GPIO 12 */
+                       >;
+
+                       range: gpio-range {
+                               #pinctrl-single,gpio-range-cells = <3>;
+                       };
+               };
+
                uart0: serial@8b00000 {
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x8b00000 0x1000>;
                };
 
                emmc: mmc@9830000 {
-                       compatible = "snps,dw-mshc";
+                       compatible = "hisilicon,hi3798cv200-dw-mshc";
                        reg = <0x9830000 0x10000>;
                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&crg HISTB_MMC_CIU_CLK>,
-                                <&crg HISTB_MMC_BIU_CLK>;
-                       clock-names = "ciu", "biu";
+                                <&crg HISTB_MMC_BIU_CLK>,
+                                <&crg HISTB_MMC_SAMPLE_CLK>,
+                                <&crg HISTB_MMC_DRV_CLK>;
+                       clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
+                       resets = <&crg 0xa0 4>;
+                       reset-names = "reset";
+                       status = "disabled";
                };
 
                gpio0: gpio@8b20000 {
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <&pmx0 0 0 8>;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <
+                               &pmx0 0 8 1
+                               &pmx0 1 9 4
+                               &pmx0 5 13 1
+                               &pmx0 6 14 1
+                               &pmx0 7 15 1
+                       >;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <
+                               &pmx0 0 24 4
+                               &pmx0 4 28 2
+                               &pmx0 6 86 1
+                               &pmx0 7 87 1
+                       >;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <&pmx0 0 46 8>;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <&pmx0 0 54 8>;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
+                       gpio-ranges = <&pmx0 0 88 8>;
                        clocks = <&crg HISTB_APB_CLK>;
                        clock-names = "apb_pclk";
                        status = "disabled";
                        clocks = <&sysctrl HISTB_IR_CLK>;
                        status = "disabled";
                };
+
+               pcie: pcie@9860000 {
+                       compatible = "hisilicon,hi3798cv200-pcie";
+                       reg = <0x9860000 0x1000>,
+                             <0x0 0x2000>,
+                             <0x2000000 0x01000000>;
+                       reg-names = "control", "rc-dbi", "config";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0 15>;
+                       num-lanes = <1>;
+                       ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
+                                 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
+                       interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg HISTB_PCIE_AUX_CLK>,
+                                <&crg HISTB_PCIE_PIPE_CLK>,
+                                <&crg HISTB_PCIE_SYS_CLK>,
+                                <&crg HISTB_PCIE_BUS_CLK>;
+                       clock-names = "aux", "pipe", "sys", "bus";
+                       resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
+                       reset-names = "soft", "sys", "bus";
+                       phys = <&combphy1 PHY_TYPE_PCIE>;
+                       phy-names = "phy";
+                       status = "disabled";
+               };
+
+               ohci: ohci@9880000 {
+                       compatible = "generic-ohci";
+                       reg = <0x9880000 0x10000>;
+                       interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg HISTB_USB2_BUS_CLK>,
+                                <&crg HISTB_USB2_12M_CLK>,
+                                <&crg HISTB_USB2_48M_CLK>;
+                       clock-names = "bus", "clk12", "clk48";
+                       resets = <&crg 0xb8 12>;
+                       reset-names = "bus";
+                       phys = <&usb2_phy1_port0>;
+                       phy-names = "usb";
+                       status = "disabled";
+               };
+
+               ehci: ehci@9890000 {
+                       compatible = "generic-ehci";
+                       reg = <0x9890000 0x10000>;
+                       interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg HISTB_USB2_BUS_CLK>,
+                                <&crg HISTB_USB2_PHY_CLK>,
+                                <&crg HISTB_USB2_UTMI_CLK>;
+                       clock-names = "bus", "phy", "utmi";
+                       resets = <&crg 0xb8 12>,
+                                <&crg 0xb8 16>,
+                                <&crg 0xb8 13>;
+                       reset-names = "bus", "phy", "utmi";
+                       phys = <&usb2_phy1_port0>;
+                       phy-names = "usb";
+                       status = "disabled";
+               };
        };
 };
index 9af633021a42a62460bed98a66ba63c244123177..a95c6f5619bfed8ded000442627bad2383fde3ed 100644 (file)
        chosen { };
 };
 
+&ipmi0 {
+       status = "ok";
+};
+
+&uart0 {
+       status = "ok";
+};
+
 &eth0 {
        status = "ok";
 };
index 35202ebe62a744decfad6b40823620d31ee300f0..d78a6a755d03dfb1c2ac6ffacd1a990fec9fa7b8 100644 (file)
                #size-cells = <2>;
                ranges;
 
+               isa@a01b0000 {
+                       compatible = "hisilicon,hip06-lpc";
+                       #size-cells = <1>;
+                       #address-cells = <2>;
+                       reg = <0x0 0xa01b0000 0x0 0x1000>;
+
+                       ipmi0: bt@e4 {
+                               compatible = "ipmi-bt";
+                               device_type = "ipmi";
+                               reg = <0x01 0xe4 0x04>;
+                               status = "disabled";
+                       };
+
+                       uart0: lpc-uart@2f8 {
+                               compatible = "ns16550a";
+                               clock-frequency = <1843200>;
+                               reg = <0x01 0x2f8 0x08>;
+                               status = "disabled";
+                       };
+               };
+
                refclk: refclk {
                        compatible = "fixed-clock";
                        clock-frequency = <50000000>;
index fe7c16c3602593a9b572fef58bba730dbd1a9c73..21147e8e3f94410f3f5e1634302cd7b296f8ff3c 100644 (file)
        status = "ok";
 };
 
+&ipmi0 {
+       status = "ok";
+};
+
 &usb_ohci {
        status = "ok";
 };
index 0600a6a84ab7d1a2c72b792ce1693e14daecf55a..9c10030a07f87e934afc86138cfa1bee0e0d8c82 100644 (file)
                #size-cells = <2>;
                ranges;
 
+               isa@a01b0000 {
+                       compatible = "hisilicon,hip07-lpc";
+                       #size-cells = <1>;
+                       #address-cells = <2>;
+                       reg = <0x0 0xa01b0000 0x0 0x1000>;
+
+                       ipmi0: bt@e4 {
+                               compatible = "ipmi-bt";
+                               device_type = "ipmi";
+                               reg = <0x01 0xe4 0x04>;
+                               status = "disabled";
+                       };
+               };
+
                uart0: uart@602b0000 {
                        compatible = "arm,sbsa-uart";
                        reg = <0x0 0x602b0000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi
new file mode 100644 (file)
index 0000000..7bb19e4
--- /dev/null
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl dts file for HiSilicon Poplar board
+ *
+ * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/hisi.h>
+
+/* value, enable bits, disable bits, mask */
+#define PINCTRL_PULLDOWN(value, enable, disable, mask) \
+       (value << 13) (enable << 13) (disable << 13) (mask << 13)
+#define PINCTRL_PULLUP(value, enable, disable, mask) \
+       (value << 12) (enable << 12) (disable << 12) (mask << 12)
+#define PINCTRL_SLEW_RATE(value, mask)   (value << 8) (mask << 8)
+#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4)
+
+&pmx0 {
+       emmc_pins_1: emmc-pins-1 {
+               pinctrl-single,pins = <
+                       0x000 MUX_M2
+                       0x004 MUX_M2
+                       0x008 MUX_M2
+                       0x00c MUX_M2
+                       0x010 MUX_M2
+                       0x014 MUX_M2
+                       0x018 MUX_M2
+                       0x01c MUX_M2
+                       0x024 MUX_M2
+               >;
+               pinctrl-single,bias-pulldown = <
+                       PINCTRL_PULLDOWN(0, 1, 0, 1)
+               >;
+               pinctrl-single,bias-pullup = <
+                       PINCTRL_PULLUP(0, 1, 0, 1)
+               >;
+               pinctrl-single,slew-rate = <
+                       PINCTRL_SLEW_RATE(1, 1)
+               >;
+               pinctrl-single,drive-strength = <
+                       PINCTRL_DRV_STRENGTH(0xb, 0xf)
+               >;
+       };
+
+       emmc_pins_2: emmc-pins-2 {
+               pinctrl-single,pins = <
+                       0x028 MUX_M2
+               >;
+               pinctrl-single,bias-pulldown = <
+                       PINCTRL_PULLDOWN(0, 1, 0, 1)
+               >;
+               pinctrl-single,bias-pullup = <
+                       PINCTRL_PULLUP(0, 1, 0, 1)
+               >;
+               pinctrl-single,slew-rate = <
+                       PINCTRL_SLEW_RATE(1, 1)
+               >;
+               pinctrl-single,drive-strength = <
+                       PINCTRL_DRV_STRENGTH(0x9, 0xf)
+               >;
+       };
+
+       emmc_pins_3: emmc-pins-3 {
+               pinctrl-single,pins = <
+                       0x02c MUX_M2
+               >;
+               pinctrl-single,bias-pulldown = <
+                       PINCTRL_PULLDOWN(0, 1, 0, 1)
+               >;
+               pinctrl-single,bias-pullup = <
+                       PINCTRL_PULLUP(0, 1, 0, 1)
+               >;
+               pinctrl-single,slew-rate = <
+                       PINCTRL_SLEW_RATE(1, 1)
+               >;
+               pinctrl-single,drive-strength = <
+                       PINCTRL_DRV_STRENGTH(3, 3)
+               >;
+       };
+
+       emmc_pins_4: emmc-pins-4 {
+               pinctrl-single,pins = <
+                       0x030 MUX_M2
+               >;
+               pinctrl-single,bias-pulldown = <
+                       PINCTRL_PULLDOWN(1, 1, 0, 1)
+               >;
+               pinctrl-single,bias-pullup = <
+                       PINCTRL_PULLUP(0, 1, 0, 1)
+               >;
+               pinctrl-single,slew-rate = <
+                       PINCTRL_SLEW_RATE(1, 1)
+               >;
+               pinctrl-single,drive-strength = <
+                       PINCTRL_DRV_STRENGTH(3, 3)
+               >;
+       };
+};