Merge tag 'v4.21-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorOlof Johansson <olof@lixom.net>
Fri, 30 Nov 2018 23:04:01 +0000 (15:04 -0800)
committerOlof Johansson <olof@lixom.net>
Fri, 30 Nov 2018 23:04:01 +0000 (15:04 -0800)
New dts for Gru-Scarlet (tablet device), default backlight brightness
for all Gru devices, rk3399 spi dma properties, some improvements for
the rk3399-sapphire board (fan, chosen, backlight), hs200 mode for the
emmc on the rock64 and declaring all cpu cores in the cooling maps
instead of just cpu0.

* tag 'v4.21-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: Add all CPUs in cooling maps
  arm64: dts: rockchip: add Gru Scarlet devicetrees
  arm64: dts: rockchip: move backlight from rk3399 sapphire to excavator
  arm64: dts: rockchip: Use default brightness table for rk3399-gru
  arm64: dts: rockchip: add chosen node on rk3399-sapphire
  arm64: dts: rockchip: enable HS200 for eMMC on rock64
  arm64: dts: rockchip: add fan on rk3399-sapphire board
  arm64: dts: rockchip: add rk3399 SPI DMAs

Signed-off-by: Olof Johansson <olof@lixom.net>
13 files changed:
Documentation/devicetree/bindings/arm/rockchip.txt
arch/arm64/boot/dts/rockchip/Makefile
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
arch/arm64/boot/dts/rockchip/rk3328.dtsi
arch/arm64/boot/dts/rockchip/rk3368.dtsi
arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts [new file with mode: 0644]
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts [new file with mode: 0644]
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
arch/arm64/boot/dts/rockchip/rk3399.dtsi

index 0cc71236d639c5b0ee234ec3bd960ab732fa7071..7ce7382fedd844bf9060b4a16ededba2d2eedc47 100644 (file)
@@ -152,6 +152,40 @@ Rockchip platforms device tree bindings
       - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
                     "google,veyron", "rockchip,rk3288";
 
+- Google Scarlet - with display from Kingdisplay
+    Required root node properties:
+      - compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15",
+                    "google,scarlet-rev14-sku7", "google,scarlet-rev14",
+                    "google,scarlet-rev13-sku7", "google,scarlet-rev13",
+                    "google,scarlet-rev12-sku7", "google,scarlet-rev12",
+                    "google,scarlet-rev11-sku7", "google,scarlet-rev11",
+                    "google,scarlet-rev10-sku7", "google,scarlet-rev10",
+                    "google,scarlet-rev9-sku7",  "google,scarlet-rev9",
+                    "google,scarlet-rev8-sku7",  "google,scarlet-rev8",
+                    "google,scarlet-rev7-sku7",  "google,scarlet-rev7",
+                    "google,scarlet-rev6-sku7",  "google,scarlet-rev6",
+                    "google,scarlet-rev5-sku7",  "google,scarlet-rev5",
+                    "google,scarlet-rev4-sku7",  "google,scarlet-rev4",
+                    "google,scarlet-rev3-sku7",  "google,scarlet-rev3",
+                    "google,scarlet", "google,gru", "rockchip,rk3399";
+
+- Google Scarlet - with display from Innolux
+    Required root node properties:
+      - compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15",
+                    "google,scarlet-rev14-sku6", "google,scarlet-rev14",
+                    "google,scarlet-rev13-sku6", "google,scarlet-rev13",
+                    "google,scarlet-rev12-sku6", "google,scarlet-rev12",
+                    "google,scarlet-rev11-sku6", "google,scarlet-rev11",
+                    "google,scarlet-rev10-sku6", "google,scarlet-rev10",
+                    "google,scarlet-rev9-sku6",  "google,scarlet-rev9",
+                    "google,scarlet-rev8-sku6",  "google,scarlet-rev8",
+                    "google,scarlet-rev7-sku6",  "google,scarlet-rev7",
+                    "google,scarlet-rev6-sku6",  "google,scarlet-rev6",
+                    "google,scarlet-rev5-sku6",  "google,scarlet-rev5",
+                    "google,scarlet-rev4-sku6",  "google,scarlet-rev4",
+                    "google,scarlet", "google,gru", "rockchip,rk3399";
+
+
 - Google Speedy (Asus C201 Chromebook):
     Required root node properties:
       - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
index 49042c47787031de279376e06d78646d2b812824..de0c406c20cc57a590570d04ad0f5323963c46eb 100644 (file)
@@ -14,6 +14,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
index dc20145dd393d93d308f7f2f3abab84b6313343b..bd937d68ca3bdb99e378c069d8a9b388ec46a516 100644 (file)
 &emmc {
        bus-width = <8>;
        cap-mmc-highspeed;
+       mmc-hs200-1_8v;
        non-removable;
        pinctrl-names = "default";
        pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
index e1a33dd981e0d2c1f93c0e333de0910fdbcb4fdd..ecd7f19c3542f740c45f5d3f4c05b314684361e1 100644 (file)
                        cooling-maps {
                                map0 {
                                        trip = <&target>;
-                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                        contribution = <4096>;
                                };
                        };
index 9c24de1ba43c56b70d0a29d063ec78324a764340..7014d10b954cf121632868f73d67d26afcd55c5d 100644 (file)
                                map0 {
                                        trip = <&cpu_alert0>;
                                        cooling-device =
-                                       <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                                map1 {
                                        trip = <&cpu_alert1>;
                                        cooling-device =
-                                       <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };
                                map0 {
                                        trip = <&gpu_alert0>;
                                        cooling-device =
-                                       <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };
index ff81dfda3b9524885956a20e7229da1c70ddf9ba..c400be64170eb17491f1d57dd7cabd6245f65245 100644 (file)
 
        backlight: backlight {
                compatible = "pwm-backlight";
-               brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
-                                    17 18 19 20 21 22 23 24 25 26 27 28 29 30
-                                    31 32 33 34 35 36 37 38 39 40 41 42 43 44
-                                    45 46 47 48 49 50 51 52 53 54 55 56 57 58
-                                    59 60 61 62 63 64 65 66 67 68 69 70 71 72
-                                    73 74 75 76 77 78 79 80 81 82 83 84 85 86
-                                    87 88 89 90 91 92 93 94 95 96 97 98 99 100>;
-               default-brightness-level = <51>;
                enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
                power-supply = <&pp3300_disp>;
                pinctrl-names = "default";
index 2cc7c47d6a85d79312a519dd0a0c02964f9223ff..81e73103fa788605471679fd1b0868f50822c4f8 100644 (file)
                        map0 {
                                trip = <&ppvar_bigcpu_alert>;
                                cooling-device =
-                                       <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                contribution = <4096>;
                        };
                        map1 {
                                trip = <&ppvar_bigcpu_alert>;
                                cooling-device =
-                                       <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                       <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                contribution = <1024>;
                        };
                };
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts
new file mode 100644 (file)
index 0000000..2d721a9
--- /dev/null
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Gru-Scarlet Rev4+ (SKU-6/Innolux) board device tree source
+ *
+ * Copyright 2018 Google, Inc
+ */
+
+/dts-v1/;
+
+#include "rk3399-gru-scarlet.dtsi"
+
+/ {
+       model = "Google Scarlet";
+       compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15",
+                    "google,scarlet-rev14-sku6", "google,scarlet-rev14",
+                    "google,scarlet-rev13-sku6", "google,scarlet-rev13",
+                    "google,scarlet-rev12-sku6", "google,scarlet-rev12",
+                    "google,scarlet-rev11-sku6", "google,scarlet-rev11",
+                    "google,scarlet-rev10-sku6", "google,scarlet-rev10",
+                    "google,scarlet-rev9-sku6",  "google,scarlet-rev9",
+                    "google,scarlet-rev8-sku6",  "google,scarlet-rev8",
+                    "google,scarlet-rev7-sku6",  "google,scarlet-rev7",
+                    "google,scarlet-rev6-sku6",  "google,scarlet-rev6",
+                    "google,scarlet-rev5-sku6",  "google,scarlet-rev5",
+                    "google,scarlet-rev4-sku6",  "google,scarlet-rev4",
+                    "google,scarlet", "google,gru", "rockchip,rk3399";
+};
+
+&mipi_panel {
+       compatible = "innolux,p097pfg";
+       avdd-supply = <&ppvarp_lcd>;
+       avee-supply = <&ppvarn_lcd>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts
new file mode 100644 (file)
index 0000000..bd75922
--- /dev/null
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Gru-Scarlet Rev3+ (SKU-7/Kingdisplay) board device tree source
+ *
+ * Copyright 2018 Google, Inc
+ */
+
+/dts-v1/;
+
+#include "rk3399-gru-scarlet.dtsi"
+
+/ {
+       model = "Google Scarlet";
+       compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15",
+                    "google,scarlet-rev14-sku7", "google,scarlet-rev14",
+                    "google,scarlet-rev13-sku7", "google,scarlet-rev13",
+                    "google,scarlet-rev12-sku7", "google,scarlet-rev12",
+                    "google,scarlet-rev11-sku7", "google,scarlet-rev11",
+                    "google,scarlet-rev10-sku7", "google,scarlet-rev10",
+                    "google,scarlet-rev9-sku7",  "google,scarlet-rev9",
+                    "google,scarlet-rev8-sku7",  "google,scarlet-rev8",
+                    "google,scarlet-rev7-sku7",  "google,scarlet-rev7",
+                    "google,scarlet-rev6-sku7",  "google,scarlet-rev6",
+                    "google,scarlet-rev5-sku7",  "google,scarlet-rev5",
+                    "google,scarlet-rev4-sku7",  "google,scarlet-rev4",
+                    "google,scarlet-rev3-sku7",  "google,scarlet-rev3",
+                    "google,scarlet", "google,gru", "rockchip,rk3399";
+};
+
+&mipi_panel {
+       compatible = "kingdisplay,kd097d04";
+       power-supply = <&pp3300_s0>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
new file mode 100644 (file)
index 0000000..fc50b3e
--- /dev/null
@@ -0,0 +1,594 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Gru-scarlet board device tree source
+ *
+ * Copyright 2018 Google, Inc
+ */
+
+#include "rk3399-gru.dtsi"
+
+/{
+       /* Power tree */
+
+       /* ppvar_sys children, sorted by name */
+       pp1250_s3: pp1250-s3 {
+               compatible = "regulator-fixed";
+               regulator-name = "pp1250_s3";
+
+               /* EC turns on w/ pp1250_s3_en; always on for AP */
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <1250000>;
+               regulator-max-microvolt = <1250000>;
+
+               vin-supply = <&ppvar_sys>;
+       };
+
+       pp1250_cam: pp1250-dvdd {
+               compatible = "regulator-fixed";
+               regulator-name = "pp1250_dvdd";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pp1250_cam_en>;
+
+               enable-active-high;
+               gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+
+               /* 740us delay from gpio output high to pp1250 stable,
+                * rounding up to 1ms for safety.
+                */
+               startup-delay-us = <1000>;
+               vin-supply = <&pp1250_s3>;
+       };
+
+       pp900_s0: pp900-s0 {
+               compatible = "regulator-fixed";
+               regulator-name = "pp900_s0";
+
+               /* EC turns on w/ pp900_s0_en; always on for AP */
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <900000>;
+               regulator-max-microvolt = <900000>;
+
+               vin-supply = <&ppvar_sys>;
+       };
+
+       ppvarn_lcd: ppvarn-lcd {
+               compatible = "regulator-fixed";
+               regulator-name = "ppvarn_lcd";
+               pinctrl-names = "default";
+               pinctrl-0 = <&ppvarn_lcd_en>;
+
+               enable-active-high;
+               gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+               vin-supply = <&ppvar_sys>;
+       };
+
+       ppvarp_lcd: ppvarp-lcd {
+               compatible = "regulator-fixed";
+               regulator-name = "ppvarp_lcd";
+               pinctrl-names = "default";
+               pinctrl-0 = <&ppvarp_lcd_en>;
+
+               enable-active-high;
+               gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+               vin-supply = <&ppvar_sys>;
+       };
+
+       /* pp1800 children, sorted by name */
+       pp900_s3: pp900-s3 {
+               compatible = "regulator-fixed";
+               regulator-name = "pp900_s3";
+
+               /* EC turns on w/ pp900_s3_en; always on for AP */
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <900000>;
+               regulator-max-microvolt = <900000>;
+
+               vin-supply = <&pp1800>;
+       };
+
+       /* EC turns on pp1800_s3_en */
+       pp1800_s3: pp1800 {
+       };
+
+       /* pp3300 children, sorted by name */
+       pp2800_cam: pp2800-avdd {
+               compatible = "regulator-fixed";
+               regulator-name = "pp2800_avdd";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pp2800_cam_en>;
+
+               enable-active-high;
+               gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
+               startup-delay-us = <100>;
+               vin-supply = <&pp3300>;
+       };
+
+       /* EC turns on pp3300_s0_en */
+       pp3300_s0: pp3300 {
+       };
+
+       /* EC turns on pp3300_s3_en */
+       pp3300_s3: pp3300 {
+       };
+
+       /*
+        * See b/66922012
+        *
+        * This is a hack to make sure the Bluetooth part of the QCA6174A
+        * is reset at boot by toggling BT_EN. At boot BT_EN is first set
+        * to low when the bt_3v3 regulator is registered (in disabled
+        * state). The fake regulator is configured as a supply of the
+        * wlan_3v3 regulator below. When wlan_3v3 is enabled early in
+        * the boot process it also enables its supply regulator bt_3v3,
+        * which changes BT_EN to high.
+        */
+       bt_3v3: bt-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "bt_3v3";
+               pinctrl-names = "default";
+               pinctrl-0 = <&bt_en_1v8_l>;
+
+               enable-active-high;
+               gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+               vin-supply = <&pp3300_s3>;
+       };
+
+       wlan_3v3: wlan-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "wlan_3v3";
+               pinctrl-names = "default";
+               pinctrl-0 = <&wlan_pd_1v8_l>;
+
+               /*
+                * The WL_EN pin is driven low when the regulator is
+                * registered, and transitions to high when the PCIe bus
+                * is powered up.
+                */
+               enable-active-high;
+               gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+
+               /*
+                * Require minimum 10ms from power-on (e.g., PD#) to init PCIe.
+                * TODO (b/64444991): how long to assert PD#?
+                */
+               regulator-enable-ramp-delay = <10000>;
+               /* See bt_3v3 hack above */
+               vin-supply = <&bt_3v3>;
+       };
+
+       backlight: backlight {
+               compatible = "pwm-backlight";
+               enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&bl_en>;
+               pwms = <&pwm1 0 1000000 0>;
+               pwm-delay-us = <10000>;
+       };
+
+       dmic: dmic {
+               compatible = "dmic-codec";
+               dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&dmic_en>;
+               wakeup-delay-ms = <250>;
+       };
+};
+
+/* pp900_s0 aliases */
+pp900_ddrpll_ap: &pp900_s0 {
+};
+pp900_pcie: &pp900_s0 {
+};
+pp900_usb: &pp900_s0 {
+};
+
+/* pp900_s3 aliases */
+pp900_emmcpll: &pp900_s3 {
+};
+
+/* EC turns on; alias for pp1800_s0 */
+pp1800_pcie: &pp1800_s0 {
+};
+
+/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */
+&ppvar_bigcpu {
+       ctrl-voltage-range = <800074 1299226>;
+       regulator-min-microvolt = <800074>;
+       regulator-max-microvolt = <1299226>;
+};
+
+&ppvar_bigcpu_pwm {
+       /* On scarlet ppvar big cpu use pwm3 */
+       pwms = <&pwm3 0 3337 0>;
+       regulator-min-microvolt = <800074>;
+       regulator-max-microvolt = <1299226>;
+};
+
+&ppvar_litcpu {
+       ctrl-voltage-range = <802122 1199620>;
+       regulator-min-microvolt = <802122>;
+       regulator-max-microvolt = <1199620>;
+};
+
+&ppvar_litcpu_pwm {
+       regulator-min-microvolt = <802122>;
+       regulator-max-microvolt = <1199620>;
+};
+
+&ppvar_gpu {
+       ctrl-voltage-range = <799600 1099600>;
+       regulator-min-microvolt = <799600>;
+       regulator-max-microvolt = <1099600>;
+};
+
+&ppvar_gpu_pwm {
+       regulator-min-microvolt = <799600>;
+       regulator-max-microvolt = <1099600>;
+};
+
+&ppvar_sd_card_io {
+       states = <1800000 0x0 3300000 0x1>;
+       regulator-max-microvolt = <3300000>;
+};
+
+&pp3000_sd_slot {
+       vin-supply = <&pp3300>;
+};
+
+ap_i2c_dig: &i2c2 {
+       status = "okay";
+
+       clock-frequency = <400000>;
+
+       /* These are relatively safe rise/fall times. */
+       i2c-scl-falling-time-ns = <50>;
+       i2c-scl-rising-time-ns = <300>;
+
+       digitizer: digitizer@9 {
+               compatible = "hid-over-i2c";
+               reg = <0x9>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               hid-descr-addr = <0x1>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pen_int_odl &pen_reset_l>;
+       };
+};
+
+&ap_i2c_ts {
+       touchscreen: touchscreen@10 {
+               compatible = "elan,ekth3500";
+               reg = <0x10>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&touch_int_l &touch_reset_l>;
+               reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+       };
+};
+
+camera: &i2c7 {
+       status = "okay";
+
+       clock-frequency = <400000>;
+
+       /* These are relatively safe rise/fall times; TODO: measure */
+       i2c-scl-falling-time-ns = <50>;
+       i2c-scl-rising-time-ns = <300>;
+
+       /* 24M mclk is shared between world and user cameras */
+       pinctrl-0 = <&i2c7_xfer &test_clkout1>;
+};
+
+&cdn_dp {
+       extcon = <&usbc_extcon0>;
+       phys = <&tcphy0_dp>;
+};
+
+&cpu_alert0 {
+       temperature = <66000>;
+};
+
+&cpu_alert1 {
+       temperature = <71000>;
+};
+
+&cros_ec {
+       interrupt-parent = <&gpio1>;
+       interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&cru {
+       assigned-clocks =
+               <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+               <&cru PLL_NPLL>,
+               <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
+               <&cru PCLK_PERIHP>,
+               <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
+               <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
+               <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
+               <&cru ACLK_VIO>,
+               <&cru ACLK_GIC_PRE>,
+               <&cru PCLK_DDR>,
+               <&cru ACLK_HDCP>;
+       assigned-clock-rates =
+               <600000000>, <1600000000>,
+               <1000000000>,
+               <150000000>, <75000000>,
+               <37500000>,
+               <100000000>, <100000000>,
+               <50000000>, <800000000>,
+               <100000000>, <50000000>,
+               <400000000>,
+               <200000000>,
+               <200000000>,
+               <400000000>;
+};
+
+&gpio_keys {
+       pinctrl-names = "default";
+       pinctrl-0 = <&bt_host_wake_l>, <&pen_eject_odl>;
+
+       pen-insert {
+               label = "Pen Insert";
+               /* Insert = low, eject = high */
+               gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+               linux,code = <SW_PEN_INSERTED>;
+               linux,input-type = <EV_SW>;
+               wakeup-source;
+       };
+};
+
+&i2c_tunnel {
+       google,remote-bus = <0>;
+};
+
+&io_domains {
+       bt656-supply = <&pp1800_s0>;            /* APIO2_VDD;  2a 2b */
+       audio-supply = <&pp1800_s0>;            /* APIO5_VDD;  3d 4a */
+       gpio1830-supply = <&pp1800_s0>;         /* APIO4_VDD;  4c 4d */
+};
+
+&max98357a {
+       sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+};
+
+&mipi_dsi {
+       status = "okay";
+       clock-master;
+
+       ports {
+               mipi_out: port@1 {
+                       reg = <1>;
+
+                       mipi_out_panel: endpoint {
+                               remote-endpoint = <&mipi_in_panel>;
+                       };
+               };
+       };
+
+       mipi_panel: panel@0 {
+               /* 2 different panels are used, compatibles are in dts files */
+               reg = <0>;
+               backlight = <&backlight>;
+               enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&display_rst_l>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+
+                               mipi_in_panel: endpoint {
+                                       remote-endpoint = <&mipi_out_panel>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+
+                               mipi1_in_panel: endpoint@1 {
+                                       remote-endpoint = <&mipi1_out_panel>;
+                               };
+                       };
+               };
+       };
+};
+
+&mipi_dsi1 {
+       status = "okay";
+
+       ports {
+               mipi1_out: port@1 {
+                       reg = <1>;
+
+                       mipi1_out_panel: endpoint {
+                               remote-endpoint = <&mipi1_in_panel>;
+                       };
+               };
+       };
+};
+
+&pcie0 {
+       ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+
+       /* PERST# asserted in S3 */
+       pcie-reset-suspend = <1>;
+
+       vpcie3v3-supply = <&wlan_3v3>;
+       vpcie1v8-supply = <&pp1800_pcie>;
+};
+
+&sdmmc {
+       cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+};
+
+&sound {
+       rockchip,codec = <&max98357a &dmic &codec &cdn_dp>;
+};
+
+&spi2 {
+       status = "okay";
+};
+
+&wake_on_bt {
+       gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+};
+
+/* PINCTRL OVERRIDES */
+&ec_ap_int_l {
+       rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
+};
+
+&ap_fw_wp {
+       rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&bl_en {
+       rockchip,pins = <4 21 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&bt_host_wake_l {
+       rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
+};
+
+&ec_ap_int_l {
+       rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
+};
+
+&headset_int_l {
+       rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_up>;
+};
+
+&i2s0_8ch_bus {
+       rockchip,pins =
+               <3 24 RK_FUNC_1 &pcfg_pull_none_6ma>,
+               <3 25 RK_FUNC_1 &pcfg_pull_none_6ma>,
+               <3 26 RK_FUNC_1 &pcfg_pull_none_6ma>,
+               <3 27 RK_FUNC_1 &pcfg_pull_none_6ma>,
+               <3 31 RK_FUNC_1 &pcfg_pull_none_6ma>,
+               <4 0 RK_FUNC_1 &pcfg_pull_none_6ma>;
+};
+
+/* there is no external pull up, so need to set this pin pull up */
+&sdmmc_cd_gpio {
+       rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_up>;
+};
+
+&sd_pwr_1800_sel {
+       rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_up>;
+};
+
+&sdmode_en {
+       rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_down>;
+};
+
+&touch_reset_l {
+       rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_down>;
+};
+
+&touch_int_l {
+       rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_down>;
+};
+
+&pinctrl {
+       pinctrl-0 = <
+               &ap_pwroff      /* AP will auto-assert this when in S3 */
+               &clk_32k        /* This pin is always 32k on gru boards */
+               &wlan_rf_kill_1v8_l
+       >;
+
+       pcfg_pull_none_6ma: pcfg-pull-none-6ma {
+               bias-disable;
+               drive-strength = <6>;
+       };
+
+       camera {
+               pp1250_cam_en: pp1250-dvdd {
+                       rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               pp2800_cam_en: pp2800-avdd {
+                       rockchip,pins = <2 24 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               ucam_rst: ucam_rst {
+                       rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               wcam_rst: wcam_rst {
+                       rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       digitizer {
+               pen_int_odl: pen-int-odl {
+                       rockchip,pins = <1 0 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+
+               pen_reset_l: pen-reset-l {
+                       rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       discrete-regulators {
+               display_rst_l: display-rst-l {
+                       rockchip,pins = <4 25 RK_FUNC_GPIO &pcfg_pull_down>;
+               };
+
+               ppvarp_lcd_en: ppvarp-lcd-en {
+                       rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               ppvarn_lcd_en: ppvarn-lcd-en {
+                       rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       dmic {
+               dmic_en: dmic-en {
+                       rockchip,pins = <4 3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       pen {
+               pen_eject_odl: pen-eject-odl {
+                       rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+
+       tpm {
+               h1_int_od_l: h1-int-od-l {
+                       rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+};
+
+&wifi {
+       bt_en_1v8_l: bt-en-1v8-l {
+               rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>;
+       };
+
+       wlan_pd_1v8_l: wlan-pd-1v8-l {
+               rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
+       };
+
+       /* Default pull-up, but just to be clear */
+       wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l {
+               rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+       };
+
+       wifi_perst_l: wifi-perst-l {
+               rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+       };
+
+       wlan_host_wake_l: wlan-host-wake-l {
+               rockchip,pins = <1 3 RK_FUNC_GPIO &pcfg_pull_up>;
+       };
+};
index fef2c06089993c38a76096df356fdf1406fa34f1..0b8f1edbd746b5ce0359e60f8279ca11b6633322 100644 (file)
                };
        };
 
+       backlight: backlight {
+               compatible = "pwm-backlight";
+               brightness-levels = <
+                         0   1   2   3   4   5   6   7
+                         8   9  10  11  12  13  14  15
+                        16  17  18  19  20  21  22  23
+                        24  25  26  27  28  29  30  31
+                        32  33  34  35  36  37  38  39
+                        40  41  42  43  44  45  46  47
+                        48  49  50  51  52  53  54  55
+                        56  57  58  59  60  61  62  63
+                        64  65  66  67  68  69  70  71
+                        72  73  74  75  76  77  78  79
+                        80  81  82  83  84  85  86  87
+                        88  89  90  91  92  93  94  95
+                        96  97  98  99 100 101 102 103
+                       104 105 106 107 108 109 110 111
+                       112 113 114 115 116 117 118 119
+                       120 121 122 123 124 125 126 127
+                       128 129 130 131 132 133 134 135
+                       136 137 138 139 140 141 142 143
+                       144 145 146 147 148 149 150 151
+                       152 153 154 155 156 157 158 159
+                       160 161 162 163 164 165 166 167
+                       168 169 170 171 172 173 174 175
+                       176 177 178 179 180 181 182 183
+                       184 185 186 187 188 189 190 191
+                       192 193 194 195 196 197 198 199
+                       200 201 202 203 204 205 206 207
+                       208 209 210 211 212 213 214 215
+                       216 217 218 219 220 221 222 223
+                       224 225 226 227 228 229 230 231
+                       232 233 234 235 236 237 238 239
+                       240 241 242 243 244 245 246 247
+                       248 249 250 251 252 253 254 255>;
+               default-brightness-level = <200>;
+               enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+               pwms = <&pwm0 0 25000 0>;
+               status = "okay";
+       };
+
        edp_panel: edp-panel {
                compatible ="lg,lp079qx1-sp0v", "simple-panel";
                backlight = <&backlight>;
        };
 };
 
-&backlight {
-       enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
-       status = "okay";
-};
-
 &edp {
        status = "okay";
 
index 5421e23760c35c60d45e0519f1cb9203abf7db83..946d3589575acadfe51627d20b63c04746a93f52 100644 (file)
 / {
        compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
 
-       backlight: backlight {
-               compatible = "pwm-backlight";
-               brightness-levels = <
-                         0   1   2   3   4   5   6   7
-                         8   9  10  11  12  13  14  15
-                        16  17  18  19  20  21  22  23
-                        24  25  26  27  28  29  30  31
-                        32  33  34  35  36  37  38  39
-                        40  41  42  43  44  45  46  47
-                        48  49  50  51  52  53  54  55
-                        56  57  58  59  60  61  62  63
-                        64  65  66  67  68  69  70  71
-                        72  73  74  75  76  77  78  79
-                        80  81  82  83  84  85  86  87
-                        88  89  90  91  92  93  94  95
-                        96  97  98  99 100 101 102 103
-                       104 105 106 107 108 109 110 111
-                       112 113 114 115 116 117 118 119
-                       120 121 122 123 124 125 126 127
-                       128 129 130 131 132 133 134 135
-                       136 137 138 139 140 141 142 143
-                       144 145 146 147 148 149 150 151
-                       152 153 154 155 156 157 158 159
-                       160 161 162 163 164 165 166 167
-                       168 169 170 171 172 173 174 175
-                       176 177 178 179 180 181 182 183
-                       184 185 186 187 188 189 190 191
-                       192 193 194 195 196 197 198 199
-                       200 201 202 203 204 205 206 207
-                       208 209 210 211 212 213 214 215
-                       216 217 218 219 220 221 222 223
-                       224 225 226 227 228 229 230 231
-                       232 233 234 235 236 237 238 239
-                       240 241 242 243 244 245 246 247
-                       248 249 250 251 252 253 254 255>;
-               default-brightness-level = <200>;
-               pwms = <&pwm0 0 25000 0>;
+       chosen {
+               stdout-path = "serial2:1500000n8";
        };
 
        clkin_gmac: external-gmac-clock {
                regulator-max-microvolt = <12000000>;
        };
 
+       /*
+        * The fan power supply comes from the baseboard.
+        * For the standalone Sapphire one option is to connect a wire
+        * from  R90030 DNP R0805 pin2  to  C90002 10uF C0805 pin1 (vcc_sys).
+        */
+       fan0: gpio-fan {
+               #cooling-cells = <2>;
+               compatible = "gpio-fan";
+               gpio-fan,speed-map = <0 0 3000 1>;
+               gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+               status = "okay";
+       };
+
        keys: gpio-keys {
                compatible = "gpio-keys";
                autorepeat;
        cpu-supply = <&vdd_cpu_b>;
 };
 
+&cpu_thermal {
+       trips {
+               cpu_hot: cpu_hot {
+                       hysteresis = <10000>;
+                       temperature = <55000>;
+                       type = "active";
+               };
+       };
+
+       cooling-maps {
+               map2 {
+                       cooling-device =
+                               <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                       trip = <&cpu_hot>;
+               };
+       };
+};
+
 &emmc_phy {
        status = "okay";
 };
                };
        };
 
+       fan {
+               motor_pwr: motor-pwr {
+                       rockchip,pins =
+                               <RK_GPIO1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
        pmic {
                pmic_int_l: pmic-int-l {
                        rockchip,pins =
index 99e7f65c1779475e4f24ebbf68182f78b1a63afc..5bd735637b77341d4fef78b0168b05549de5e5ef 100644 (file)
                clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
                clock-names = "spiclk", "apb_pclk";
                interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
+               dmas = <&dmac_peri 10>, <&dmac_peri 11>;
+               dma-names = "tx", "rx";
                pinctrl-names = "default";
                pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
                #address-cells = <1>;
                clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
                clock-names = "spiclk", "apb_pclk";
                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
+               dmas = <&dmac_peri 12>, <&dmac_peri 13>;
+               dma-names = "tx", "rx";
                pinctrl-names = "default";
                pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
                #address-cells = <1>;
                clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
                clock-names = "spiclk", "apb_pclk";
                interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
+               dmas = <&dmac_peri 14>, <&dmac_peri 15>;
+               dma-names = "tx", "rx";
                pinctrl-names = "default";
                pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
                #address-cells = <1>;
                clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
                clock-names = "spiclk", "apb_pclk";
                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
+               dmas = <&dmac_peri 18>, <&dmac_peri 19>;
+               dma-names = "tx", "rx";
                pinctrl-names = "default";
                pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
                #address-cells = <1>;
                clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
                clock-names = "spiclk", "apb_pclk";
                interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
+               dmas = <&dmac_bus 8>, <&dmac_bus 9>;
+               dma-names = "tx", "rx";
                pinctrl-names = "default";
                pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
                power-domains = <&power RK3399_PD_SDIOAUDIO>;
                                map0 {
                                        trip = <&cpu_alert0>;
                                        cooling-device =
-                                               <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                               <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                                map1 {
                                        trip = <&cpu_alert1>;
                                        cooling-device =
                                                <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-                                               <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                               <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };
                                map0 {
                                        trip = <&gpu_alert0>;
                                        cooling-device =
-                                               <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                               <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };