Merge tag 'mmc-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
authorLinus Torvalds <torvalds@linux-foundation.org>
Tue, 5 Mar 2019 03:07:02 +0000 (19:07 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Tue, 5 Mar 2019 03:07:02 +0000 (19:07 -0800)
Pull MMC updates from Ulf Hansson:
 "MMC core:
   - Fixup max_discard/trim calculations
   - Announce SD specs greater than 4.0
   - Add discard support for SD cards
   - Don't do retries for CMD6 (SWITCH command)
   - Various cleanups and re-structuring

  MMC host:
   - cqhci:
      * Add maintainers for eMMC CQHCI driver
   - sdhci:
      * Consolidate WP GPIO code
      * Add ADMA3 DMA support for V4 enabled host
      * Fixup card detect support in pci-o2micro driver
      * Add support for CMDQ and SDMMC pads auto-calibration in tegra
        driver
      * Add DCMD support and CMDQ support, support for i.MX6ULL variant,
        fixup HS400 timing issue and add HS400_ES support for i.MX8QXP
        to esdhc-imx driver
      * Avoid CRC errors by adjusting settings to speed mode and fixup
        card initialization for high speed mode in renesas_sdhi
      * Fixup timeout settings for omap
      * Enable 8 bits bus-width support in atmel-mci
      * Convert some legacy code in jz4740 driver to use modern APIs
      * Send a CMD12 to clear DPSM at errors for STM32 sdmmc mmci
        driver"

* tag 'mmc-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (69 commits)
  mmc:fix a bug when max_discard is 0
  mmc: core: Add a debug print when the card may have been replaced
  mmc: core: Add sd discard timeout
  mmc: core: Add discard support to sd
  mmc: sdhci-esdhc-imx: clear the HALT bit when enable CQE
  mmc: core: do not retry CMD6 in __mmc_switch()
  mmc: core: Convert mmc_align_data_size() into an SDIO specific function
  mmc: core: Move mmc_of_parse_voltage() to host.c
  mmc: core: Convert mmc_regulator_get_ocrmask() to static
  mmc: core: Move regulator helpers to separate file
  mmc: of_mmc_spi: Convert to mmc_of_parse_voltage()
  mmc: core: Drop retries as in-parameter to mmc_wait_for_app_cmd()
  mmc: core: Convert mmc_wait_for_app_cmd() to static
  mmc: renesas_sdhi: Change HW adjustment register according to speed mode
  mmc: mmci: Send a CMD12 to clear the DPSM at errors
  mmc: sdhci-xenon: Fixup already marked switch fall-through
  mmc: sdhci-tegra: drop ->get_ro() implementation
  mmc: sdhci-omap: drop ->get_ro() implementation
  mmc: sdhci: use WP GPIO in sdhci_check_ro()
  mmc: wmt-sdmmc: Drop unused include
  ...

193 files changed:
Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt [new file with mode: 0644]
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt [new file with mode: 0644]
MAINTAINERS
Makefile
arch/alpha/include/asm/uaccess.h
arch/arm/boot/dts/gemini-dlink-dir-685.dts
arch/arm/crypto/sha256-armv4.pl
arch/arm/crypto/sha256-core.S_shipped
arch/arm/crypto/sha512-armv4.pl
arch/arm/crypto/sha512-core.S_shipped
arch/arm/include/asm/uaccess.h
arch/arm/kernel/process.c
arch/arm/xen/hypercall.S
arch/arm64/boot/dts/qcom/msm8998.dtsi
arch/arm64/crypto/chacha-neon-core.S
arch/arm64/include/asm/uaccess.h
arch/csky/include/asm/segment.h
arch/h8300/include/asm/segment.h
arch/ia64/include/asm/uaccess.h
arch/m68k/include/asm/segment.h
arch/microblaze/include/asm/uaccess.h
arch/mips/bcm63xx/dev-enet.c
arch/mips/include/asm/uaccess.h
arch/mips/kernel/cmpxchg.c
arch/mips/kernel/ftrace.c
arch/mips/kernel/kgdb.c
arch/mips/kernel/setup.c
arch/mips/kernel/traps.c
arch/mips/lantiq/xway/vmmc.c
arch/mips/net/ebpf_jit.c
arch/nds32/include/asm/uaccess.h
arch/nds32/kernel/process.c
arch/nios2/include/asm/uaccess.h
arch/openrisc/include/asm/uaccess.h
arch/parisc/include/asm/uaccess.h
arch/powerpc/include/asm/uaccess.h
arch/riscv/include/asm/uaccess.h
arch/s390/include/asm/uaccess.h
arch/sh/include/asm/segment.h
arch/sparc/include/asm/uaccess_32.h
arch/sparc/include/asm/uaccess_64.h
arch/x86/include/asm/hyperv-tlfs.h
arch/x86/include/asm/uaccess.h
arch/x86/mm/extable.c
arch/xtensa/include/asm/asm-uaccess.h
arch/xtensa/include/asm/uaccess.h
drivers/crypto/ccree/cc_pm.h
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/bochs/bochs_drv.c
drivers/gpu/drm/drm_atomic_helper.c
drivers/i3c/master/dw-i3c-master.c
drivers/iommu/dmar.c
drivers/mtd/chips/cfi_cmdset_0001.c
drivers/mtd/chips/gen_probe.c
drivers/mtd/devices/docg3.c
drivers/mtd/devices/m25p80.c
drivers/mtd/devices/mtdram.c
drivers/mtd/lpddr/qinfo_probe.c
drivers/mtd/mtdcore.c
drivers/mtd/nand/raw/Kconfig
drivers/mtd/nand/raw/Makefile
drivers/mtd/nand/raw/atmel/pmecc.c
drivers/mtd/nand/raw/denali.c
drivers/mtd/nand/raw/denali.h
drivers/mtd/nand/raw/denali_dt.c
drivers/mtd/nand/raw/fsmc_nand.c
drivers/mtd/nand/raw/jz4780_bch.c
drivers/mtd/nand/raw/marvell_nand.c
drivers/mtd/nand/raw/meson_nand.c [new file with mode: 0644]
drivers/mtd/nand/raw/mtk_ecc.c
drivers/mtd/nand/raw/mtk_nand.c
drivers/mtd/nand/raw/nand_base.c
drivers/mtd/nand/raw/nand_legacy.c
drivers/mtd/nand/raw/omap2.c
drivers/mtd/nand/raw/r852.c
drivers/mtd/nand/raw/stm32_fmc2_nand.c [new file with mode: 0644]
drivers/mtd/nand/raw/sunxi_nand.c
drivers/mtd/nand/raw/tmio_nand.c
drivers/mtd/nand/spi/gigadevice.c
drivers/mtd/nand/spi/macronix.c
drivers/mtd/nand/spi/toshiba.c
drivers/mtd/spi-nor/Kconfig
drivers/mtd/spi-nor/Makefile
drivers/mtd/spi-nor/cadence-quadspi.c
drivers/mtd/spi-nor/mtk-quadspi.c
drivers/mtd/spi-nor/spi-nor.c
drivers/net/dsa/lantiq_gswip.c
drivers/net/dsa/mv88e6xxx/chip.c
drivers/net/dsa/mv88e6xxx/port.c
drivers/net/dsa/mv88e6xxx/port.h
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
drivers/net/ethernet/broadcom/bnxt/bnxt.c
drivers/net/ethernet/microchip/enc28j60.c
drivers/net/ethernet/microchip/lan743x_main.c
drivers/net/geneve.c
drivers/net/hyperv/netvsc_drv.c
drivers/net/phy/dp83867.c
drivers/net/phy/micrel.c
drivers/net/phy/phylink.c
drivers/net/tun.c
drivers/net/xen-netback/hash.c
drivers/net/xen-netback/interface.c
drivers/net/xen-netback/netback.c
drivers/scsi/3w-9xxx.c
drivers/scsi/3w-sas.c
drivers/scsi/aic94xx/aic94xx_init.c
drivers/scsi/bfa/bfad.c
drivers/scsi/csiostor/csio_init.c
drivers/scsi/hisi_sas/hisi_sas_main.c
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
drivers/scsi/hptiop.c
drivers/scsi/lpfc/lpfc_init.c
drivers/scsi/scsi_lib.c
drivers/staging/rtl8723bs/os_dep/osdep_service.c
drivers/tee/optee/core.c
drivers/vfio/mdev/mdev_core.c
drivers/vfio/mdev/mdev_private.h
drivers/vfio/mdev/mdev_sysfs.c
drivers/vfio/pci/vfio_pci.c
drivers/vfio/pci/vfio_pci_config.c
drivers/vfio/pci/vfio_pci_private.h
drivers/vfio/platform/reset/Makefile
drivers/vfio/platform/reset/vfio_platform_amdxgbe.c
drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c
drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c
drivers/vfio/vfio.c
drivers/vfio/vfio_iommu_spapr_tce.c
fs/afs/cell.c
fs/aio.c
fs/exec.c
fs/hugetlbfs/inode.c
fs/kernfs/mount.c
fs/namespace.c
fs/orangefs/file.c
fs/read_write.c
fs/splice.c
include/asm-generic/uaccess.h
include/linux/fs.h
include/linux/mdev.h
include/linux/mtd/rawnand.h
include/linux/mtd/spi-nor.h
include/linux/netdevice.h
include/linux/sched.h
include/net/icmp.h
include/net/ip.h
kernel/bpf/syscall.c
kernel/bpf/verifier.c
kernel/cgroup/cgroup-internal.h
kernel/cgroup/cgroup-v1.c
kernel/cgroup/cgroup.c
lib/Kconfig.kasan
mm/hugetlb.c
mm/maccess.c
mm/migrate.c
mm/mmap.c
mm/shmem.c
net/dsa/dsa2.c
net/dsa/port.c
net/ipv4/cipso_ipv4.c
net/ipv4/fib_frontend.c
net/ipv4/icmp.c
net/ipv4/ip_input.c
net/ipv4/ip_options.c
net/ipv4/netlink.c
net/ipv4/route.c
net/ipv6/route.c
net/ipv6/sit.c
net/mpls/af_mpls.c
net/netlabel/netlabel_kapi.c
net/nfc/llcp_commands.c
net/nfc/llcp_core.c
net/sched/act_ipt.c
net/sched/act_skbedit.c
net/sched/act_tunnel_key.c
net/sched/sch_netem.c
net/sctp/chunk.c
net/socket.c
net/tipc/socket.c
samples/vfio-mdev/mbochs.c
samples/vfio-mdev/mdpy.c
samples/vfio-mdev/mtty.c
scripts/Makefile.kasan
security/integrity/iint.c
tools/testing/selftests/net/pmtu.sh
tools/testing/selftests/net/udpgro.sh
tools/testing/selftests/net/udpgso_bench_rx.c
virt/kvm/kvm_main.c

diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
new file mode 100644 (file)
index 0000000..3983c11
--- /dev/null
@@ -0,0 +1,60 @@
+Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
+
+This file documents the properties in addition to those available in
+the MTD NAND bindings.
+
+Required properties:
+- compatible : contains one of:
+  - "amlogic,meson-gxl-nfc"
+  - "amlogic,meson-axg-nfc"
+- clocks     :
+       A list of phandle + clock-specifier pairs for the clocks listed
+       in clock-names.
+
+- clock-names: Should contain the following:
+       "core" - NFC module gate clock
+       "device" - device clock from eMMC sub clock controller
+       "rx" - rx clock phase
+       "tx" - tx clock phase
+
+- amlogic,mmc-syscon   : Required for NAND clocks, it's shared with SD/eMMC
+                               controller port C
+
+Optional children nodes:
+Children nodes represent the available nand chips.
+
+Other properties:
+see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
+
+Example demonstrate on AXG SoC:
+
+       sd_emmc_c_clkc: mmc@7000 {
+               compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
+               reg = <0x0 0x7000 0x0 0x800>;
+       };
+
+       nand-controller@7800 {
+               compatible = "amlogic,meson-axg-nfc";
+               reg = <0x0 0x7800 0x0 0x100>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
+
+               clocks = <&clkc CLKID_SD_EMMC_C>,
+                       <&sd_emmc_c_clkc CLKID_MMC_DIV>,
+                       <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>,
+                       <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>;
+               clock-names = "core", "device", "rx", "tx";
+               amlogic,mmc-syscon = <&sd_emmc_c_clkc>;
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&nand_pins>;
+
+               nand@0 {
+                       reg = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       nand-on-flash-bbt;
+               };
+       };
index bb2075df9b3826dd813dd23567ac470ffed5144e..4345c3a6f5300725d72b5dd3c93f6e9a7c82ddb2 100644 (file)
@@ -4,6 +4,7 @@ Required properties:
 - compatible : should be one of the following:
        Generic default - "cdns,qspi-nor".
        For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
+       For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".
 - reg : Contains two entries, each of which is a tuple consisting of a
        physical address and length. The first entry is the address and
        length of the controller register set. The second entry is the
index 56d3668e2c50e808fca1274436d151951f4ee6a1..a12e3b5c495d969eb7cef2b99f1cef25990e4bd9 100644 (file)
@@ -1,4 +1,4 @@
-* Serial NOR flash controller for MTK MT81xx (and similar)
+* Serial NOR flash controller for MediaTek SoCs
 
 Required properties:
 - compatible:    For mt8173, compatible should be "mediatek,mt8173-nor",
@@ -10,6 +10,7 @@ Required properties:
                  "mediatek,mt2712-nor", "mediatek,mt8173-nor"
                  "mediatek,mt7622-nor", "mediatek,mt8173-nor"
                  "mediatek,mt7623-nor", "mediatek,mt8173-nor"
+                 "mediatek,mt7629-nor", "mediatek,mt8173-nor"
                  "mediatek,mt8173-nor"
 - reg:                   physical base address and length of the controller's register
 - clocks:        the phandle of the clocks needed by the nor controller
diff --git a/Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt b/Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt
new file mode 100644 (file)
index 0000000..ad2bef8
--- /dev/null
@@ -0,0 +1,61 @@
+STMicroelectronics Flexible Memory Controller 2 (FMC2)
+NAND Interface
+
+Required properties:
+- compatible: Should be one of:
+              * st,stm32mp15-fmc2
+- reg: NAND flash controller memory areas.
+       First region contains the register location.
+       Regions 2 to 4 respectively contain the data, command,
+       and address space for CS0.
+       Regions 5 to 7 contain the same areas for CS1.
+- interrupts: The interrupt number
+- pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
+- clocks: The clock needed by the NAND flash controller
+
+Optional properties:
+- resets: Reference to a reset controller asserting the FMC controller
+- dmas: DMA specifiers (see: dma/stm32-mdma.txt)
+- dma-names: Must be "tx", "rx" and "ecc"
+
+* NAND device bindings:
+
+Required properties:
+- reg: describes the CS lines assigned to the NAND device.
+
+Optional properties:
+- nand-on-flash-bbt: see nand.txt
+- nand-ecc-strength: see nand.txt
+- nand-ecc-step-size: see nand.txt
+
+The following ECC strength and step size are currently supported:
+ - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
+ - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
+ - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) (default)
+
+Example:
+
+       fmc: nand-controller@58002000 {
+               compatible = "st,stm32mp15-fmc2";
+               reg = <0x58002000 0x1000>,
+                     <0x80000000 0x1000>,
+                     <0x88010000 0x1000>,
+                     <0x88020000 0x1000>,
+                     <0x81000000 0x1000>,
+                     <0x89010000 0x1000>,
+                     <0x89020000 0x1000>;
+               interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&rcc FMC_K>;
+               resets = <&rcc FMC_R>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&fmc_pins_a>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               nand@0 {
+                       reg = <0>;
+                       nand-on-flash-bbt;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+               };
+       };
index 91eacdbe9cda45f1a01b7c95e76c7465fe07710e..84857bc78a61baeeec36fbb3e894216f958e3c84 100644 (file)
@@ -7176,6 +7176,7 @@ F:        drivers/i2c/i2c-stub.c
 I3C SUBSYSTEM
 M:     Boris Brezillon <bbrezillon@kernel.org>
 L:     linux-i3c@lists.infradead.org
+C:     irc://chat.freenode.net/linux-i3c
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git
 S:     Maintained
 F:     Documentation/ABI/testing/sysfs-bus-i3c
@@ -9866,6 +9867,13 @@ F:       drivers/media/platform/meson/ao-cec.c
 F:     Documentation/devicetree/bindings/media/meson-ao-cec.txt
 T:     git git://linuxtv.org/media_tree.git
 
+MESON NAND CONTROLLER DRIVER FOR AMLOGIC SOCS
+M:     Liang Yang <liang.yang@amlogic.com>
+L:     linux-mtd@lists.infradead.org
+S:     Maintained
+F:     drivers/mtd/nand/raw/meson_*
+F:     Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
+
 MICROBLAZE ARCHITECTURE
 M:     Michal Simek <monstr@monstr.eu>
 W:     http://www.monstr.eu/fdt/
@@ -14346,6 +14354,7 @@ F:      arch/arm/mach-spear/
 
 SPI NOR SUBSYSTEM
 M:     Marek Vasut <marek.vasut@gmail.com>
+M:     Tudor Ambarus <tudor.ambarus@microchip.com>
 L:     linux-mtd@lists.infradead.org
 W:     http://www.linux-mtd.infradead.org/
 Q:     http://patchwork.ozlabs.org/project/linux-mtd/list/
index ac5ac28a24e99120726f9fbb2cc9c228090d1317..d5713e7b1e5069fc69888880c4373818827710ac 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
 VERSION = 5
 PATCHLEVEL = 0
 SUBLEVEL = 0
-EXTRAVERSION = -rc8
+EXTRAVERSION =
 NAME = Shy Crocodile
 
 # *DOCUMENTATION*
index cf4ac791a592fdf8dc595e9407182c85bdac4243..1fe2b56cb861fe4150785699ded8f29fc8132baf 100644 (file)
@@ -18,7 +18,6 @@
 #define USER_DS                ((mm_segment_t) { -0x40000000000UL })
 
 #define get_fs()  (current_thread_info()->addr_limit)
-#define get_ds()  (KERNEL_DS)
 #define set_fs(x) (current_thread_info()->addr_limit = (x))
 
 #define segment_eq(a, b)       ((a).seg == (b).seg)
index cc0c3cf89eaad5842f26c3d42bf1b71b64c567bd..592111c8d6fdfcd299a316b2bf02d757c6f40cef 100644 (file)
                };
 
                display-controller@6a000000 {
-                       status = "disabled";
+                       status = "okay";
 
                        port@0 {
                                reg = <0>;
index b9ec44060ed313dac5c469e4e6e39e905d0206cc..a03cf4dfb7818d1275ee0d06ecf633b149adf1cd 100644 (file)
@@ -212,10 +212,11 @@ K256:
 .global        sha256_block_data_order
 .type  sha256_block_data_order,%function
 sha256_block_data_order:
+.Lsha256_block_data_order:
 #if __ARM_ARCH__<7
        sub     r3,pc,#8                @ sha256_block_data_order
 #else
-       adr     r3,sha256_block_data_order
+       adr     r3,.Lsha256_block_data_order
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
        ldr     r12,.LOPENSSL_armcap
index 3b58300d611cf4c94f9014901d0a3204acb75f13..054aae0edfce5628715d607fd7d194ac5cc81938 100644 (file)
@@ -93,10 +93,11 @@ K256:
 .global        sha256_block_data_order
 .type  sha256_block_data_order,%function
 sha256_block_data_order:
+.Lsha256_block_data_order:
 #if __ARM_ARCH__<7
        sub     r3,pc,#8                @ sha256_block_data_order
 #else
-       adr     r3,sha256_block_data_order
+       adr     r3,.Lsha256_block_data_order
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
        ldr     r12,.LOPENSSL_armcap
index fb5d15048c0b2d2ea2d8c8c9a2bdbb15a6c14052..788c17b56ecceb5e607382539faec13b8fbc2886 100644 (file)
@@ -274,10 +274,11 @@ WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
 .global        sha512_block_data_order
 .type  sha512_block_data_order,%function
 sha512_block_data_order:
+.Lsha512_block_data_order:
 #if __ARM_ARCH__<7
        sub     r3,pc,#8                @ sha512_block_data_order
 #else
-       adr     r3,sha512_block_data_order
+       adr     r3,.Lsha512_block_data_order
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
        ldr     r12,.LOPENSSL_armcap
index b1c334a49cdaa61f019b7367bfa4e20d4ac4a078..710ea309769e71628d1d4a166c834ad92033b658 100644 (file)
@@ -141,10 +141,11 @@ WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
 .global        sha512_block_data_order
 .type  sha512_block_data_order,%function
 sha512_block_data_order:
+.Lsha512_block_data_order:
 #if __ARM_ARCH__<7
        sub     r3,pc,#8                @ sha512_block_data_order
 #else
-       adr     r3,sha512_block_data_order
+       adr     r3,.Lsha512_block_data_order
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
        ldr     r12,.LOPENSSL_armcap
index 42aa4a22803c2760d7799bdd17b4434d9cc387bd..ae5a0df5316e5780121bcc8de5f78b847222e9e7 100644 (file)
@@ -59,7 +59,6 @@ extern int __put_user_bad(void);
  * Note that this is actually 0x1,0000,0000
  */
 #define KERNEL_DS      0x00000000
-#define get_ds()       (KERNEL_DS)
 
 #ifdef CONFIG_MMU
 
index 16601d1442d1767b4498442b8454a31afb34268d..72cc0862a30e9a96722716e561cd9633d752cdc6 100644 (file)
@@ -150,7 +150,7 @@ void __show_regs(struct pt_regs *regs)
                if ((domain & domain_mask(DOMAIN_USER)) ==
                    domain_val(DOMAIN_USER, DOMAIN_NOACCESS))
                        segment = "none";
-               else if (fs == get_ds())
+               else if (fs == KERNEL_DS)
                        segment = "kernel";
                else
                        segment = "user";
index b0b80c0f09f31e30aba022e317b4d9a19daaccbd..b11bba542faccc4889abe8b5571b583e83ee0479 100644 (file)
@@ -113,8 +113,7 @@ ENTRY(privcmd_call)
 
        /*
         * Disable userspace access from kernel. This is fine to do it
-        * unconditionally as no set_fs(KERNEL_DS)/set_fs(get_ds()) is
-        * called before.
+        * unconditionally as no set_fs(KERNEL_DS) is called before.
         */
        uaccess_disable r4
 
index 8d41b69ec2dab077eb535c26386d385392fca339..99bccaac31ad8783da3f19c11ca2af7a9355c317 100644 (file)
@@ -37,7 +37,7 @@
                };
 
                memory@86200000 {
-                       reg = <0x0 0x86200000 0x0 0x2600000>;
+                       reg = <0x0 0x86200000 0x0 0x2d00000>;
                        no-map;
                };
 
index 021bb9e9784b271cb670f8c973312e9e2ec14ba4..706c4e10e9e294c7c5de49dbbe7a784ec7ca1458 100644 (file)
@@ -158,8 +158,8 @@ ENTRY(hchacha_block_neon)
        mov             w3, w2
        bl              chacha_permute
 
-       st1             {v0.16b}, [x1], #16
-       st1             {v3.16b}, [x1]
+       st1             {v0.4s}, [x1], #16
+       st1             {v3.4s}, [x1]
 
        ldp             x29, x30, [sp], #16
        ret
@@ -532,6 +532,10 @@ ENTRY(chacha_4block_xor_neon)
        add             v3.4s, v3.4s, v19.4s
          add           a2, a2, w8
          add           a3, a3, w9
+CPU_BE(          rev           a0, a0          )
+CPU_BE(          rev           a1, a1          )
+CPU_BE(          rev           a2, a2          )
+CPU_BE(          rev           a3, a3          )
 
        ld4r            {v24.4s-v27.4s}, [x0], #16
        ld4r            {v28.4s-v31.4s}, [x0]
@@ -552,6 +556,10 @@ ENTRY(chacha_4block_xor_neon)
        add             v7.4s, v7.4s, v23.4s
          add           a6, a6, w8
          add           a7, a7, w9
+CPU_BE(          rev           a4, a4          )
+CPU_BE(          rev           a5, a5          )
+CPU_BE(          rev           a6, a6          )
+CPU_BE(          rev           a7, a7          )
 
        // x8[0-3] += s2[0]
        // x9[0-3] += s2[1]
@@ -569,6 +577,10 @@ ENTRY(chacha_4block_xor_neon)
        add             v11.4s, v11.4s, v27.4s
          add           a10, a10, w8
          add           a11, a11, w9
+CPU_BE(          rev           a8, a8          )
+CPU_BE(          rev           a9, a9          )
+CPU_BE(          rev           a10, a10        )
+CPU_BE(          rev           a11, a11        )
 
        // x12[0-3] += s3[0]
        // x13[0-3] += s3[1]
@@ -586,6 +598,10 @@ ENTRY(chacha_4block_xor_neon)
        add             v15.4s, v15.4s, v31.4s
          add           a14, a14, w8
          add           a15, a15, w9
+CPU_BE(          rev           a12, a12        )
+CPU_BE(          rev           a13, a13        )
+CPU_BE(          rev           a14, a14        )
+CPU_BE(          rev           a15, a15        )
 
        // interleave 32-bit words in state n, n+1
          ldp           w6, w7, [x2], #64
index 547d7a0c9d05bdfa30cc102acbc4a7c403d5bfc6..f1e5c9165809ea589e1923bdd09cbf881836ff91 100644 (file)
@@ -34,7 +34,6 @@
 #include <asm/memory.h>
 #include <asm/extable.h>
 
-#define get_ds()       (KERNEL_DS)
 #define get_fs()       (current_thread_info()->addr_limit)
 
 static inline void set_fs(mm_segment_t fs)
index ffdc4c47ff4338322666ffc95b0cb39b75ef3af2..db2640d5f57591f32adb9b9508daf2233358582c 100644 (file)
@@ -9,7 +9,6 @@ typedef struct {
 } mm_segment_t;
 
 #define KERNEL_DS              ((mm_segment_t) { 0xFFFFFFFF })
-#define get_ds()               KERNEL_DS
 
 #define USER_DS                        ((mm_segment_t) { 0x80000000UL })
 #define get_fs()               (current_thread_info()->addr_limit)
index 9adbf7e1aaa395e4337ab3b2e5e4729db9c2dc2c..a407978f9f9fb8219f64f4561fbe80cfc91678e3 100644 (file)
@@ -33,12 +33,6 @@ static inline mm_segment_t get_fs(void)
        return USER_DS;
 }
 
-static inline mm_segment_t get_ds(void)
-{
-       /* return the supervisor data space code */
-       return KERNEL_DS;
-}
-
 #define segment_eq(a, b)       ((a).seg == (b).seg)
 
 #endif /* __ASSEMBLY__ */
index 306d469e43da6d45e5b7bb2b5aac58f387fd9955..89782ad3fb887b98ce5913b56841375e4ad143a9 100644 (file)
@@ -48,7 +48,6 @@
 #define KERNEL_DS      ((mm_segment_t) { ~0UL })               /* cf. access_ok() */
 #define USER_DS                ((mm_segment_t) { TASK_SIZE-1 })        /* cf. access_ok() */
 
-#define get_ds()  (KERNEL_DS)
 #define get_fs()  (current_thread_info()->addr_limit)
 #define set_fs(x) (current_thread_info()->addr_limit = (x))
 
index 0b4cc1e079b5e5a8cf37df88b720198417f2de24..c6686559e9b742f5df781efac658a9c6f57553a3 100644 (file)
@@ -45,16 +45,9 @@ static inline void set_fs(mm_segment_t val)
                              : /* no outputs */ : "r" (val.seg) : "memory");
 }
 
-static inline mm_segment_t get_ds(void)
-{
-    /* return the supervisor data space code */
-    return KERNEL_DS;
-}
-
 #else
 #define USER_DS                MAKE_MM_SEG(TASK_SIZE)
 #define KERNEL_DS      MAKE_MM_SEG(0xFFFFFFFF)
-#define get_ds()       (KERNEL_DS)
 #define get_fs()       (current_thread_info()->addr_limit)
 #define set_fs(x)      (current_thread_info()->addr_limit = (x))
 #endif
index dbfea093a7c7db596bd2e108a0a47220b7698457..bff2a71c828a349aeb9eafb8de43b2c7c2263612 100644 (file)
@@ -42,7 +42,6 @@
 #  define USER_DS      MAKE_MM_SEG(TASK_SIZE - 1)
 #  endif
 
-# define get_ds()      (KERNEL_DS)
 # define get_fs()      (current_thread_info()->addr_limit)
 # define set_fs(val)   (current_thread_info()->addr_limit = (val))
 
index 07b4c65a88a43708467626b410baf79936bac203..8e73d65f348064792e5a1515ddcd7809b12da2c8 100644 (file)
@@ -70,6 +70,8 @@ static struct platform_device bcm63xx_enet_shared_device = {
 
 static int shared_device_registered;
 
+static u64 enet_dmamask = DMA_BIT_MASK(32);
+
 static struct resource enet0_res[] = {
        {
                .start          = -1, /* filled at runtime */
@@ -99,6 +101,8 @@ static struct platform_device bcm63xx_enet0_device = {
        .resource       = enet0_res,
        .dev            = {
                .platform_data = &enet0_pd,
+               .dma_mask = &enet_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
        },
 };
 
@@ -131,6 +135,8 @@ static struct platform_device bcm63xx_enet1_device = {
        .resource       = enet1_res,
        .dev            = {
                .platform_data = &enet1_pd,
+               .dma_mask = &enet_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
        },
 };
 
@@ -157,6 +163,8 @@ static struct platform_device bcm63xx_enetsw_device = {
        .resource       = enetsw_res,
        .dev            = {
                .platform_data = &enetsw_pd,
+               .dma_mask = &enet_dmamask,
+               .coherent_dma_mask = DMA_BIT_MASK(32),
        },
 };
 
index d43c1dc6ef157a59c4b96d456aacc9d69ce077ed..62b298c50905f67cdcd2221c5d28ae179a195a7d 100644 (file)
@@ -69,7 +69,6 @@ extern u64 __ua_limit;
 #define USER_DS                ((mm_segment_t) { __UA_LIMIT })
 #endif
 
-#define get_ds()       (KERNEL_DS)
 #define get_fs()       (current_thread_info()->addr_limit)
 #define set_fs(x)      (current_thread_info()->addr_limit = (x))
 
index 0b9535bc2c53d0c450a0c02beb24691d356614e2..6b2a4a902a981c7365cb05abc94744cfc6648741 100644 (file)
@@ -54,10 +54,9 @@ unsigned long __xchg_small(volatile void *ptr, unsigned long val, unsigned int s
 unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
                              unsigned long new, unsigned int size)
 {
-       u32 mask, old32, new32, load32;
+       u32 mask, old32, new32, load32, load;
        volatile u32 *ptr32;
        unsigned int shift;
-       u8 load;
 
        /* Check that ptr is naturally aligned */
        WARN_ON((unsigned long)ptr & (size - 1));
index 2ea0ec95efe9b7f31974cb0cbbb9872c92389a6e..4b5e1f2bfbcea85f6b3c339bdd3c0efaf491beb9 100644 (file)
@@ -86,7 +86,7 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
                return -EFAULT;
 
        old_fs = get_fs();
-       set_fs(get_ds());
+       set_fs(KERNEL_DS);
        flush_icache_range(ip, ip + 8);
        set_fs(old_fs);
 
@@ -111,7 +111,7 @@ static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1,
 
        ip -= 4;
        old_fs = get_fs();
-       set_fs(get_ds());
+       set_fs(KERNEL_DS);
        flush_icache_range(ip, ip + 8);
        set_fs(old_fs);
 
@@ -135,7 +135,7 @@ static int ftrace_modify_code_2r(unsigned long ip, unsigned int new_code1,
                return -EFAULT;
 
        old_fs = get_fs();
-       set_fs(get_ds());
+       set_fs(KERNEL_DS);
        flush_icache_range(ip, ip + 8);
        set_fs(old_fs);
 
index 149100e1bc7c4687903d929e6b9a33700b199454..6e574c02e4c3b81137618c97fe9bc176c5a40d52 100644 (file)
@@ -212,7 +212,7 @@ void kgdb_call_nmi_hook(void *ignored)
        mm_segment_t old_fs;
 
        old_fs = get_fs();
-       set_fs(get_ds());
+       set_fs(KERNEL_DS);
 
        kgdb_nmicallback(raw_smp_processor_id(), NULL);
 
@@ -318,7 +318,7 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd,
 
        /* Kernel mode. Set correct address limit */
        old_fs = get_fs();
-       set_fs(get_ds());
+       set_fs(KERNEL_DS);
 
        if (atomic_read(&kgdb_active) != -1)
                kgdb_nmicallback(smp_processor_id(), regs);
index 8c6c48ed786a1527c22ba5b46bcdad70029e5865..d2e5a5ad0e6f5e4b90e5f1a20c7942f40a1c735d 100644 (file)
@@ -384,7 +384,8 @@ static void __init bootmem_init(void)
        init_initrd();
        reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end));
 
-       memblock_reserve(PHYS_OFFSET, reserved_end << PAGE_SHIFT);
+       memblock_reserve(PHYS_OFFSET,
+                        (reserved_end << PAGE_SHIFT) - PHYS_OFFSET);
 
        /*
         * max_low_pfn is not a number of pages. The number of pages
index c91097f7b32f1d3a87dcb36a375c18d1ed8ff220..cbab46004e99d4f07c1eb9a10c16bba3b5cb992f 100644 (file)
@@ -1077,7 +1077,7 @@ asmlinkage void do_tr(struct pt_regs *regs)
 
        seg = get_fs();
        if (!user_mode(regs))
-               set_fs(get_ds());
+               set_fs(KERNEL_DS);
 
        prev_state = exception_enter();
        current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
index 577ec81b557dcfa2d4805ed39cbcaffb1f7052d1..3deab9a777185a634b095ebb2c8297f32fbaf90c 100644 (file)
@@ -31,8 +31,8 @@ static int vmmc_probe(struct platform_device *pdev)
        dma_addr_t dma;
 
        cp1_base =
-               (void *) CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE,
-                                                   &dma, GFP_ATOMIC));
+               (void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE,
+                                                   &dma, GFP_KERNEL));
 
        gpio_count = of_gpio_count(pdev->dev.of_node);
        while (gpio_count > 0) {
index 76e9bf88d3b9198f6b1e8baaf8aa620bd1755959..0effd3cba9a731907920c6f47a1b52321ac7225f 100644 (file)
@@ -1819,7 +1819,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
 
        /* Update the icache */
        flush_icache_range((unsigned long)ctx.target,
-                          (unsigned long)(ctx.target + ctx.idx * sizeof(u32)));
+                          (unsigned long)&ctx.target[ctx.idx]);
 
        if (bpf_jit_enable > 1)
                /* Dump JIT code */
index 53dcb49b0b12f5b8a85dd1858f71d3b4a0f23939..116598b47c4d2b7c19cce39ba9ad98d8c00e51fd 100644 (file)
@@ -37,7 +37,6 @@ extern int fixup_exception(struct pt_regs *regs);
 #define KERNEL_DS      ((mm_segment_t) { ~0UL })
 #define USER_DS                ((mm_segment_t) {TASK_SIZE - 1})
 
-#define get_ds()       (KERNEL_DS)
 #define get_fs()       (current_thread_info()->addr_limit)
 #define user_addr_max  get_fs
 
index ab7ab46234b1475c106d8adb9a79e9eff0de6f12..9712fd474f2ca3faa4b7dc6e66f5503b48ef59f8 100644 (file)
@@ -121,7 +121,7 @@ void show_regs(struct pt_regs *regs)
                regs->uregs[3], regs->uregs[2], regs->uregs[1], regs->uregs[0]);
        pr_info("  IRQs o%s  Segment %s\n",
                interrupts_enabled(regs) ? "n" : "ff",
-               segment_eq(get_fs(), get_ds())? "kernel" : "user");
+               segment_eq(get_fs(), KERNEL_DS)? "kernel" : "user");
 }
 
 EXPORT_SYMBOL(show_regs);
index e0ea10806491f47f8e9e7b21b8edd938881b1b5b..e83f831a76f93926e5ac5717b259d3b5777dae97 100644 (file)
@@ -26,7 +26,6 @@
 #define USER_DS                        MAKE_MM_SEG(0x80000000UL)
 #define KERNEL_DS              MAKE_MM_SEG(0)
 
-#define get_ds()               (KERNEL_DS)
 
 #define get_fs()               (current_thread_info()->addr_limit)
 #define set_fs(seg)            (current_thread_info()->addr_limit = (seg))
index a44682c8adc34efeeb794a9340d4962fdf50d622..45afd9ab78c1b5d4ff3c13a09433fd0028a12ab9 100644 (file)
@@ -42,7 +42,6 @@
  */
 
 #define KERNEL_DS      (~0UL)
-#define get_ds()       (KERNEL_DS)
 
 #define USER_DS                (TASK_SIZE)
 #define get_fs()       (current_thread_info()->addr_limit)
index 30ac2865ea730cdf650efd7ca993cfd6daa79d2e..ebbb9ffe038c76728de555ca8a3d2b0ec86020a2 100644 (file)
@@ -16,7 +16,6 @@
 
 #define segment_eq(a, b) ((a).seg == (b).seg)
 
-#define get_ds()       (KERNEL_DS)
 #define get_fs()       (current_thread_info()->addr_limit)
 #define set_fs(x)      (current_thread_info()->addr_limit = (x))
 
index e3a731793ea23f24bbe28981f7191ed48a14f715..4d6d905e913809ef018ecc57a1c31a2845fdfd7f 100644 (file)
@@ -28,7 +28,6 @@
 #define USER_DS                MAKE_MM_SEG(TASK_SIZE - 1)
 #endif
 
-#define get_ds()       (KERNEL_DS)
 #define get_fs()       (current->thread.addr_limit)
 
 static inline void set_fs(mm_segment_t fs)
index 637b896894fc4380ad19e8f96fa0d76e35da7b69..a00168b980d2e6ca265ae0424045508275fbbe3f 100644 (file)
@@ -41,7 +41,6 @@
 #define KERNEL_DS      (~0UL)
 #define USER_DS                (TASK_SIZE)
 
-#define get_ds()       (KERNEL_DS)
 #define get_fs()       (current_thread_info()->addr_limit)
 
 static inline void set_fs(mm_segment_t fs)
index bd2545977ad35f33ee8c2f3fa63466e52a97a59b..007fcb9aeeb83eb99d00a0ea116236f8213e9db1 100644 (file)
@@ -31,7 +31,6 @@
 #define USER_DS                (2)
 #define USER_DS_SACF   (3)
 
-#define get_ds()        (KERNEL_DS)
 #define get_fs()        (current->thread.mm_segment)
 #define segment_eq(a,b) (((a) & 2) == ((b) & 2))
 
index 101c13c0c6adc0688380097e4c41837c41937903..33d1d28057cbfb37aa25896a88cbfa98596b09b9 100644 (file)
@@ -26,7 +26,6 @@ typedef struct {
 
 #define segment_eq(a, b) ((a).seg == (b).seg)
 
-#define get_ds()       (KERNEL_DS)
 
 #define get_fs()       (current_thread_info()->addr_limit)
 #define set_fs(x)      (current_thread_info()->addr_limit = (x))
index 5153798051fb2f0a3a529ec62e8f8fe9b7b7ff2e..d6d8413eca835aa325a892ad45ce792b9fedf014 100644 (file)
@@ -25,7 +25,6 @@
 #define KERNEL_DS   ((mm_segment_t) { 0 })
 #define USER_DS     ((mm_segment_t) { -1 })
 
-#define get_ds()       (KERNEL_DS)
 #define get_fs()       (current->thread.current_ds)
 #define set_fs(val)    ((current->thread.current_ds) = (val))
 
index 87ae9ffb1521b199ea57b477c4fc8fb789bf3dc3..bf9d330073b2352d571dde9093b60fd75ea06bea 100644 (file)
@@ -31,7 +31,6 @@
 #define USER_DS     ((mm_segment_t) { ASI_AIUS })      /* har har har */
 
 #define get_fs() ((mm_segment_t){(current_thread_info()->current_ds)})
-#define get_ds() (KERNEL_DS)
 
 #define segment_eq(a, b)  ((a).seg == (b).seg)
 
index 705dafc2d11ab5bb9ddf3b249e0a69dae31a966e..2bdbbbcfa393fd6b2df936029917d20dc4ae8e84 100644 (file)
@@ -841,7 +841,7 @@ union hv_gpa_page_range {
  * count is equal with how many entries of union hv_gpa_page_range can
  * be populated into the input parameter page.
  */
-#define HV_MAX_FLUSH_REP_COUNT (PAGE_SIZE - 2 * sizeof(u64) /  \
+#define HV_MAX_FLUSH_REP_COUNT ((PAGE_SIZE - 2 * sizeof(u64)) /        \
                                sizeof(union hv_gpa_page_range))
 
 struct hv_guest_mapping_flush_list {
index 780f2b42c8efe76b5d78291d4b633dd26b6e5c64..5e49a0acb5eeb194fa892baebf01f4c0bfbfc531 100644 (file)
@@ -25,7 +25,6 @@
 #define KERNEL_DS      MAKE_MM_SEG(-1UL)
 #define USER_DS        MAKE_MM_SEG(TASK_SIZE_MAX)
 
-#define get_ds()       (KERNEL_DS)
 #define get_fs()       (current->thread.addr_limit)
 static inline void set_fs(mm_segment_t fs)
 {
@@ -284,7 +283,7 @@ do {                                                                        \
                __put_user_goto(x, ptr, "l", "k", "ir", label);         \
                break;                                                  \
        case 8:                                                         \
-               __put_user_goto_u64((__typeof__(*ptr))(x), ptr, label); \
+               __put_user_goto_u64(x, ptr, label);                     \
                break;                                                  \
        default:                                                        \
                __put_user_bad();                                       \
@@ -431,8 +430,10 @@ do {                                                                       \
 ({                                                             \
        __label__ __pu_label;                                   \
        int __pu_err = -EFAULT;                                 \
+       __typeof__(*(ptr)) __pu_val;                            \
+       __pu_val = x;                                           \
        __uaccess_begin();                                      \
-       __put_user_size((x), (ptr), (size), __pu_label);        \
+       __put_user_size(__pu_val, (ptr), (size), __pu_label);   \
        __pu_err = 0;                                           \
 __pu_label:                                                    \
        __uaccess_end();                                        \
index 6521134057e8f9ef34dbfaf8a0a4e46672a32d3c..3c4568f8fb28e4c9dc2ab49a026a9cd336b57e9e 100644 (file)
@@ -117,67 +117,12 @@ __visible bool ex_handler_fprestore(const struct exception_table_entry *fixup,
 }
 EXPORT_SYMBOL_GPL(ex_handler_fprestore);
 
-/* Helper to check whether a uaccess fault indicates a kernel bug. */
-static bool bogus_uaccess(struct pt_regs *regs, int trapnr,
-                         unsigned long fault_addr)
-{
-       /* This is the normal case: #PF with a fault address in userspace. */
-       if (trapnr == X86_TRAP_PF && fault_addr < TASK_SIZE_MAX)
-               return false;
-
-       /*
-        * This code can be reached for machine checks, but only if the #MC
-        * handler has already decided that it looks like a candidate for fixup.
-        * This e.g. happens when attempting to access userspace memory which
-        * the CPU can't access because of uncorrectable bad memory.
-        */
-       if (trapnr == X86_TRAP_MC)
-               return false;
-
-       /*
-        * There are two remaining exception types we might encounter here:
-        *  - #PF for faulting accesses to kernel addresses
-        *  - #GP for faulting accesses to noncanonical addresses
-        * Complain about anything else.
-        */
-       if (trapnr != X86_TRAP_PF && trapnr != X86_TRAP_GP) {
-               WARN(1, "unexpected trap %d in uaccess\n", trapnr);
-               return false;
-       }
-
-       /*
-        * This is a faulting memory access in kernel space, on a kernel
-        * address, in a usercopy function. This can e.g. be caused by improper
-        * use of helpers like __put_user and by improper attempts to access
-        * userspace addresses in KERNEL_DS regions.
-        * The one (semi-)legitimate exception are probe_kernel_{read,write}(),
-        * which can be invoked from places like kgdb, /dev/mem (for reading)
-        * and privileged BPF code (for reading).
-        * The probe_kernel_*() functions set the kernel_uaccess_faults_ok flag
-        * to tell us that faulting on kernel addresses, and even noncanonical
-        * addresses, in a userspace accessor does not necessarily imply a
-        * kernel bug, root might just be doing weird stuff.
-        */
-       if (current->kernel_uaccess_faults_ok)
-               return false;
-
-       /* This is bad. Refuse the fixup so that we go into die(). */
-       if (trapnr == X86_TRAP_PF) {
-               pr_emerg("BUG: pagefault on kernel address 0x%lx in non-whitelisted uaccess\n",
-                        fault_addr);
-       } else {
-               pr_emerg("BUG: GPF in non-whitelisted uaccess (non-canonical address?)\n");
-       }
-       return true;
-}
-
 __visible bool ex_handler_uaccess(const struct exception_table_entry *fixup,
                                  struct pt_regs *regs, int trapnr,
                                  unsigned long error_code,
                                  unsigned long fault_addr)
 {
-       if (bogus_uaccess(regs, trapnr, fault_addr))
-               return false;
+       WARN_ONCE(trapnr == X86_TRAP_GP, "General protection fault in user access. Non-canonical address?");
        regs->ip = ex_fixup_addr(fixup);
        return true;
 }
@@ -188,8 +133,6 @@ __visible bool ex_handler_ext(const struct exception_table_entry *fixup,
                              unsigned long error_code,
                              unsigned long fault_addr)
 {
-       if (bogus_uaccess(regs, trapnr, fault_addr))
-               return false;
        /* Special hack for uaccess_err */
        current->thread.uaccess_err = 1;
        regs->ip = ex_fixup_addr(fixup);
index dfdf9fae1f84bc9f971b1caf861cfdbeb07a08b6..7f6cf4151843abea3b591e5536762f155a7cb5ff 100644 (file)
@@ -32,8 +32,6 @@
 #define KERNEL_DS      0
 #define USER_DS                1
 
-#define get_ds         (KERNEL_DS)
-
 /*
  * get_fs reads current->thread.current_ds into a register.
  * On Entry:
index 4b2480304bc311ffd8c1769efa885a2b78e65357..6792928ba84a7bb16d20a661f5070d0676e2f6b6 100644 (file)
@@ -32,7 +32,6 @@
 #define KERNEL_DS      ((mm_segment_t) { 0 })
 #define USER_DS                ((mm_segment_t) { 1 })
 
-#define get_ds()       (KERNEL_DS)
 #define get_fs()       (current->thread.current_ds)
 #define set_fs(val)    (current->thread.current_ds = (val))
 
index f6262435702094effeb6356bf5636728ffb06fd2..907a6db4d6c036fe1c5433d5bda095d157e166b0 100644 (file)
@@ -30,7 +30,7 @@ static inline int cc_pm_init(struct cc_drvdata *drvdata)
        return 0;
 }
 
-static void cc_pm_go(struct cc_drvdata *drvdata) {}
+static inline void cc_pm_go(struct cc_drvdata *drvdata) {}
 
 static inline void cc_pm_fini(struct cc_drvdata *drvdata) {}
 
index aadd0fa42e430d02bfb386152f5510fc332183e3..3aa42c64484af5bd665b0f1b82fe1db9e170aa39 100644 (file)
@@ -405,6 +405,7 @@ struct amdgpu_crtc {
        struct amdgpu_flip_work *pflip_works;
        enum amdgpu_flip_status pflip_status;
        int deferred_flip_completion;
+       u64 last_flip_vblank;
        /* pll sharing */
        struct amdgpu_atom_ss ss;
        bool ss_enabled;
index 5296b8f3e0ab369377a5d7c3cad8014dbead02b9..636d14a609525732b1c4ef3fca4d772e2bafb253 100644 (file)
@@ -303,12 +303,11 @@ static void dm_pflip_high_irq(void *interrupt_params)
                return;
        }
 
+       /* Update to correct count(s) if racing with vblank irq */
+       amdgpu_crtc->last_flip_vblank = drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 
        /* wake up userspace */
        if (amdgpu_crtc->event) {
-               /* Update to correct count(s) if racing with vblank irq */
-               drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
-
                drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
 
                /* page flip completed. clean up */
@@ -4828,6 +4827,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                        to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
        int planes_count = 0;
        unsigned long flags;
+       u64 last_flip_vblank;
+       bool vrr_active = acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE;
 
        /* update planes when needed */
        for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
@@ -4859,6 +4860,16 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                        /* In commit tail framework this cannot happen */
                        WARN_ON(1);
                }
+
+               /* For variable refresh rate mode only:
+                * Get vblank of last completed flip to avoid > 1 vrr flips per
+                * video frame by use of throttling, but allow flip programming
+                * anywhere in the possibly large variable vrr vblank interval
+                * for fine-grained flip timing control and more opportunity to
+                * avoid stutter on late submission of amdgpu_dm_do_flip() calls.
+                */
+               last_flip_vblank = acrtc_attach->last_flip_vblank;
+
                spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 
                if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
@@ -4882,10 +4893,18 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                        if (plane->type == DRM_PLANE_TYPE_PRIMARY)
                                drm_crtc_vblank_get(crtc);
 
+                       /* Use old throttling in non-vrr fixed refresh rate mode
+                        * to keep flip scheduling based on target vblank counts
+                        * working in a backwards compatible way, e.g., clients
+                        * using GLX_OML_sync_control extension.
+                        */
+                       if (!vrr_active)
+                               last_flip_vblank = drm_crtc_vblank_count(crtc);
+
                        amdgpu_dm_do_flip(
                                crtc,
                                fb,
-                               (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
+                               (uint32_t) last_flip_vblank + *wait_for_vblank,
                                dc_state);
                }
 
index f3dd66ae990aebc8a9518127f74d63c1ee98b252..aa35007262cdb995f4ddba8392ca6da20b100a9a 100644 (file)
@@ -154,6 +154,10 @@ static int bochs_pci_probe(struct pci_dev *pdev,
        if (IS_ERR(dev))
                return PTR_ERR(dev);
 
+       ret = pci_enable_device(pdev);
+       if (ret)
+               goto err_free_dev;
+
        dev->pdev = pdev;
        pci_set_drvdata(pdev, dev);
 
index 54e2ae614dccb4e94187df67abfebf776962f2a6..f4290f6b0c38304b86cd84478fa60f6bcbe302e5 100644 (file)
@@ -1602,6 +1602,15 @@ int drm_atomic_helper_async_check(struct drm_device *dev,
            old_plane_state->crtc != new_plane_state->crtc)
                return -EINVAL;
 
+       /*
+        * FIXME: Since prepare_fb and cleanup_fb are always called on
+        * the new_plane_state for async updates we need to block framebuffer
+        * changes. This prevents use of a fb that's been cleaned up and
+        * double cleanups from occuring.
+        */
+       if (old_plane_state->fb != new_plane_state->fb)
+               return -EINVAL;
+
        funcs = plane->helper_private;
        if (!funcs->atomic_async_update)
                return -EINVAL;
index bb03079fbade164806047e17aa697c0f886bd5b0..59279224e07fcefa460b1939212a5009eb8a3681 100644 (file)
@@ -602,6 +602,7 @@ static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
                ret = dw_i2c_clk_cfg(master);
                if (ret)
                        return ret;
+               /* fall through */
        case I3C_BUS_MODE_PURE:
                ret = dw_i3c_clk_cfg(master);
                if (ret)
index dc9f14811e0f4d9ed3a12936501274ad55789a55..58dc70bffd5b87ec682984e3a9e8842b5dcfb68d 100644 (file)
@@ -144,7 +144,7 @@ dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
                for (tmp = dev; tmp; tmp = tmp->bus->self)
                        level++;
 
-       size = sizeof(*info) + level * sizeof(struct acpi_dmar_pci_path);
+       size = sizeof(*info) + level * sizeof(info->path[0]);
        if (size <= sizeof(dmar_pci_notify_info_buf)) {
                info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
        } else {
index 6e8e7b1bb34b65a4196c7979aa8d1ca10a9f2f07..79a53cb8507b69a6102c8ac7e9d7716eb58dc021 100644 (file)
@@ -756,7 +756,8 @@ static int cfi_intelext_partition_fixup(struct mtd_info *mtd,
                }
 
                numvirtchips = cfi->numchips * numparts;
-               newcfi = kmalloc(sizeof(struct cfi_private) + numvirtchips * sizeof(struct flchip), GFP_KERNEL);
+               newcfi = kmalloc(struct_size(newcfi, chips, numvirtchips),
+                                GFP_KERNEL);
                if (!newcfi)
                        return -ENOMEM;
                shared = kmalloc_array(cfi->numchips,
index 837b04ab96a9c526f19699655cfa9ee174bd190b..839ed40625d6bbd94c7d1de5c6aa5260f3fa4388 100644 (file)
@@ -135,7 +135,7 @@ static struct cfi_private *genprobe_ident_chips(struct map_info *map, struct chi
         * our caller, and copy the appropriate data into them.
         */
 
-       retcfi = kmalloc(sizeof(struct cfi_private) + cfi.numchips * sizeof(struct flchip), GFP_KERNEL);
+       retcfi = kmalloc(struct_size(retcfi, chips, cfi.numchips), GFP_KERNEL);
 
        if (!retcfi) {
                kfree(cfi.cfiq);
index 4c94fc0966964b8c15aefc086cd5ecb8174f7d27..7754803e34639a79bbe49c16617a03339acb097a 100644 (file)
@@ -1767,8 +1767,8 @@ static int __init doc_set_driver_info(int chip_id, struct mtd_info *mtd)
 
        switch (chip_id) {
        case DOC_CHIPID_G3:
-               mtd->name = kasprintf(GFP_KERNEL, "docg3.%d",
-                                     docg3->device_id);
+               mtd->name = devm_kasprintf(docg3->dev, GFP_KERNEL, "docg3.%d",
+                                          docg3->device_id);
                if (!mtd->name)
                        return -ENOMEM;
                docg3->max_block = 2047;
@@ -1872,7 +1872,7 @@ nomem3:
 nomem2:
        kfree(docg3);
 nomem1:
-       return ERR_PTR(ret);
+       return ret ? ERR_PTR(ret) : NULL;
 }
 
 /**
@@ -1886,7 +1886,6 @@ static void doc_release_device(struct mtd_info *mtd)
        mtd_device_unregister(mtd);
        kfree(docg3->bbt);
        kfree(docg3);
-       kfree(mtd->name);
        kfree(mtd);
 }
 
index c4a1d04b8c800d1b090e99dc9975025d4b61009c..651bab6d4e31bea8c68f0461a3aefedf21e01fc7 100644 (file)
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
        spi_mem_set_drvdata(spimem, flash);
        flash->spimem = spimem;
 
-       if (spi->mode & SPI_RX_QUAD) {
+       if (spi->mode & SPI_RX_OCTAL) {
+               hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+               if (spi->mode & SPI_TX_OCTAL)
+                       hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+                                       SNOR_HWCAPS_PP_1_1_8 |
+                                       SNOR_HWCAPS_PP_1_8_8);
+       } else if (spi->mode & SPI_RX_QUAD) {
                hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 
                if (spi->mode & SPI_TX_QUAD)
index 46238796145ffad93092197b7dc76fa0ae9c91ef..1c97fabc4bf9bf8739b90a696d05bde14f0de21c 100644 (file)
@@ -24,14 +24,12 @@ static unsigned long writebuf_size = 64;
 #define MTDRAM_TOTAL_SIZE (total_size * 1024)
 #define MTDRAM_ERASE_SIZE (erase_size * 1024)
 
-#ifdef MODULE
 module_param(total_size, ulong, 0);
 MODULE_PARM_DESC(total_size, "Total device size in KiB");
 module_param(erase_size, ulong, 0);
 MODULE_PARM_DESC(erase_size, "Device erase block size in KiB");
 module_param(writebuf_size, ulong, 0);
 MODULE_PARM_DESC(writebuf_size, "Device write buf size in Bytes (Default: 64)");
-#endif
 
 // We could store these in the mtd structure, but we only support 1 device..
 static struct mtd_info *mtd_info;
index 69f2112340b19dc94639ff90bd87114490767168..175bdc3b72f4efb56b56221ae644122642f7bfe7 100644 (file)
@@ -181,8 +181,8 @@ static struct lpddr_private *lpddr_probe_chip(struct map_info *map)
        lpddr.numchips = 1;
 
        numvirtchips = lpddr.numchips * lpddr.qinfo->HWPartsNum;
-       retlpddr = kzalloc(sizeof(struct lpddr_private) +
-                       numvirtchips * sizeof(struct flchip), GFP_KERNEL);
+       retlpddr = kzalloc(struct_size(retlpddr, chips, numvirtchips),
+                          GFP_KERNEL);
        if (!retlpddr)
                return NULL;
 
index 3ef01baef9b62d1085de674b43f6310fbdc62821..76b4264936ff8bee1bc2f9c7ce848ac70074d4e6 100644 (file)
@@ -155,7 +155,6 @@ static ssize_t mtd_flags_show(struct device *dev,
        struct mtd_info *mtd = dev_get_drvdata(dev);
 
        return snprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)mtd->flags);
-
 }
 static DEVICE_ATTR(flags, S_IRUGO, mtd_flags_show, NULL);
 
@@ -166,7 +165,6 @@ static ssize_t mtd_size_show(struct device *dev,
 
        return snprintf(buf, PAGE_SIZE, "%llu\n",
                (unsigned long long)mtd->size);
-
 }
 static DEVICE_ATTR(size, S_IRUGO, mtd_size_show, NULL);
 
@@ -176,7 +174,6 @@ static ssize_t mtd_erasesize_show(struct device *dev,
        struct mtd_info *mtd = dev_get_drvdata(dev);
 
        return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->erasesize);
-
 }
 static DEVICE_ATTR(erasesize, S_IRUGO, mtd_erasesize_show, NULL);
 
@@ -186,7 +183,6 @@ static ssize_t mtd_writesize_show(struct device *dev,
        struct mtd_info *mtd = dev_get_drvdata(dev);
 
        return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->writesize);
-
 }
 static DEVICE_ATTR(writesize, S_IRUGO, mtd_writesize_show, NULL);
 
@@ -197,7 +193,6 @@ static ssize_t mtd_subpagesize_show(struct device *dev,
        unsigned int subpagesize = mtd->writesize >> mtd->subpage_sft;
 
        return snprintf(buf, PAGE_SIZE, "%u\n", subpagesize);
-
 }
 static DEVICE_ATTR(subpagesize, S_IRUGO, mtd_subpagesize_show, NULL);
 
@@ -207,7 +202,6 @@ static ssize_t mtd_oobsize_show(struct device *dev,
        struct mtd_info *mtd = dev_get_drvdata(dev);
 
        return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->oobsize);
-
 }
 static DEVICE_ATTR(oobsize, S_IRUGO, mtd_oobsize_show, NULL);
 
@@ -226,7 +220,6 @@ static ssize_t mtd_numeraseregions_show(struct device *dev,
        struct mtd_info *mtd = dev_get_drvdata(dev);
 
        return snprintf(buf, PAGE_SIZE, "%u\n", mtd->numeraseregions);
-
 }
 static DEVICE_ATTR(numeraseregions, S_IRUGO, mtd_numeraseregions_show,
        NULL);
@@ -237,7 +230,6 @@ static ssize_t mtd_name_show(struct device *dev,
        struct mtd_info *mtd = dev_get_drvdata(dev);
 
        return snprintf(buf, PAGE_SIZE, "%s\n", mtd->name);
-
 }
 static DEVICE_ATTR(name, S_IRUGO, mtd_name_show, NULL);
 
@@ -560,6 +552,14 @@ int add_mtd_device(struct mtd_info *mtd)
 
        BUG_ON(mtd->writesize == 0);
 
+       /*
+        * MTD drivers should implement ->_{write,read}() or
+        * ->_{write,read}_oob(), but not both.
+        */
+       if (WARN_ON((mtd->_write && mtd->_write_oob) ||
+                   (mtd->_read && mtd->_read_oob)))
+               return -EINVAL;
+
        if (WARN_ON((!mtd->erasesize || !mtd->_erase) &&
                    !(mtd->flags & MTD_NO_ERASE)))
                return -EINVAL;
@@ -1090,67 +1090,32 @@ EXPORT_SYMBOL_GPL(mtd_get_unmapped_area);
 int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
             u_char *buf)
 {
-       int ret_code;
-       *retlen = 0;
-       if (from < 0 || from >= mtd->size || len > mtd->size - from)
-               return -EINVAL;
-       if (!len)
-               return 0;
+       struct mtd_oob_ops ops = {
+               .len = len,
+               .datbuf = buf,
+       };
+       int ret;
 
-       ledtrig_mtd_activity();
-       /*
-        * In the absence of an error, drivers return a non-negative integer
-        * representing the maximum number of bitflips that were corrected on
-        * any one ecc region (if applicable; zero otherwise).
-        */
-       if (mtd->_read) {
-               ret_code = mtd->_read(mtd, from, len, retlen, buf);
-       } else if (mtd->_read_oob) {
-               struct mtd_oob_ops ops = {
-                       .len = len,
-                       .datbuf = buf,
-               };
-
-               ret_code = mtd->_read_oob(mtd, from, &ops);
-               *retlen = ops.retlen;
-       } else {
-               return -ENOTSUPP;
-       }
+       ret = mtd_read_oob(mtd, from, &ops);
+       *retlen = ops.retlen;
 
-       if (unlikely(ret_code < 0))
-               return ret_code;
-       if (mtd->ecc_strength == 0)
-               return 0;       /* device lacks ecc */
-       return ret_code >= mtd->bitflip_threshold ? -EUCLEAN : 0;
+       return ret;
 }
 EXPORT_SYMBOL_GPL(mtd_read);
 
 int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
              const u_char *buf)
 {
-       *retlen = 0;
-       if (to < 0 || to >= mtd->size || len > mtd->size - to)
-               return -EINVAL;
-       if ((!mtd->_write && !mtd->_write_oob) ||
-           !(mtd->flags & MTD_WRITEABLE))
-               return -EROFS;
-       if (!len)
-               return 0;
-       ledtrig_mtd_activity();
+       struct mtd_oob_ops ops = {
+               .len = len,
+               .datbuf = (u8 *)buf,
+       };
+       int ret;
 
-       if (!mtd->_write) {
-               struct mtd_oob_ops ops = {
-                       .len = len,
-                       .datbuf = (u8 *)buf,
-               };
-               int ret;
+       ret = mtd_write_oob(mtd, to, &ops);
+       *retlen = ops.retlen;
 
-               ret = mtd->_write_oob(mtd, to, &ops);
-               *retlen = ops.retlen;
-               return ret;
-       }
-
-       return mtd->_write(mtd, to, len, retlen, buf);
+       return ret;
 }
 EXPORT_SYMBOL_GPL(mtd_write);
 
index 1a55d3e3d4c5d6f4aee59f92a5446105151caf69..e604625e2dfa402c783d14266e8a201de81ee7d2 100644 (file)
@@ -541,4 +541,21 @@ config MTD_NAND_TEGRA
          is supported. Extra OOB bytes when using HW ECC are currently
          not supported.
 
+config MTD_NAND_STM32_FMC2
+       tristate "Support for NAND controller on STM32MP SoCs"
+       depends on MACH_STM32MP157 || COMPILE_TEST
+       help
+         Enables support for NAND Flash chips on SoCs containing the FMC2
+         NAND controller. This controller is found on STM32MP SoCs.
+         The controller supports a maximum 8k page size and supports
+         a maximum 8-bit correction error per sector of 512 bytes.
+
+config MTD_NAND_MESON
+       tristate "Support for NAND controller on Amlogic's Meson SoCs"
+       depends on ARCH_MESON || COMPILE_TEST
+       select MFD_SYSCON
+       help
+         Enables support for NAND controller on Amlogic's Meson SoCs.
+         This controller is found on Meson SoCs.
+
 endif # MTD_NAND
index 57159b349054ddf2065890326a5809633f8c4f16..5a5a72f0793eb2765fe954ea3c7d1e85bb444c0f 100644 (file)
@@ -56,6 +56,8 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND)               += brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)            += qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK)             += mtk_ecc.o mtk_nand.o
 obj-$(CONFIG_MTD_NAND_TEGRA)           += tegra_nand.o
+obj-$(CONFIG_MTD_NAND_STM32_FMC2)      += stm32_fmc2_nand.o
+obj-$(CONFIG_MTD_NAND_MESON)           += meson_nand.o
 
 nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_onfi.o
index 555a74e15269da45f2b4685dcd149cfd88f47438..9d3997840889b2b3139e54ecbd0729cf507f74ae 100644 (file)
@@ -876,23 +876,32 @@ static struct atmel_pmecc *atmel_pmecc_get_by_node(struct device *userdev,
 {
        struct platform_device *pdev;
        struct atmel_pmecc *pmecc, **ptr;
+       int ret;
 
        pdev = of_find_device_by_node(np);
-       if (!pdev || !platform_get_drvdata(pdev))
+       if (!pdev)
                return ERR_PTR(-EPROBE_DEFER);
+       pmecc = platform_get_drvdata(pdev);
+       if (!pmecc) {
+               ret = -EPROBE_DEFER;
+               goto err_put_device;
+       }
 
        ptr = devres_alloc(devm_atmel_pmecc_put, sizeof(*ptr), GFP_KERNEL);
-       if (!ptr)
-               return ERR_PTR(-ENOMEM);
-
-       get_device(&pdev->dev);
-       pmecc = platform_get_drvdata(pdev);
+       if (!ptr) {
+               ret = -ENOMEM;
+               goto err_put_device;
+       }
 
        *ptr = pmecc;
 
        devres_add(userdev, ptr);
 
        return pmecc;
+
+err_put_device:
+       put_device(&pdev->dev);
+       return ERR_PTR(ret);
 }
 
 static const int atmel_pmecc_strengths[] = { 2, 4, 8, 12, 24, 32 };
index 6e8edc9375dde933470541dc3123ae515965a2de..24aeafc67cd4ea9f1eeb79652074785b0b45446e 100644 (file)
@@ -37,9 +37,6 @@
 #define DENALI_MAP11_ADDR      ((DENALI_MAP11) | 1)    /* address cycle */
 #define DENALI_MAP11_DATA      ((DENALI_MAP11) | 2)    /* data cycle */
 
-/* MAP10 commands */
-#define DENALI_ERASE           0x01
-
 #define DENALI_BANK(denali)    ((denali)->active_bank << 24)
 
 #define DENALI_INVALID_BANK    -1
@@ -476,7 +473,7 @@ static void denali_setup_dma32(struct denali_nand_info *denali,
 }
 
 static int denali_pio_read(struct denali_nand_info *denali, void *buf,
-                          size_t size, int page, int raw)
+                          size_t size, int page)
 {
        u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
        uint32_t *buf32 = (uint32_t *)buf;
@@ -504,7 +501,7 @@ static int denali_pio_read(struct denali_nand_info *denali, void *buf,
 }
 
 static int denali_pio_write(struct denali_nand_info *denali,
-                           const void *buf, size_t size, int page, int raw)
+                           const void *buf, size_t size, int page)
 {
        u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
        const uint32_t *buf32 = (uint32_t *)buf;
@@ -525,16 +522,16 @@ static int denali_pio_write(struct denali_nand_info *denali,
 }
 
 static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
-                          size_t size, int page, int raw, int write)
+                          size_t size, int page, int write)
 {
        if (write)
-               return denali_pio_write(denali, buf, size, page, raw);
+               return denali_pio_write(denali, buf, size, page);
        else
-               return denali_pio_read(denali, buf, size, page, raw);
+               return denali_pio_read(denali, buf, size, page);
 }
 
 static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
-                          size_t size, int page, int raw, int write)
+                          size_t size, int page, int write)
 {
        dma_addr_t dma_addr;
        uint32_t irq_mask, irq_status, ecc_err_mask;
@@ -544,7 +541,7 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
        dma_addr = dma_map_single(denali->dev, buf, size, dir);
        if (dma_mapping_error(denali->dev, dma_addr)) {
                dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
-               return denali_pio_xfer(denali, buf, size, page, raw, write);
+               return denali_pio_xfer(denali, buf, size, page, write);
        }
 
        if (write) {
@@ -598,9 +595,9 @@ static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
                  denali->reg + TRANSFER_SPARE_REG);
 
        if (denali->dma_avail)
-               return denali_dma_xfer(denali, buf, size, page, raw, write);
+               return denali_dma_xfer(denali, buf, size, page, write);
        else
-               return denali_pio_xfer(denali, buf, size, page, raw, write);
+               return denali_pio_xfer(denali, buf, size, page, write);
 }
 
 static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
@@ -754,9 +751,6 @@ static int denali_read_oob(struct nand_chip *chip, int page)
 static int denali_write_oob(struct nand_chip *chip, int page)
 {
        struct mtd_info *mtd = nand_to_mtd(chip);
-       struct denali_nand_info *denali = mtd_to_denali(mtd);
-
-       denali_reset_irq(denali);
 
        denali_oob_xfer(mtd, chip, page, 1);
 
@@ -903,23 +897,6 @@ static int denali_waitfunc(struct nand_chip *chip)
        return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
 }
 
-static int denali_erase(struct nand_chip *chip, int page)
-{
-       struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
-       uint32_t irq_status;
-
-       denali_reset_irq(denali);
-
-       denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
-                          DENALI_ERASE);
-
-       /* wait for erase to complete or failure to occur */
-       irq_status = denali_wait_for_irq(denali,
-                                        INTR__ERASE_COMP | INTR__ERASE_FAIL);
-
-       return irq_status & INTR__ERASE_COMP ? 0 : -EIO;
-}
-
 static int denali_setup_data_interface(struct nand_chip *chip, int chipnr,
                                       const struct nand_data_interface *conf)
 {
@@ -1244,7 +1221,6 @@ static int denali_attach_chip(struct nand_chip *chip)
        chip->ecc.write_page_raw = denali_write_page_raw;
        chip->ecc.read_oob = denali_read_oob;
        chip->ecc.write_oob = denali_write_oob;
-       chip->legacy.erase = denali_erase;
 
        ret = denali_multidev_fixup(denali);
        if (ret)
index 25c00601b8b34fdc0c9d45689781384979100da2..c8c2620fc736b07b3707317fed7fefe883b5e3d6 100644 (file)
@@ -304,7 +304,6 @@ struct denali_nand_info {
        u32 irq_status;                 /* interrupts that have happened */
        int irq;
        void *buf;                      /* for syndrome layout conversion */
-       dma_addr_t dma_addr;
        int dma_avail;                  /* can support DMA? */
        int devs_per_cs;                /* devices connected in parallel */
        int oob_skip_bytes;             /* number of bytes reserved for BBM */
index 7c6a8a426606afdf37ff59e63108c262437a4017..0b5ae2418815b66fd7379a2f3ef8f056e1e3b5bd 100644 (file)
@@ -109,25 +109,17 @@ static int denali_dt_probe(struct platform_device *pdev)
        if (IS_ERR(denali->host))
                return PTR_ERR(denali->host);
 
-       /*
-        * A single anonymous clock is supported for the backward compatibility.
-        * New platforms should support all the named clocks.
-        */
        dt->clk = devm_clk_get(dev, "nand");
        if (IS_ERR(dt->clk))
-               dt->clk = devm_clk_get(dev, NULL);
-       if (IS_ERR(dt->clk)) {
-               dev_err(dev, "no clk available\n");
                return PTR_ERR(dt->clk);
-       }
 
        dt->clk_x = devm_clk_get(dev, "nand_x");
        if (IS_ERR(dt->clk_x))
-               dt->clk_x = NULL;
+               return PTR_ERR(dt->clk_x);
 
        dt->clk_ecc = devm_clk_get(dev, "ecc");
        if (IS_ERR(dt->clk_ecc))
-               dt->clk_ecc = NULL;
+               return PTR_ERR(dt->clk_ecc);
 
        ret = clk_prepare_enable(dt->clk);
        if (ret)
@@ -141,19 +133,8 @@ static int denali_dt_probe(struct platform_device *pdev)
        if (ret)
                goto out_disable_clk_x;
 
-       if (dt->clk_x) {
-               denali->clk_rate = clk_get_rate(dt->clk);
-               denali->clk_x_rate = clk_get_rate(dt->clk_x);
-       } else {
-               /*
-                * Hardcode the clock rates for the backward compatibility.
-                * This works for both SOCFPGA and UniPhier.
-                */
-               dev_notice(dev,
-                          "necessary clock is missing. default clock rates are used.\n");
-               denali->clk_rate = 50000000;
-               denali->clk_x_rate = 200000000;
-       }
+       denali->clk_rate = clk_get_rate(dt->clk);
+       denali->clk_x_rate = clk_get_rate(dt->clk_x);
 
        ret = denali_init(denali);
        if (ret)
index c9149a37f8f0a16c40ed9fdd7989dad7403c1680..6c7ca41354be64f8efeee787d419175e384b9e7c 100644 (file)
@@ -965,6 +965,19 @@ static const struct nand_controller_ops fsmc_nand_controller_ops = {
        .setup_data_interface = fsmc_setup_data_interface,
 };
 
+/**
+ * fsmc_nand_disable() - Disables the NAND bank
+ * @host: The instance to disable
+ */
+static void fsmc_nand_disable(struct fsmc_nand_data *host)
+{
+       u32 val;
+
+       val = readl(host->regs_va + FSMC_PC);
+       val &= ~FSMC_ENABLE;
+       writel(val, host->regs_va + FSMC_PC);
+}
+
 /*
  * fsmc_nand_probe - Probe function
  * @pdev:       platform device structure
@@ -1120,6 +1133,7 @@ release_dma_read_chan:
        if (host->mode == USE_DMA_ACCESS)
                dma_release_channel(host->read_dma_chan);
 disable_clk:
+       fsmc_nand_disable(host);
        clk_disable_unprepare(host->clk);
 
        return ret;
@@ -1134,6 +1148,7 @@ static int fsmc_nand_remove(struct platform_device *pdev)
 
        if (host) {
                nand_release(&host->nand);
+               fsmc_nand_disable(host);
 
                if (host->mode == USE_DMA_ACCESS) {
                        dma_release_channel(host->write_dma_chan);
@@ -1164,6 +1179,7 @@ static int fsmc_nand_resume(struct device *dev)
                clk_prepare_enable(host->clk);
                if (host->dev_timings)
                        fsmc_nand_setup(host, host->dev_timings);
+               nand_reset(&host->nand, 0);
        }
 
        return 0;
index 7201827809e9aa461b5662a17f0e297c7379997d..c5f74ed85862679e1ea6b6cdc15b95d45e11b2ec 100644 (file)
@@ -281,12 +281,15 @@ static struct jz4780_bch *jz4780_bch_get(struct device_node *np)
        struct jz4780_bch *bch;
 
        pdev = of_find_device_by_node(np);
-       if (!pdev || !platform_get_drvdata(pdev))
+       if (!pdev)
                return ERR_PTR(-EPROBE_DEFER);
 
-       get_device(&pdev->dev);
-
        bch = platform_get_drvdata(pdev);
+       if (!bch) {
+               put_device(&pdev->dev);
+               return ERR_PTR(-EPROBE_DEFER);
+       }
+
        clk_prepare_enable(bch->clk);
 
        return bch;
index 84283c6bb0ff9dc12a99857e3c6dc9c0ad5e855b..f38e5c1b87e474557a1bc0392f6a7ea3b51638cf 100644 (file)
@@ -2550,9 +2550,8 @@ static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
        }
 
        /* Alloc the nand chip structure */
-       marvell_nand = devm_kzalloc(dev, sizeof(*marvell_nand) +
-                                   (nsels *
-                                    sizeof(struct marvell_nand_chip_sel)),
+       marvell_nand = devm_kzalloc(dev,
+                                   struct_size(marvell_nand, sels, nsels),
                                    GFP_KERNEL);
        if (!marvell_nand) {
                dev_err(dev, "could not allocate chip structure\n");
diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
new file mode 100644 (file)
index 0000000..3e8aa71
--- /dev/null
@@ -0,0 +1,1464 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Amlogic Meson Nand Flash Controller Driver
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Liang Yang <liang.yang@amlogic.com>
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/iopoll.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/sched/task_stack.h>
+
+#define NFC_REG_CMD            0x00
+#define NFC_CMD_IDLE           (0xc << 14)
+#define NFC_CMD_CLE            (0x5 << 14)
+#define NFC_CMD_ALE            (0x6 << 14)
+#define NFC_CMD_ADL            ((0 << 16) | (3 << 20))
+#define NFC_CMD_ADH            ((1 << 16) | (3 << 20))
+#define NFC_CMD_AIL            ((2 << 16) | (3 << 20))
+#define NFC_CMD_AIH            ((3 << 16) | (3 << 20))
+#define NFC_CMD_SEED           ((8 << 16) | (3 << 20))
+#define NFC_CMD_M2N            ((0 << 17) | (2 << 20))
+#define NFC_CMD_N2M            ((1 << 17) | (2 << 20))
+#define NFC_CMD_RB             BIT(20)
+#define NFC_CMD_SCRAMBLER_ENABLE       BIT(19)
+#define NFC_CMD_SCRAMBLER_DISABLE      0
+#define NFC_CMD_SHORTMODE_DISABLE      0
+#define NFC_CMD_RB_INT         BIT(14)
+
+#define NFC_CMD_GET_SIZE(x)    (((x) >> 22) & GENMASK(4, 0))
+
+#define NFC_REG_CFG            0x04
+#define NFC_REG_DADR           0x08
+#define NFC_REG_IADR           0x0c
+#define NFC_REG_BUF            0x10
+#define NFC_REG_INFO           0x14
+#define NFC_REG_DC             0x18
+#define NFC_REG_ADR            0x1c
+#define NFC_REG_DL             0x20
+#define NFC_REG_DH             0x24
+#define NFC_REG_CADR           0x28
+#define NFC_REG_SADR           0x2c
+#define NFC_REG_PINS           0x30
+#define NFC_REG_VER            0x38
+
+#define NFC_RB_IRQ_EN          BIT(21)
+
+#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages)      \
+       (                                                               \
+               (cmd_dir)                       |                       \
+               ((ran) << 19)                   |                       \
+               ((bch) << 14)                   |                       \
+               ((short_mode) << 13)            |                       \
+               (((page_size) & 0x7f) << 6)     |                       \
+               ((pages) & 0x3f)                                        \
+       )
+
+#define GENCMDDADDRL(adl, addr)                ((adl) | ((addr) & 0xffff))
+#define GENCMDDADDRH(adh, addr)                ((adh) | (((addr) >> 16) & 0xffff))
+#define GENCMDIADDRL(ail, addr)                ((ail) | ((addr) & 0xffff))
+#define GENCMDIADDRH(aih, addr)                ((aih) | (((addr) >> 16) & 0xffff))
+
+#define DMA_DIR(dir)           ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N)
+
+#define ECC_CHECK_RETURN_FF    (-1)
+
+#define NAND_CE0               (0xe << 10)
+#define NAND_CE1               (0xd << 10)
+
+#define DMA_BUSY_TIMEOUT       0x100000
+#define CMD_FIFO_EMPTY_TIMEOUT 1000
+
+#define MAX_CE_NUM             2
+
+/* eMMC clock register, misc control */
+#define CLK_SELECT_NAND                BIT(31)
+
+#define NFC_CLK_CYCLE          6
+
+/* nand flash controller delay 3 ns */
+#define NFC_DEFAULT_DELAY      3000
+
+#define ROW_ADDER(page, index) (((page) >> (8 * (index))) & 0xff)
+#define MAX_CYCLE_ADDRS                5
+#define DIRREAD                        1
+#define DIRWRITE               0
+
+#define ECC_PARITY_BCH8_512B   14
+#define ECC_COMPLETE            BIT(31)
+#define ECC_ERR_CNT(x)         (((x) >> 24) & GENMASK(5, 0))
+#define ECC_ZERO_CNT(x)                (((x) >> 16) & GENMASK(5, 0))
+#define ECC_UNCORRECTABLE      0x3f
+
+#define PER_INFO_BYTE          8
+
+struct meson_nfc_nand_chip {
+       struct list_head node;
+       struct nand_chip nand;
+       unsigned long clk_rate;
+       unsigned long level1_divider;
+       u32 bus_timing;
+       u32 twb;
+       u32 tadl;
+       u32 tbers_max;
+
+       u32 bch_mode;
+       u8 *data_buf;
+       __le64 *info_buf;
+       u32 nsels;
+       u8 sels[0];
+};
+
+struct meson_nand_ecc {
+       u32 bch;
+       u32 strength;
+};
+
+struct meson_nfc_data {
+       const struct nand_ecc_caps *ecc_caps;
+};
+
+struct meson_nfc_param {
+       u32 chip_select;
+       u32 rb_select;
+};
+
+struct nand_rw_cmd {
+       u32 cmd0;
+       u32 addrs[MAX_CYCLE_ADDRS];
+       u32 cmd1;
+};
+
+struct nand_timing {
+       u32 twb;
+       u32 tadl;
+       u32 tbers_max;
+};
+
+struct meson_nfc {
+       struct nand_controller controller;
+       struct clk *core_clk;
+       struct clk *device_clk;
+       struct clk *phase_tx;
+       struct clk *phase_rx;
+
+       unsigned long clk_rate;
+       u32 bus_timing;
+
+       struct device *dev;
+       void __iomem *reg_base;
+       struct regmap *reg_clk;
+       struct completion completion;
+       struct list_head chips;
+       const struct meson_nfc_data *data;
+       struct meson_nfc_param param;
+       struct nand_timing timing;
+       union {
+               int cmd[32];
+               struct nand_rw_cmd rw;
+       } cmdfifo;
+
+       dma_addr_t daddr;
+       dma_addr_t iaddr;
+
+       unsigned long assigned_cs;
+};
+
+enum {
+       NFC_ECC_BCH8_1K         = 2,
+       NFC_ECC_BCH24_1K,
+       NFC_ECC_BCH30_1K,
+       NFC_ECC_BCH40_1K,
+       NFC_ECC_BCH50_1K,
+       NFC_ECC_BCH60_1K,
+};
+
+#define MESON_ECC_DATA(b, s)   { .bch = (b),   .strength = (s)}
+
+static struct meson_nand_ecc meson_ecc[] = {
+       MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8),
+       MESON_ECC_DATA(NFC_ECC_BCH24_1K, 24),
+       MESON_ECC_DATA(NFC_ECC_BCH30_1K, 30),
+       MESON_ECC_DATA(NFC_ECC_BCH40_1K, 40),
+       MESON_ECC_DATA(NFC_ECC_BCH50_1K, 50),
+       MESON_ECC_DATA(NFC_ECC_BCH60_1K, 60),
+};
+
+static int meson_nand_calc_ecc_bytes(int step_size, int strength)
+{
+       int ecc_bytes;
+
+       if (step_size == 512 && strength == 8)
+               return ECC_PARITY_BCH8_512B;
+
+       ecc_bytes = DIV_ROUND_UP(strength * fls(step_size * 8), 8);
+       ecc_bytes = ALIGN(ecc_bytes, 2);
+
+       return ecc_bytes;
+}
+
+NAND_ECC_CAPS_SINGLE(meson_gxl_ecc_caps,
+                    meson_nand_calc_ecc_bytes, 1024, 8, 24, 30, 40, 50, 60);
+NAND_ECC_CAPS_SINGLE(meson_axg_ecc_caps,
+                    meson_nand_calc_ecc_bytes, 1024, 8);
+
+static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand)
+{
+       return container_of(nand, struct meson_nfc_nand_chip, nand);
+}
+
+static void meson_nfc_select_chip(struct nand_chip *nand, int chip)
+{
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       struct meson_nfc *nfc = nand_get_controller_data(nand);
+       int ret, value;
+
+       if (chip < 0 || WARN_ON_ONCE(chip >= meson_chip->nsels))
+               return;
+
+       nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0;
+       nfc->param.rb_select = nfc->param.chip_select;
+       nfc->timing.twb = meson_chip->twb;
+       nfc->timing.tadl = meson_chip->tadl;
+       nfc->timing.tbers_max = meson_chip->tbers_max;
+
+       if (nfc->clk_rate != meson_chip->clk_rate) {
+               ret = clk_set_rate(nfc->device_clk, meson_chip->clk_rate);
+               if (ret) {
+                       dev_err(nfc->dev, "failed to set clock rate\n");
+                       return;
+               }
+               nfc->clk_rate = meson_chip->clk_rate;
+       }
+       if (nfc->bus_timing != meson_chip->bus_timing) {
+               value = (NFC_CLK_CYCLE - 1) | (meson_chip->bus_timing << 5);
+               writel(value, nfc->reg_base + NFC_REG_CFG);
+               writel((1 << 31), nfc->reg_base + NFC_REG_CMD);
+               nfc->bus_timing =  meson_chip->bus_timing;
+       }
+}
+
+static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time)
+{
+       writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff),
+              nfc->reg_base + NFC_REG_CMD);
+}
+
+static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed)
+{
+       writel(NFC_CMD_SEED | (0xc2 + (seed & 0x7fff)),
+              nfc->reg_base + NFC_REG_CMD);
+}
+
+static void meson_nfc_cmd_access(struct nand_chip *nand, int raw, bool dir,
+                                int scrambler)
+{
+       struct mtd_info *mtd = nand_to_mtd(nand);
+       struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       u32 bch = meson_chip->bch_mode, cmd;
+       int len = mtd->writesize, pagesize, pages;
+
+       pagesize = nand->ecc.size;
+
+       if (raw) {
+               len = mtd->writesize + mtd->oobsize;
+               cmd = (len & GENMASK(5, 0)) | scrambler | DMA_DIR(dir);
+               writel(cmd, nfc->reg_base + NFC_REG_CMD);
+               return;
+       }
+
+       pages = len / nand->ecc.size;
+
+       cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch,
+                      NFC_CMD_SHORTMODE_DISABLE, pagesize, pages);
+
+       writel(cmd, nfc->reg_base + NFC_REG_CMD);
+}
+
+static void meson_nfc_drain_cmd(struct meson_nfc *nfc)
+{
+       /*
+        * Insert two commands to make sure all valid commands are finished.
+        *
+        * The Nand flash controller is designed as two stages pipleline -
+        *  a) fetch and b) excute.
+        * There might be cases when the driver see command queue is empty,
+        * but the Nand flash controller still has two commands buffered,
+        * one is fetched into NFC request queue (ready to run), and another
+        * is actively executing. So pushing 2 "IDLE" commands guarantees that
+        * the pipeline is emptied.
+        */
+       meson_nfc_cmd_idle(nfc, 0);
+       meson_nfc_cmd_idle(nfc, 0);
+}
+
+static int meson_nfc_wait_cmd_finish(struct meson_nfc *nfc,
+                                    unsigned int timeout_ms)
+{
+       u32 cmd_size = 0;
+       int ret;
+
+       /* wait cmd fifo is empty */
+       ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size,
+                                        !NFC_CMD_GET_SIZE(cmd_size),
+                                        10, timeout_ms * 1000);
+       if (ret)
+               dev_err(nfc->dev, "wait for empty CMD FIFO time out\n");
+
+       return ret;
+}
+
+static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc)
+{
+       meson_nfc_drain_cmd(nfc);
+
+       return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT);
+}
+
+static u8 *meson_nfc_oob_ptr(struct nand_chip *nand, int i)
+{
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       int len;
+
+       len = nand->ecc.size * (i + 1) + (nand->ecc.bytes + 2) * i;
+
+       return meson_chip->data_buf + len;
+}
+
+static u8 *meson_nfc_data_ptr(struct nand_chip *nand, int i)
+{
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       int len, temp;
+
+       temp = nand->ecc.size + nand->ecc.bytes;
+       len = (temp + 2) * i;
+
+       return meson_chip->data_buf + len;
+}
+
+static void meson_nfc_get_data_oob(struct nand_chip *nand,
+                                  u8 *buf, u8 *oobbuf)
+{
+       int i, oob_len = 0;
+       u8 *dsrc, *osrc;
+
+       oob_len = nand->ecc.bytes + 2;
+       for (i = 0; i < nand->ecc.steps; i++) {
+               if (buf) {
+                       dsrc = meson_nfc_data_ptr(nand, i);
+                       memcpy(buf, dsrc, nand->ecc.size);
+                       buf += nand->ecc.size;
+               }
+               osrc = meson_nfc_oob_ptr(nand, i);
+               memcpy(oobbuf, osrc, oob_len);
+               oobbuf += oob_len;
+       }
+}
+
+static void meson_nfc_set_data_oob(struct nand_chip *nand,
+                                  const u8 *buf, u8 *oobbuf)
+{
+       int i, oob_len = 0;
+       u8 *dsrc, *osrc;
+
+       oob_len = nand->ecc.bytes + 2;
+       for (i = 0; i < nand->ecc.steps; i++) {
+               if (buf) {
+                       dsrc = meson_nfc_data_ptr(nand, i);
+                       memcpy(dsrc, buf, nand->ecc.size);
+                       buf += nand->ecc.size;
+               }
+               osrc = meson_nfc_oob_ptr(nand, i);
+               memcpy(osrc, oobbuf, oob_len);
+               oobbuf += oob_len;
+       }
+}
+
+static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms)
+{
+       u32 cmd, cfg;
+       int ret = 0;
+
+       meson_nfc_cmd_idle(nfc, nfc->timing.twb);
+       meson_nfc_drain_cmd(nfc);
+       meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
+
+       cfg = readl(nfc->reg_base + NFC_REG_CFG);
+       cfg |= NFC_RB_IRQ_EN;
+       writel(cfg, nfc->reg_base + NFC_REG_CFG);
+
+       init_completion(&nfc->completion);
+
+       /* use the max erase time as the maximum clock for waiting R/B */
+       cmd = NFC_CMD_RB | NFC_CMD_RB_INT
+               | nfc->param.chip_select | nfc->timing.tbers_max;
+       writel(cmd, nfc->reg_base + NFC_REG_CMD);
+
+       ret = wait_for_completion_timeout(&nfc->completion,
+                                         msecs_to_jiffies(timeout_ms));
+       if (ret == 0)
+               ret = -1;
+
+       return ret;
+}
+
+static void meson_nfc_set_user_byte(struct nand_chip *nand, u8 *oob_buf)
+{
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       __le64 *info;
+       int i, count;
+
+       for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) {
+               info = &meson_chip->info_buf[i];
+               *info |= oob_buf[count];
+               *info |= oob_buf[count + 1] << 8;
+       }
+}
+
+static void meson_nfc_get_user_byte(struct nand_chip *nand, u8 *oob_buf)
+{
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       __le64 *info;
+       int i, count;
+
+       for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) {
+               info = &meson_chip->info_buf[i];
+               oob_buf[count] = *info;
+               oob_buf[count + 1] = *info >> 8;
+       }
+}
+
+static int meson_nfc_ecc_correct(struct nand_chip *nand, u32 *bitflips,
+                                u64 *correct_bitmap)
+{
+       struct mtd_info *mtd = nand_to_mtd(nand);
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       __le64 *info;
+       int ret = 0, i;
+
+       for (i = 0; i < nand->ecc.steps; i++) {
+               info = &meson_chip->info_buf[i];
+               if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE) {
+                       mtd->ecc_stats.corrected += ECC_ERR_CNT(*info);
+                       *bitflips = max_t(u32, *bitflips, ECC_ERR_CNT(*info));
+                       *correct_bitmap |= 1 >> i;
+                       continue;
+               }
+               if ((nand->options & NAND_NEED_SCRAMBLING) &&
+                   ECC_ZERO_CNT(*info) < nand->ecc.strength) {
+                       mtd->ecc_stats.corrected += ECC_ZERO_CNT(*info);
+                       *bitflips = max_t(u32, *bitflips,
+                                         ECC_ZERO_CNT(*info));
+                       ret = ECC_CHECK_RETURN_FF;
+               } else {
+                       ret = -EBADMSG;
+               }
+       }
+       return ret;
+}
+
+static int meson_nfc_dma_buffer_setup(struct nand_chip *nand, u8 *databuf,
+                                     int datalen, u8 *infobuf, int infolen,
+                                     enum dma_data_direction dir)
+{
+       struct meson_nfc *nfc = nand_get_controller_data(nand);
+       u32 cmd;
+       int ret = 0;
+
+       nfc->daddr = dma_map_single(nfc->dev, (void *)databuf, datalen, dir);
+       ret = dma_mapping_error(nfc->dev, nfc->daddr);
+       if (ret) {
+               dev_err(nfc->dev, "DMA mapping error\n");
+               return ret;
+       }
+       cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr);
+       writel(cmd, nfc->reg_base + NFC_REG_CMD);
+
+       cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr);
+       writel(cmd, nfc->reg_base + NFC_REG_CMD);
+
+       if (infobuf) {
+               nfc->iaddr = dma_map_single(nfc->dev, infobuf, infolen, dir);
+               ret = dma_mapping_error(nfc->dev, nfc->iaddr);
+               if (ret) {
+                       dev_err(nfc->dev, "DMA mapping error\n");
+                       dma_unmap_single(nfc->dev,
+                                        nfc->daddr, datalen, dir);
+                       return ret;
+               }
+               cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr);
+               writel(cmd, nfc->reg_base + NFC_REG_CMD);
+
+               cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr);
+               writel(cmd, nfc->reg_base + NFC_REG_CMD);
+       }
+
+       return ret;
+}
+
+static void meson_nfc_dma_buffer_release(struct nand_chip *nand,
+                                        int infolen, int datalen,
+                                        enum dma_data_direction dir)
+{
+       struct meson_nfc *nfc = nand_get_controller_data(nand);
+
+       dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir);
+       if (infolen)
+               dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir);
+}
+
+static int meson_nfc_read_buf(struct nand_chip *nand, u8 *buf, int len)
+{
+       struct meson_nfc *nfc = nand_get_controller_data(nand);
+       int ret = 0;
+       u32 cmd;
+       u8 *info;
+
+       info = kzalloc(PER_INFO_BYTE, GFP_KERNEL);
+       ret = meson_nfc_dma_buffer_setup(nand, buf, len, info,
+                                        PER_INFO_BYTE, DMA_FROM_DEVICE);
+       if (ret)
+               return ret;
+
+       cmd = NFC_CMD_N2M | (len & GENMASK(5, 0));
+       writel(cmd, nfc->reg_base + NFC_REG_CMD);
+
+       meson_nfc_drain_cmd(nfc);
+       meson_nfc_wait_cmd_finish(nfc, 1000);
+       meson_nfc_dma_buffer_release(nand, len, PER_INFO_BYTE, DMA_FROM_DEVICE);
+       kfree(info);
+
+       return ret;
+}
+
+static int meson_nfc_write_buf(struct nand_chip *nand, u8 *buf, int len)
+{
+       struct meson_nfc *nfc = nand_get_controller_data(nand);
+       int ret = 0;
+       u32 cmd;
+
+       ret = meson_nfc_dma_buffer_setup(nand, buf, len, NULL,
+                                        0, DMA_TO_DEVICE);
+       if (ret)
+               return ret;
+
+       cmd = NFC_CMD_M2N | (len & GENMASK(5, 0));
+       writel(cmd, nfc->reg_base + NFC_REG_CMD);
+
+       meson_nfc_drain_cmd(nfc);
+       meson_nfc_wait_cmd_finish(nfc, 1000);
+       meson_nfc_dma_buffer_release(nand, len, 0, DMA_TO_DEVICE);
+
+       return ret;
+}
+
+static int meson_nfc_rw_cmd_prepare_and_execute(struct nand_chip *nand,
+                                               int page, bool in)
+{
+       struct mtd_info *mtd = nand_to_mtd(nand);
+       struct meson_nfc *nfc = nand_get_controller_data(nand);
+       const struct nand_sdr_timings *sdr =
+               nand_get_sdr_timings(&nand->data_interface);
+       u32 *addrs = nfc->cmdfifo.rw.addrs;
+       u32 cs = nfc->param.chip_select;
+       u32 cmd0, cmd_num, row_start;
+       int ret = 0, i;
+
+       cmd_num = sizeof(struct nand_rw_cmd) / sizeof(int);
+
+       cmd0 = in ? NAND_CMD_READ0 : NAND_CMD_SEQIN;
+       nfc->cmdfifo.rw.cmd0 = cs | NFC_CMD_CLE | cmd0;
+
+       addrs[0] = cs | NFC_CMD_ALE | 0;
+       if (mtd->writesize <= 512) {
+               cmd_num--;
+               row_start = 1;
+       } else {
+               addrs[1] = cs | NFC_CMD_ALE | 0;
+               row_start = 2;
+       }
+
+       addrs[row_start] = cs | NFC_CMD_ALE | ROW_ADDER(page, 0);
+       addrs[row_start + 1] = cs | NFC_CMD_ALE | ROW_ADDER(page, 1);
+
+       if (nand->options & NAND_ROW_ADDR_3)
+               addrs[row_start + 2] =
+                       cs | NFC_CMD_ALE | ROW_ADDER(page, 2);
+       else
+               cmd_num--;
+
+       /* subtract cmd1 */
+       cmd_num--;
+
+       for (i = 0; i < cmd_num; i++)
+               writel_relaxed(nfc->cmdfifo.cmd[i],
+                              nfc->reg_base + NFC_REG_CMD);
+
+       if (in) {
+               nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART;
+               writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD);
+               meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tR_max));
+       } else {
+               meson_nfc_cmd_idle(nfc, nfc->timing.tadl);
+       }
+
+       return ret;
+}
+
+static int meson_nfc_write_page_sub(struct nand_chip *nand,
+                                   int page, int raw)
+{
+       struct mtd_info *mtd = nand_to_mtd(nand);
+       const struct nand_sdr_timings *sdr =
+               nand_get_sdr_timings(&nand->data_interface);
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       struct meson_nfc *nfc = nand_get_controller_data(nand);
+       int data_len, info_len;
+       u32 cmd;
+       int ret;
+
+       meson_nfc_select_chip(nand, nand->cur_cs);
+
+       data_len =  mtd->writesize + mtd->oobsize;
+       info_len = nand->ecc.steps * PER_INFO_BYTE;
+
+       ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRWRITE);
+       if (ret)
+               return ret;
+
+       ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
+                                        data_len, (u8 *)meson_chip->info_buf,
+                                        info_len, DMA_TO_DEVICE);
+       if (ret)
+               return ret;
+
+       if (nand->options & NAND_NEED_SCRAMBLING) {
+               meson_nfc_cmd_seed(nfc, page);
+               meson_nfc_cmd_access(nand, raw, DIRWRITE,
+                                    NFC_CMD_SCRAMBLER_ENABLE);
+       } else {
+               meson_nfc_cmd_access(nand, raw, DIRWRITE,
+                                    NFC_CMD_SCRAMBLER_DISABLE);
+       }
+
+       cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
+       writel(cmd, nfc->reg_base + NFC_REG_CMD);
+       meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tPROG_max));
+
+       meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_TO_DEVICE);
+
+       return ret;
+}
+
+static int meson_nfc_write_page_raw(struct nand_chip *nand, const u8 *buf,
+                                   int oob_required, int page)
+{
+       u8 *oob_buf = nand->oob_poi;
+
+       meson_nfc_set_data_oob(nand, buf, oob_buf);
+
+       return meson_nfc_write_page_sub(nand, page, 1);
+}
+
+static int meson_nfc_write_page_hwecc(struct nand_chip *nand,
+                                     const u8 *buf, int oob_required, int page)
+{
+       struct mtd_info *mtd = nand_to_mtd(nand);
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       u8 *oob_buf = nand->oob_poi;
+
+       memcpy(meson_chip->data_buf, buf, mtd->writesize);
+       memset(meson_chip->info_buf, 0, nand->ecc.steps * PER_INFO_BYTE);
+       meson_nfc_set_user_byte(nand, oob_buf);
+
+       return meson_nfc_write_page_sub(nand, page, 0);
+}
+
+static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc,
+                                           struct nand_chip *nand, int raw)
+{
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       __le64 *info;
+       u32 neccpages;
+       int ret;
+
+       neccpages = raw ? 1 : nand->ecc.steps;
+       info = &meson_chip->info_buf[neccpages - 1];
+       do {
+               usleep_range(10, 15);
+               /* info is updated by nfc dma engine*/
+               smp_rmb();
+               ret = *info & ECC_COMPLETE;
+       } while (!ret);
+}
+
+static int meson_nfc_read_page_sub(struct nand_chip *nand,
+                                  int page, int raw)
+{
+       struct mtd_info *mtd = nand_to_mtd(nand);
+       struct meson_nfc *nfc = nand_get_controller_data(nand);
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       int data_len, info_len;
+       int ret;
+
+       meson_nfc_select_chip(nand, nand->cur_cs);
+
+       data_len =  mtd->writesize + mtd->oobsize;
+       info_len = nand->ecc.steps * PER_INFO_BYTE;
+
+       ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRREAD);
+       if (ret)
+               return ret;
+
+       ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
+                                        data_len, (u8 *)meson_chip->info_buf,
+                                        info_len, DMA_FROM_DEVICE);
+       if (ret)
+               return ret;
+
+       if (nand->options & NAND_NEED_SCRAMBLING) {
+               meson_nfc_cmd_seed(nfc, page);
+               meson_nfc_cmd_access(nand, raw, DIRREAD,
+                                    NFC_CMD_SCRAMBLER_ENABLE);
+       } else {
+               meson_nfc_cmd_access(nand, raw, DIRREAD,
+                                    NFC_CMD_SCRAMBLER_DISABLE);
+       }
+
+       ret = meson_nfc_wait_dma_finish(nfc);
+       meson_nfc_check_ecc_pages_valid(nfc, nand, raw);
+
+       meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_FROM_DEVICE);
+
+       return ret;
+}
+
+static int meson_nfc_read_page_raw(struct nand_chip *nand, u8 *buf,
+                                  int oob_required, int page)
+{
+       u8 *oob_buf = nand->oob_poi;
+       int ret;
+
+       ret = meson_nfc_read_page_sub(nand, page, 1);
+       if (ret)
+               return ret;
+
+       meson_nfc_get_data_oob(nand, buf, oob_buf);
+
+       return 0;
+}
+
+static int meson_nfc_read_page_hwecc(struct nand_chip *nand, u8 *buf,
+                                    int oob_required, int page)
+{
+       struct mtd_info *mtd = nand_to_mtd(nand);
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       struct nand_ecc_ctrl *ecc = &nand->ecc;
+       u64 correct_bitmap = 0;
+       u32 bitflips = 0;
+       u8 *oob_buf = nand->oob_poi;
+       int ret, i;
+
+       ret = meson_nfc_read_page_sub(nand, page, 0);
+       if (ret)
+               return ret;
+
+       meson_nfc_get_user_byte(nand, oob_buf);
+       ret = meson_nfc_ecc_correct(nand, &bitflips, &correct_bitmap);
+       if (ret == ECC_CHECK_RETURN_FF) {
+               if (buf)
+                       memset(buf, 0xff, mtd->writesize);
+               memset(oob_buf, 0xff, mtd->oobsize);
+       } else if (ret < 0) {
+               if ((nand->options & NAND_NEED_SCRAMBLING) || !buf) {
+                       mtd->ecc_stats.failed++;
+                       return bitflips;
+               }
+               ret  = meson_nfc_read_page_raw(nand, buf, 0, page);
+               if (ret)
+                       return ret;
+
+               for (i = 0; i < nand->ecc.steps ; i++) {
+                       u8 *data = buf + i * ecc->size;
+                       u8 *oob = nand->oob_poi + i * (ecc->bytes + 2);
+
+                       if (correct_bitmap & (1 << i))
+                               continue;
+                       ret = nand_check_erased_ecc_chunk(data, ecc->size,
+                                                         oob, ecc->bytes + 2,
+                                                         NULL, 0,
+                                                         ecc->strength);
+                       if (ret < 0) {
+                               mtd->ecc_stats.failed++;
+                       } else {
+                               mtd->ecc_stats.corrected += ret;
+                               bitflips =  max_t(u32, bitflips, ret);
+                       }
+               }
+       } else if (buf && buf != meson_chip->data_buf) {
+               memcpy(buf, meson_chip->data_buf, mtd->writesize);
+       }
+
+       return bitflips;
+}
+
+static int meson_nfc_read_oob_raw(struct nand_chip *nand, int page)
+{
+       return meson_nfc_read_page_raw(nand, NULL, 1, page);
+}
+
+static int meson_nfc_read_oob(struct nand_chip *nand, int page)
+{
+       return meson_nfc_read_page_hwecc(nand, NULL, 1, page);
+}
+
+static bool meson_nfc_is_buffer_dma_safe(const void *buffer)
+{
+       if (virt_addr_valid(buffer) && (!object_is_on_stack(buffer)))
+               return true;
+       return false;
+}
+
+static void *
+meson_nand_op_get_dma_safe_input_buf(const struct nand_op_instr *instr)
+{
+       if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR))
+               return NULL;
+
+       if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.in))
+               return instr->ctx.data.buf.in;
+
+       return kzalloc(instr->ctx.data.len, GFP_KERNEL);
+}
+
+static void
+meson_nand_op_put_dma_safe_input_buf(const struct nand_op_instr *instr,
+                                    void *buf)
+{
+       if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR) ||
+           WARN_ON(!buf))
+               return;
+
+       if (buf == instr->ctx.data.buf.in)
+               return;
+
+       memcpy(instr->ctx.data.buf.in, buf, instr->ctx.data.len);
+       kfree(buf);
+}
+
+static void *
+meson_nand_op_get_dma_safe_output_buf(const struct nand_op_instr *instr)
+{
+       if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR))
+               return NULL;
+
+       if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.out))
+               return (void *)instr->ctx.data.buf.out;
+
+       return kmemdup(instr->ctx.data.buf.out,
+                      instr->ctx.data.len, GFP_KERNEL);
+}
+
+static void
+meson_nand_op_put_dma_safe_output_buf(const struct nand_op_instr *instr,
+                                     const void *buf)
+{
+       if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR) ||
+           WARN_ON(!buf))
+               return;
+
+       if (buf != instr->ctx.data.buf.out)
+               kfree(buf);
+}
+
+static int meson_nfc_exec_op(struct nand_chip *nand,
+                            const struct nand_operation *op, bool check_only)
+{
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       struct meson_nfc *nfc = nand_get_controller_data(nand);
+       const struct nand_op_instr *instr = NULL;
+       void *buf;
+       u32 op_id, delay_idle, cmd;
+       int i;
+
+       meson_nfc_select_chip(nand, op->cs);
+       for (op_id = 0; op_id < op->ninstrs; op_id++) {
+               instr = &op->instrs[op_id];
+               delay_idle = DIV_ROUND_UP(PSEC_TO_NSEC(instr->delay_ns),
+                                         meson_chip->level1_divider *
+                                         NFC_CLK_CYCLE);
+               switch (instr->type) {
+               case NAND_OP_CMD_INSTR:
+                       cmd = nfc->param.chip_select | NFC_CMD_CLE;
+                       cmd |= instr->ctx.cmd.opcode & 0xff;
+                       writel(cmd, nfc->reg_base + NFC_REG_CMD);
+                       meson_nfc_cmd_idle(nfc, delay_idle);
+                       break;
+
+               case NAND_OP_ADDR_INSTR:
+                       for (i = 0; i < instr->ctx.addr.naddrs; i++) {
+                               cmd = nfc->param.chip_select | NFC_CMD_ALE;
+                               cmd |= instr->ctx.addr.addrs[i] & 0xff;
+                               writel(cmd, nfc->reg_base + NFC_REG_CMD);
+                       }
+                       meson_nfc_cmd_idle(nfc, delay_idle);
+                       break;
+
+               case NAND_OP_DATA_IN_INSTR:
+                       buf = meson_nand_op_get_dma_safe_input_buf(instr);
+                       if (!buf)
+                               return -ENOMEM;
+                       meson_nfc_read_buf(nand, buf, instr->ctx.data.len);
+                       meson_nand_op_put_dma_safe_input_buf(instr, buf);
+                       break;
+
+               case NAND_OP_DATA_OUT_INSTR:
+                       buf = meson_nand_op_get_dma_safe_output_buf(instr);
+                       if (!buf)
+                               return -ENOMEM;
+                       meson_nfc_write_buf(nand, buf, instr->ctx.data.len);
+                       meson_nand_op_put_dma_safe_output_buf(instr, buf);
+                       break;
+
+               case NAND_OP_WAITRDY_INSTR:
+                       meson_nfc_queue_rb(nfc, instr->ctx.waitrdy.timeout_ms);
+                       if (instr->delay_ns)
+                               meson_nfc_cmd_idle(nfc, delay_idle);
+                       break;
+               }
+       }
+       meson_nfc_wait_cmd_finish(nfc, 1000);
+       return 0;
+}
+
+static int meson_ooblayout_ecc(struct mtd_info *mtd, int section,
+                              struct mtd_oob_region *oobregion)
+{
+       struct nand_chip *nand = mtd_to_nand(mtd);
+
+       if (section >= nand->ecc.steps)
+               return -ERANGE;
+
+       oobregion->offset =  2 + (section * (2 + nand->ecc.bytes));
+       oobregion->length = nand->ecc.bytes;
+
+       return 0;
+}
+
+static int meson_ooblayout_free(struct mtd_info *mtd, int section,
+                               struct mtd_oob_region *oobregion)
+{
+       struct nand_chip *nand = mtd_to_nand(mtd);
+
+       if (section >= nand->ecc.steps)
+               return -ERANGE;
+
+       oobregion->offset = section * (2 + nand->ecc.bytes);
+       oobregion->length = 2;
+
+       return 0;
+}
+
+static const struct mtd_ooblayout_ops meson_ooblayout_ops = {
+       .ecc = meson_ooblayout_ecc,
+       .free = meson_ooblayout_free,
+};
+
+static int meson_nfc_clk_init(struct meson_nfc *nfc)
+{
+       int ret;
+
+       /* request core clock */
+       nfc->core_clk = devm_clk_get(nfc->dev, "core");
+       if (IS_ERR(nfc->core_clk)) {
+               dev_err(nfc->dev, "failed to get core clock\n");
+               return PTR_ERR(nfc->core_clk);
+       }
+
+       nfc->device_clk = devm_clk_get(nfc->dev, "device");
+       if (IS_ERR(nfc->device_clk)) {
+               dev_err(nfc->dev, "failed to get device clock\n");
+               return PTR_ERR(nfc->device_clk);
+       }
+
+       nfc->phase_tx = devm_clk_get(nfc->dev, "tx");
+       if (IS_ERR(nfc->phase_tx)) {
+               dev_err(nfc->dev, "failed to get TX clk\n");
+               return PTR_ERR(nfc->phase_tx);
+       }
+
+       nfc->phase_rx = devm_clk_get(nfc->dev, "rx");
+       if (IS_ERR(nfc->phase_rx)) {
+               dev_err(nfc->dev, "failed to get RX clk\n");
+               return PTR_ERR(nfc->phase_rx);
+       }
+
+       /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
+       regmap_update_bits(nfc->reg_clk,
+                          0, CLK_SELECT_NAND, CLK_SELECT_NAND);
+
+       ret = clk_prepare_enable(nfc->core_clk);
+       if (ret) {
+               dev_err(nfc->dev, "failed to enable core clock\n");
+               return ret;
+       }
+
+       ret = clk_prepare_enable(nfc->device_clk);
+       if (ret) {
+               dev_err(nfc->dev, "failed to enable device clock\n");
+               goto err_device_clk;
+       }
+
+       ret = clk_prepare_enable(nfc->phase_tx);
+       if (ret) {
+               dev_err(nfc->dev, "failed to enable TX clock\n");
+               goto err_phase_tx;
+       }
+
+       ret = clk_prepare_enable(nfc->phase_rx);
+       if (ret) {
+               dev_err(nfc->dev, "failed to enable RX clock\n");
+               goto err_phase_rx;
+       }
+
+       ret = clk_set_rate(nfc->device_clk, 24000000);
+       if (ret)
+               goto err_phase_rx;
+
+       return 0;
+err_phase_rx:
+       clk_disable_unprepare(nfc->phase_tx);
+err_phase_tx:
+       clk_disable_unprepare(nfc->device_clk);
+err_device_clk:
+       clk_disable_unprepare(nfc->core_clk);
+       return ret;
+}
+
+static void meson_nfc_disable_clk(struct meson_nfc *nfc)
+{
+       clk_disable_unprepare(nfc->phase_rx);
+       clk_disable_unprepare(nfc->phase_tx);
+       clk_disable_unprepare(nfc->device_clk);
+       clk_disable_unprepare(nfc->core_clk);
+}
+
+static void meson_nfc_free_buffer(struct nand_chip *nand)
+{
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+
+       kfree(meson_chip->info_buf);
+       kfree(meson_chip->data_buf);
+}
+
+static int meson_chip_buffer_init(struct nand_chip *nand)
+{
+       struct mtd_info *mtd = nand_to_mtd(nand);
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       u32 page_bytes, info_bytes, nsectors;
+
+       nsectors = mtd->writesize / nand->ecc.size;
+
+       page_bytes =  mtd->writesize + mtd->oobsize;
+       info_bytes = nsectors * PER_INFO_BYTE;
+
+       meson_chip->data_buf = kmalloc(page_bytes, GFP_KERNEL);
+       if (!meson_chip->data_buf)
+               return -ENOMEM;
+
+       meson_chip->info_buf = kmalloc(info_bytes, GFP_KERNEL);
+       if (!meson_chip->info_buf) {
+               kfree(meson_chip->data_buf);
+               return -ENOMEM;
+       }
+
+       return 0;
+}
+
+static
+int meson_nfc_setup_data_interface(struct nand_chip *nand, int csline,
+                                  const struct nand_data_interface *conf)
+{
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       const struct nand_sdr_timings *timings;
+       u32 div, bt_min, bt_max, tbers_clocks;
+
+       timings = nand_get_sdr_timings(conf);
+       if (IS_ERR(timings))
+               return -ENOTSUPP;
+
+       if (csline == NAND_DATA_IFACE_CHECK_ONLY)
+               return 0;
+
+       div = DIV_ROUND_UP((timings->tRC_min / 1000), NFC_CLK_CYCLE);
+       bt_min = (timings->tREA_max + NFC_DEFAULT_DELAY) / div;
+       bt_max = (NFC_DEFAULT_DELAY + timings->tRHOH_min +
+                 timings->tRC_min / 2) / div;
+
+       meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max),
+                                      div * NFC_CLK_CYCLE);
+       meson_chip->tadl = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tADL_min),
+                                       div * NFC_CLK_CYCLE);
+       tbers_clocks = DIV_ROUND_UP_ULL(PSEC_TO_NSEC(timings->tBERS_max),
+                                       div * NFC_CLK_CYCLE);
+       meson_chip->tbers_max = ilog2(tbers_clocks);
+       if (!is_power_of_2(tbers_clocks))
+               meson_chip->tbers_max++;
+
+       bt_min = DIV_ROUND_UP(bt_min, 1000);
+       bt_max = DIV_ROUND_UP(bt_max, 1000);
+
+       if (bt_max < bt_min)
+               return -EINVAL;
+
+       meson_chip->level1_divider = div;
+       meson_chip->clk_rate = 1000000000 / meson_chip->level1_divider;
+       meson_chip->bus_timing = (bt_min + bt_max) / 2 + 1;
+
+       return 0;
+}
+
+static int meson_nand_bch_mode(struct nand_chip *nand)
+{
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       int i;
+
+       if (nand->ecc.strength > 60 || nand->ecc.strength < 8)
+               return -EINVAL;
+
+       for (i = 0; i < ARRAY_SIZE(meson_ecc); i++) {
+               if (meson_ecc[i].strength == nand->ecc.strength) {
+                       meson_chip->bch_mode = meson_ecc[i].bch;
+                       return 0;
+               }
+       }
+
+       return -EINVAL;
+}
+
+static void meson_nand_detach_chip(struct nand_chip *nand)
+{
+       meson_nfc_free_buffer(nand);
+}
+
+static int meson_nand_attach_chip(struct nand_chip *nand)
+{
+       struct meson_nfc *nfc = nand_get_controller_data(nand);
+       struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+       struct mtd_info *mtd = nand_to_mtd(nand);
+       int nsectors = mtd->writesize / 1024;
+       int ret;
+
+       if (!mtd->name) {
+               mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
+                                          "%s:nand%d",
+                                          dev_name(nfc->dev),
+                                          meson_chip->sels[0]);
+               if (!mtd->name)
+                       return -ENOMEM;
+       }
+
+       if (nand->bbt_options & NAND_BBT_USE_FLASH)
+               nand->bbt_options |= NAND_BBT_NO_OOB;
+
+       nand->options |= NAND_NO_SUBPAGE_WRITE;
+
+       ret = nand_ecc_choose_conf(nand, nfc->data->ecc_caps,
+                                  mtd->oobsize - 2 * nsectors);
+       if (ret) {
+               dev_err(nfc->dev, "failed to ECC init\n");
+               return -EINVAL;
+       }
+
+       ret = meson_nand_bch_mode(nand);
+       if (ret)
+               return -EINVAL;
+
+       nand->ecc.mode = NAND_ECC_HW;
+       nand->ecc.write_page_raw = meson_nfc_write_page_raw;
+       nand->ecc.write_page = meson_nfc_write_page_hwecc;
+       nand->ecc.write_oob_raw = nand_write_oob_std;
+       nand->ecc.write_oob = nand_write_oob_std;
+
+       nand->ecc.read_page_raw = meson_nfc_read_page_raw;
+       nand->ecc.read_page = meson_nfc_read_page_hwecc;
+       nand->ecc.read_oob_raw = meson_nfc_read_oob_raw;
+       nand->ecc.read_oob = meson_nfc_read_oob;
+
+       if (nand->options & NAND_BUSWIDTH_16) {
+               dev_err(nfc->dev, "16bits bus width not supported");
+               return -EINVAL;
+       }
+       ret = meson_chip_buffer_init(nand);
+       if (ret)
+               return -ENOMEM;
+
+       return ret;
+}
+
+static const struct nand_controller_ops meson_nand_controller_ops = {
+       .attach_chip = meson_nand_attach_chip,
+       .detach_chip = meson_nand_detach_chip,
+       .setup_data_interface = meson_nfc_setup_data_interface,
+       .exec_op = meson_nfc_exec_op,
+};
+
+static int
+meson_nfc_nand_chip_init(struct device *dev,
+                        struct meson_nfc *nfc, struct device_node *np)
+{
+       struct meson_nfc_nand_chip *meson_chip;
+       struct nand_chip *nand;
+       struct mtd_info *mtd;
+       int ret, i;
+       u32 tmp, nsels;
+
+       if (!of_get_property(np, "reg", &nsels))
+               return -EINVAL;
+
+       nsels /= sizeof(u32);
+       if (!nsels || nsels > MAX_CE_NUM) {
+               dev_err(dev, "invalid register property size\n");
+               return -EINVAL;
+       }
+
+       meson_chip = devm_kzalloc(dev,
+                                 sizeof(*meson_chip) + (nsels * sizeof(u8)),
+                                 GFP_KERNEL);
+       if (!meson_chip)
+               return -ENOMEM;
+
+       meson_chip->nsels = nsels;
+
+       for (i = 0; i < nsels; i++) {
+               ret = of_property_read_u32_index(np, "reg", i, &tmp);
+               if (ret) {
+                       dev_err(dev, "could not retrieve register property: %d\n",
+                               ret);
+                       return ret;
+               }
+
+               if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
+                       dev_err(dev, "CS %d already assigned\n", tmp);
+                       return -EINVAL;
+               }
+       }
+
+       nand = &meson_chip->nand;
+       nand->controller = &nfc->controller;
+       nand->controller->ops = &meson_nand_controller_ops;
+       nand_set_flash_node(nand, np);
+       nand_set_controller_data(nand, nfc);
+
+       nand->options |= NAND_USE_BOUNCE_BUFFER;
+       mtd = nand_to_mtd(nand);
+       mtd->owner = THIS_MODULE;
+       mtd->dev.parent = dev;
+
+       ret = nand_scan(nand, nsels);
+       if (ret)
+               return ret;
+
+       ret = mtd_device_register(mtd, NULL, 0);
+       if (ret) {
+               dev_err(dev, "failed to register MTD device: %d\n", ret);
+               nand_cleanup(nand);
+               return ret;
+       }
+
+       list_add_tail(&meson_chip->node, &nfc->chips);
+
+       return 0;
+}
+
+static int meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc)
+{
+       struct meson_nfc_nand_chip *meson_chip;
+       struct mtd_info *mtd;
+       int ret;
+
+       while (!list_empty(&nfc->chips)) {
+               meson_chip = list_first_entry(&nfc->chips,
+                                             struct meson_nfc_nand_chip, node);
+               mtd = nand_to_mtd(&meson_chip->nand);
+               ret = mtd_device_unregister(mtd);
+               if (ret)
+                       return ret;
+
+               meson_nfc_free_buffer(&meson_chip->nand);
+               nand_cleanup(&meson_chip->nand);
+               list_del(&meson_chip->node);
+       }
+
+       return 0;
+}
+
+static int meson_nfc_nand_chips_init(struct device *dev,
+                                    struct meson_nfc *nfc)
+{
+       struct device_node *np = dev->of_node;
+       struct device_node *nand_np;
+       int ret;
+
+       for_each_child_of_node(np, nand_np) {
+               ret = meson_nfc_nand_chip_init(dev, nfc, nand_np);
+               if (ret) {
+                       meson_nfc_nand_chip_cleanup(nfc);
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
+static irqreturn_t meson_nfc_irq(int irq, void *id)
+{
+       struct meson_nfc *nfc = id;
+       u32 cfg;
+
+       cfg = readl(nfc->reg_base + NFC_REG_CFG);
+       if (!(cfg & NFC_RB_IRQ_EN))
+               return IRQ_NONE;
+
+       cfg &= ~(NFC_RB_IRQ_EN);
+       writel(cfg, nfc->reg_base + NFC_REG_CFG);
+
+       complete(&nfc->completion);
+       return IRQ_HANDLED;
+}
+
+static const struct meson_nfc_data meson_gxl_data = {
+       .ecc_caps = &meson_gxl_ecc_caps,
+};
+
+static const struct meson_nfc_data meson_axg_data = {
+       .ecc_caps = &meson_axg_ecc_caps,
+};
+
+static const struct of_device_id meson_nfc_id_table[] = {
+       {
+               .compatible = "amlogic,meson-gxl-nfc",
+               .data = &meson_gxl_data,
+       }, {
+               .compatible = "amlogic,meson-axg-nfc",
+               .data = &meson_axg_data,
+       },
+       {}
+};
+MODULE_DEVICE_TABLE(of, meson_nfc_id_table);
+
+static int meson_nfc_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       struct meson_nfc *nfc;
+       struct resource *res;
+       int ret, irq;
+
+       nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
+       if (!nfc)
+               return -ENOMEM;
+
+       nfc->data = of_device_get_match_data(&pdev->dev);
+       if (!nfc->data)
+               return -ENODEV;
+
+       nand_controller_init(&nfc->controller);
+       INIT_LIST_HEAD(&nfc->chips);
+
+       nfc->dev = dev;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       nfc->reg_base = devm_ioremap_resource(dev, res);
+       if (IS_ERR(nfc->reg_base))
+               return PTR_ERR(nfc->reg_base);
+
+       nfc->reg_clk =
+               syscon_regmap_lookup_by_phandle(dev->of_node,
+                                               "amlogic,mmc-syscon");
+       if (IS_ERR(nfc->reg_clk)) {
+               dev_err(dev, "Failed to lookup clock base\n");
+               return PTR_ERR(nfc->reg_clk);
+       }
+
+       irq = platform_get_irq(pdev, 0);
+       if (irq < 0) {
+               dev_err(dev, "no NFC IRQ resource\n");
+               return -EINVAL;
+       }
+
+       ret = meson_nfc_clk_init(nfc);
+       if (ret) {
+               dev_err(dev, "failed to initialize NAND clock\n");
+               return ret;
+       }
+
+       writel(0, nfc->reg_base + NFC_REG_CFG);
+       ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc);
+       if (ret) {
+               dev_err(dev, "failed to request NFC IRQ\n");
+               ret = -EINVAL;
+               goto err_clk;
+       }
+
+       ret = dma_set_mask(dev, DMA_BIT_MASK(32));
+       if (ret) {
+               dev_err(dev, "failed to set DMA mask\n");
+               goto err_clk;
+       }
+
+       platform_set_drvdata(pdev, nfc);
+
+       ret = meson_nfc_nand_chips_init(dev, nfc);
+       if (ret) {
+               dev_err(dev, "failed to init NAND chips\n");
+               goto err_clk;
+       }
+
+       return 0;
+err_clk:
+       meson_nfc_disable_clk(nfc);
+       return ret;
+}
+
+static int meson_nfc_remove(struct platform_device *pdev)
+{
+       struct meson_nfc *nfc = platform_get_drvdata(pdev);
+       int ret;
+
+       ret = meson_nfc_nand_chip_cleanup(nfc);
+       if (ret)
+               return ret;
+
+       meson_nfc_disable_clk(nfc);
+
+       platform_set_drvdata(pdev, NULL);
+
+       return 0;
+}
+
+static struct platform_driver meson_nfc_driver = {
+       .probe  = meson_nfc_probe,
+       .remove = meson_nfc_remove,
+       .driver = {
+               .name  = "meson-nand",
+               .of_match_table = meson_nfc_id_table,
+       },
+};
+module_platform_driver(meson_nfc_driver);
+
+MODULE_LICENSE("Dual MIT/GPL");
+MODULE_AUTHOR("Liang Yang <liang.yang@amlogic.com>");
+MODULE_DESCRIPTION("Amlogic's Meson NAND Flash Controller driver");
index 6432bd70c3b3913a71442744ad122b727e12bc30..05b0c19d72d99ec5b149a345adcefb6f6faeb0cd 100644 (file)
@@ -267,11 +267,15 @@ static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
        struct mtk_ecc *ecc;
 
        pdev = of_find_device_by_node(np);
-       if (!pdev || !platform_get_drvdata(pdev))
+       if (!pdev)
                return ERR_PTR(-EPROBE_DEFER);
 
-       get_device(&pdev->dev);
        ecc = platform_get_drvdata(pdev);
+       if (!ecc) {
+               put_device(&pdev->dev);
+               return ERR_PTR(-EPROBE_DEFER);
+       }
+
        clk_prepare_enable(ecc->clk);
        mtk_ecc_hw_init(ecc);
 
index b6b4602f5132ebc7b9b3fe30daabd3094bd06ccf..2c0e091877738d2bb49ab4c483bcc848261821c7 100644 (file)
@@ -1451,8 +1451,7 @@ static int mtk_nfc_probe(struct platform_device *pdev)
        if (!nfc)
                return -ENOMEM;
 
-       spin_lock_init(&nfc->controller.lock);
-       init_waitqueue_head(&nfc->controller.wq);
+       nand_controller_init(&nfc->controller);
        INIT_LIST_HEAD(&nfc->chips);
        nfc->controller.ops = &mtk_nfc_controller_ops;
 
index 839494ac457c15c4697a357f2136f0cf0852acc6..ddd396e93e321055d425c2baba0cb634dae6c879 100644 (file)
@@ -278,11 +278,8 @@ EXPORT_SYMBOL_GPL(nand_deselect_target);
 static void nand_release_device(struct nand_chip *chip)
 {
        /* Release the controller and the chip */
-       spin_lock(&chip->controller->lock);
-       chip->controller->active = NULL;
-       chip->state = FL_READY;
-       wake_up(&chip->controller->wq);
-       spin_unlock(&chip->controller->lock);
+       mutex_unlock(&chip->controller->lock);
+       mutex_unlock(&chip->lock);
 }
 
 /**
@@ -330,58 +327,24 @@ static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs)
        return nand_block_bad(chip, ofs);
 }
 
-/**
- * panic_nand_get_device - [GENERIC] Get chip for selected access
- * @chip: the nand chip descriptor
- * @new_state: the state which is requested
- *
- * Used when in panic, no locks are taken.
- */
-static void panic_nand_get_device(struct nand_chip *chip, int new_state)
-{
-       /* Hardware controller shared among independent devices */
-       chip->controller->active = chip;
-       chip->state = new_state;
-}
-
 /**
  * nand_get_device - [GENERIC] Get chip for selected access
  * @chip: NAND chip structure
- * @new_state: the state which is requested
  *
- * Get the device and lock it for exclusive access
+ * Lock the device and its controller for exclusive access
+ *
+ * Return: -EBUSY if the chip has been suspended, 0 otherwise
  */
-static int
-nand_get_device(struct nand_chip *chip, int new_state)
+static int nand_get_device(struct nand_chip *chip)
 {
-       spinlock_t *lock = &chip->controller->lock;
-       wait_queue_head_t *wq = &chip->controller->wq;
-       DECLARE_WAITQUEUE(wait, current);
-retry:
-       spin_lock(lock);
-
-       /* Hardware controller shared among independent devices */
-       if (!chip->controller->active)
-               chip->controller->active = chip;
-
-       if (chip->controller->active == chip && chip->state == FL_READY) {
-               chip->state = new_state;
-               spin_unlock(lock);
-               return 0;
-       }
-       if (new_state == FL_PM_SUSPENDED) {
-               if (chip->controller->active->state == FL_PM_SUSPENDED) {
-                       chip->state = FL_PM_SUSPENDED;
-                       spin_unlock(lock);
-                       return 0;
-               }
+       mutex_lock(&chip->lock);
+       if (chip->suspended) {
+               mutex_unlock(&chip->lock);
+               return -EBUSY;
        }
-       set_current_state(TASK_UNINTERRUPTIBLE);
-       add_wait_queue(wq, &wait);
-       spin_unlock(lock);
-       schedule();
-       remove_wait_queue(wq, &wait);
-       goto retry;
+       mutex_lock(&chip->controller->lock);
+
+       return 0;
 }
 
 /**
@@ -458,7 +421,7 @@ static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
                             struct mtd_oob_ops *ops)
 {
        struct mtd_info *mtd = nand_to_mtd(chip);
-       int chipnr, page, status, len;
+       int chipnr, page, status, len, ret;
 
        pr_debug("%s: to = 0x%08x, len = %i\n",
                         __func__, (unsigned int)to, (int)ops->ooblen);
@@ -480,7 +443,9 @@ static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
         * if we don't do this. I have no clue why, but I seem to have 'fixed'
         * it in the doc2000 driver in August 1999.  dwmw2.
         */
-       nand_reset(chip, chipnr);
+       ret = nand_reset(chip, chipnr);
+       if (ret)
+               return ret;
 
        nand_select_target(chip, chipnr);
 
@@ -603,7 +568,10 @@ static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs)
                nand_erase_nand(chip, &einfo, 0);
 
                /* Write bad block marker to OOB */
-               nand_get_device(chip, FL_WRITING);
+               ret = nand_get_device(chip);
+               if (ret)
+                       return ret;
+
                ret = nand_markbad_bbm(chip, ofs);
                nand_release_device(chip);
        }
@@ -3581,7 +3549,9 @@ static int nand_read_oob(struct mtd_info *mtd, loff_t from,
            ops->mode != MTD_OPS_RAW)
                return -ENOTSUPP;
 
-       nand_get_device(chip, FL_READING);
+       ret = nand_get_device(chip);
+       if (ret)
+               return ret;
 
        if (!ops->datbuf)
                ret = nand_do_read_oob(chip, from, ops);
@@ -4100,9 +4070,6 @@ static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
        struct mtd_oob_ops ops;
        int ret;
 
-       /* Grab the device */
-       panic_nand_get_device(chip, FL_WRITING);
-
        nand_select_target(chip, chipnr);
 
        /* Wait for the device to get ready */
@@ -4133,7 +4100,9 @@ static int nand_write_oob(struct mtd_info *mtd, loff_t to,
 
        ops->retlen = 0;
 
-       nand_get_device(chip, FL_WRITING);
+       ret = nand_get_device(chip);
+       if (ret)
+               return ret;
 
        switch (ops->mode) {
        case MTD_OPS_PLACE_OOB:
@@ -4155,23 +4124,6 @@ out:
        return ret;
 }
 
-/**
- * single_erase - [GENERIC] NAND standard block erase command function
- * @chip: NAND chip object
- * @page: the page address of the block which will be erased
- *
- * Standard erase command for NAND chips. Returns NAND status.
- */
-static int single_erase(struct nand_chip *chip, int page)
-{
-       unsigned int eraseblock;
-
-       /* Send commands to erase a block */
-       eraseblock = page >> (chip->phys_erase_shift - chip->page_shift);
-
-       return nand_erase_op(chip, eraseblock);
-}
-
 /**
  * nand_erase - [MTD Interface] erase block(s)
  * @mtd: MTD device structure
@@ -4195,7 +4147,7 @@ static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
 int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
                    int allowbbt)
 {
-       int page, status, pages_per_block, ret, chipnr;
+       int page, pages_per_block, ret, chipnr;
        loff_t len;
 
        pr_debug("%s: start = 0x%012llx, len = %llu\n",
@@ -4206,7 +4158,9 @@ int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
                return -EINVAL;
 
        /* Grab the lock and see if the device is available */
-       nand_get_device(chip, FL_ERASING);
+       ret = nand_get_device(chip);
+       if (ret)
+               return ret;
 
        /* Shift to get first page */
        page = (int)(instr->addr >> chip->page_shift);
@@ -4247,17 +4201,11 @@ int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
                    (page + pages_per_block))
                        chip->pagebuf = -1;
 
-               if (chip->legacy.erase)
-                       status = chip->legacy.erase(chip,
-                                                   page & chip->pagemask);
-               else
-                       status = single_erase(chip, page & chip->pagemask);
-
-               /* See if block erase succeeded */
-               if (status) {
+               ret = nand_erase_op(chip, (page & chip->pagemask) >>
+                                   (chip->phys_erase_shift - chip->page_shift));
+               if (ret) {
                        pr_debug("%s: failed erase, page 0x%08x\n",
                                        __func__, page);
-                       ret = -EIO;
                        instr->fail_addr =
                                ((loff_t)page << chip->page_shift);
                        goto erase_exit;
@@ -4299,7 +4247,7 @@ static void nand_sync(struct mtd_info *mtd)
        pr_debug("%s: called\n", __func__);
 
        /* Grab the lock and see if the device is available */
-       nand_get_device(chip, FL_SYNCING);
+       WARN_ON(nand_get_device(chip));
        /* Release it and go back */
        nand_release_device(chip);
 }
@@ -4316,7 +4264,10 @@ static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
        int ret;
 
        /* Select the NAND device */
-       nand_get_device(chip, FL_READING);
+       ret = nand_get_device(chip);
+       if (ret)
+               return ret;
+
        nand_select_target(chip, chipnr);
 
        ret = nand_block_checkbad(chip, offs, 0);
@@ -4389,7 +4340,13 @@ static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len)
  */
 static int nand_suspend(struct mtd_info *mtd)
 {
-       return nand_get_device(mtd_to_nand(mtd), FL_PM_SUSPENDED);
+       struct nand_chip *chip = mtd_to_nand(mtd);
+
+       mutex_lock(&chip->lock);
+       chip->suspended = 1;
+       mutex_unlock(&chip->lock);
+
+       return 0;
 }
 
 /**
@@ -4400,11 +4357,13 @@ static void nand_resume(struct mtd_info *mtd)
 {
        struct nand_chip *chip = mtd_to_nand(mtd);
 
-       if (chip->state == FL_PM_SUSPENDED)
-               nand_release_device(chip);
+       mutex_lock(&chip->lock);
+       if (chip->suspended)
+               chip->suspended = 0;
        else
                pr_err("%s called for a chip which is not in suspended state\n",
                        __func__);
+       mutex_unlock(&chip->lock);
 }
 
 /**
@@ -4414,7 +4373,7 @@ static void nand_resume(struct mtd_info *mtd)
  */
 static void nand_shutdown(struct mtd_info *mtd)
 {
-       nand_get_device(mtd_to_nand(mtd), FL_PM_SUSPENDED);
+       nand_suspend(mtd);
 }
 
 /* Set default functions */
@@ -5019,6 +4978,8 @@ static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
        /* Assume all dies are deselected when we enter nand_scan_ident(). */
        chip->cur_cs = -1;
 
+       mutex_init(&chip->lock);
+
        /* Enforce the right timings for reset/detection */
        onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
 
@@ -5061,11 +5022,15 @@ static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
                u8 id[2];
 
                /* See comment in nand_get_flash_type for reset */
-               nand_reset(chip, i);
+               ret = nand_reset(chip, i);
+               if (ret)
+                       break;
 
                nand_select_target(chip, i);
                /* Send the command for reading device ID */
-               nand_readid_op(chip, 0, id, sizeof(id));
+               ret = nand_readid_op(chip, 0, id, sizeof(id));
+               if (ret)
+                       break;
                /* Read manufacturer and device IDs */
                if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
                        nand_deselect_target(chip);
@@ -5556,6 +5521,7 @@ static int nand_scan_tail(struct nand_chip *chip)
                }
                if (!ecc->read_page)
                        ecc->read_page = nand_read_page_hwecc_oob_first;
+               /* fall through */
 
        case NAND_ECC_HW:
                /* Use standard hwecc read page function? */
@@ -5575,6 +5541,7 @@ static int nand_scan_tail(struct nand_chip *chip)
                        ecc->read_subpage = nand_read_subpage;
                if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
                        ecc->write_subpage = nand_write_subpage_hwecc;
+               /* fall through */
 
        case NAND_ECC_HW_SYNDROME:
                if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
@@ -5612,6 +5579,7 @@ static int nand_scan_tail(struct nand_chip *chip)
                        ecc->size, mtd->writesize);
                ecc->mode = NAND_ECC_SOFT;
                ecc->algo = NAND_ECC_HAMMING;
+               /* fall through */
 
        case NAND_ECC_SOFT:
                ret = nand_set_ecc_soft_ops(chip);
@@ -5718,9 +5686,6 @@ static int nand_scan_tail(struct nand_chip *chip)
        }
        chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
 
-       /* Initialize state */
-       chip->state = FL_READY;
-
        /* Invalidate the pagebuffer reference */
        chip->pagebuf = -1;
 
index 43575943f13bde45a3ff5889af83e0506e82e758..f2526ec616a621512bf15440c23632ff448b2311 100644 (file)
@@ -331,6 +331,7 @@ static void nand_command(struct nand_chip *chip, unsigned int command,
                 */
                if (column == -1 && page_addr == -1)
                        return;
+               /* fall through */
 
        default:
                /*
@@ -483,7 +484,7 @@ static void nand_command_lp(struct nand_chip *chip, unsigned int command,
                chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
                                      NAND_NCE | NAND_CTRL_CHANGE);
 
-               /* This applies to read commands */
+               /* fall through - This applies to read commands */
        default:
                /*
                 * If we don't have access to the busy pin, we apply the given
index 68e8b9f7f372a71618837e6a39e88d373c59ed3b..8f280a2962c8b8b6cacad67a67df67a54e3ebe29 100644 (file)
@@ -994,12 +994,9 @@ static int omap_wait(struct nand_chip *this)
 {
        struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(this));
        unsigned long timeo = jiffies;
-       int status, state = this->state;
+       int status;
 
-       if (state == FL_ERASING)
-               timeo += msecs_to_jiffies(400);
-       else
-               timeo += msecs_to_jiffies(20);
+       timeo += msecs_to_jiffies(400);
 
        writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
        while (time_before(jiffies, timeo)) {
@@ -2173,11 +2170,8 @@ static const struct nand_controller_ops omap_nand_controller_ops = {
 };
 
 /* Shared among all NAND instances to synchronize access to the ECC Engine */
-static struct nand_controller omap_gpmc_controller = {
-       .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
-       .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
-       .ops = &omap_nand_controller_ops,
-};
+static struct nand_controller omap_gpmc_controller;
+static bool omap_gpmc_controller_initialized;
 
 static int omap_nand_probe(struct platform_device *pdev)
 {
@@ -2227,6 +2221,12 @@ static int omap_nand_probe(struct platform_device *pdev)
 
        info->phys_base = res->start;
 
+       if (!omap_gpmc_controller_initialized) {
+               omap_gpmc_controller.ops = &omap_nand_controller_ops;
+               nand_controller_init(&omap_gpmc_controller);
+               omap_gpmc_controller_initialized = true;
+       }
+
        nand_chip->controller = &omap_gpmc_controller;
 
        nand_chip->legacy.IO_ADDR_W = nand_chip->legacy.IO_ADDR_R;
index c01422d953dd80487f3a21839bccf6859d818951..86456216fb93f5bf9b90fc6b6f454630e947269b 100644 (file)
@@ -369,8 +369,7 @@ static int r852_wait(struct nand_chip *chip)
        unsigned long timeout;
        u8 status;
 
-       timeout = jiffies + (chip->state == FL_ERASING ?
-               msecs_to_jiffies(400) : msecs_to_jiffies(20));
+       timeout = jiffies + msecs_to_jiffies(400);
 
        while (time_before(jiffies, timeout))
                if (chip->legacy.dev_ready(chip))
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
new file mode 100644 (file)
index 0000000..999ca6a
--- /dev/null
@@ -0,0 +1,2073 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2018
+ * Author: Christophe Kerello <christophe.kerello@st.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+/* Bad block marker length */
+#define FMC2_BBM_LEN                   2
+
+/* ECC step size */
+#define FMC2_ECC_STEP_SIZE             512
+
+/* BCHDSRx registers length */
+#define FMC2_BCHDSRS_LEN               20
+
+/* HECCR length */
+#define FMC2_HECCR_LEN                 4
+
+/* Max requests done for a 8k nand page size */
+#define FMC2_MAX_SG                    16
+
+/* Max chip enable */
+#define FMC2_MAX_CE                    2
+
+/* Max ECC buffer length */
+#define FMC2_MAX_ECC_BUF_LEN           (FMC2_BCHDSRS_LEN * FMC2_MAX_SG)
+
+/* Timings */
+#define FMC2_THIZ                      1
+#define FMC2_TIO                       8000
+#define FMC2_TSYNC                     3000
+#define FMC2_PCR_TIMING_MASK           0xf
+#define FMC2_PMEM_PATT_TIMING_MASK     0xff
+
+/* FMC2 Controller Registers */
+#define FMC2_BCR1                      0x0
+#define FMC2_PCR                       0x80
+#define FMC2_SR                                0x84
+#define FMC2_PMEM                      0x88
+#define FMC2_PATT                      0x8c
+#define FMC2_HECCR                     0x94
+#define FMC2_CSQCR                     0x200
+#define FMC2_CSQCFGR1                  0x204
+#define FMC2_CSQCFGR2                  0x208
+#define FMC2_CSQCFGR3                  0x20c
+#define FMC2_CSQAR1                    0x210
+#define FMC2_CSQAR2                    0x214
+#define FMC2_CSQIER                    0x220
+#define FMC2_CSQISR                    0x224
+#define FMC2_CSQICR                    0x228
+#define FMC2_CSQEMSR                   0x230
+#define FMC2_BCHIER                    0x250
+#define FMC2_BCHISR                    0x254
+#define FMC2_BCHICR                    0x258
+#define FMC2_BCHPBR1                   0x260
+#define FMC2_BCHPBR2                   0x264
+#define FMC2_BCHPBR3                   0x268
+#define FMC2_BCHPBR4                   0x26c
+#define FMC2_BCHDSR0                   0x27c
+#define FMC2_BCHDSR1                   0x280
+#define FMC2_BCHDSR2                   0x284
+#define FMC2_BCHDSR3                   0x288
+#define FMC2_BCHDSR4                   0x28c
+
+/* Register: FMC2_BCR1 */
+#define FMC2_BCR1_FMC2EN               BIT(31)
+
+/* Register: FMC2_PCR */
+#define FMC2_PCR_PWAITEN               BIT(1)
+#define FMC2_PCR_PBKEN                 BIT(2)
+#define FMC2_PCR_PWID_MASK             GENMASK(5, 4)
+#define FMC2_PCR_PWID(x)               (((x) & 0x3) << 4)
+#define FMC2_PCR_PWID_BUSWIDTH_8       0
+#define FMC2_PCR_PWID_BUSWIDTH_16      1
+#define FMC2_PCR_ECCEN                 BIT(6)
+#define FMC2_PCR_ECCALG                        BIT(8)
+#define FMC2_PCR_TCLR_MASK             GENMASK(12, 9)
+#define FMC2_PCR_TCLR(x)               (((x) & 0xf) << 9)
+#define FMC2_PCR_TCLR_DEFAULT          0xf
+#define FMC2_PCR_TAR_MASK              GENMASK(16, 13)
+#define FMC2_PCR_TAR(x)                        (((x) & 0xf) << 13)
+#define FMC2_PCR_TAR_DEFAULT           0xf
+#define FMC2_PCR_ECCSS_MASK            GENMASK(19, 17)
+#define FMC2_PCR_ECCSS(x)              (((x) & 0x7) << 17)
+#define FMC2_PCR_ECCSS_512             1
+#define FMC2_PCR_ECCSS_2048            3
+#define FMC2_PCR_BCHECC                        BIT(24)
+#define FMC2_PCR_WEN                   BIT(25)
+
+/* Register: FMC2_SR */
+#define FMC2_SR_NWRF                   BIT(6)
+
+/* Register: FMC2_PMEM */
+#define FMC2_PMEM_MEMSET(x)            (((x) & 0xff) << 0)
+#define FMC2_PMEM_MEMWAIT(x)           (((x) & 0xff) << 8)
+#define FMC2_PMEM_MEMHOLD(x)           (((x) & 0xff) << 16)
+#define FMC2_PMEM_MEMHIZ(x)            (((x) & 0xff) << 24)
+#define FMC2_PMEM_DEFAULT              0x0a0a0a0a
+
+/* Register: FMC2_PATT */
+#define FMC2_PATT_ATTSET(x)            (((x) & 0xff) << 0)
+#define FMC2_PATT_ATTWAIT(x)           (((x) & 0xff) << 8)
+#define FMC2_PATT_ATTHOLD(x)           (((x) & 0xff) << 16)
+#define FMC2_PATT_ATTHIZ(x)            (((x) & 0xff) << 24)
+#define FMC2_PATT_DEFAULT              0x0a0a0a0a
+
+/* Register: FMC2_CSQCR */
+#define FMC2_CSQCR_CSQSTART            BIT(0)
+
+/* Register: FMC2_CSQCFGR1 */
+#define FMC2_CSQCFGR1_CMD2EN           BIT(1)
+#define FMC2_CSQCFGR1_DMADEN           BIT(2)
+#define FMC2_CSQCFGR1_ACYNBR(x)                (((x) & 0x7) << 4)
+#define FMC2_CSQCFGR1_CMD1(x)          (((x) & 0xff) << 8)
+#define FMC2_CSQCFGR1_CMD2(x)          (((x) & 0xff) << 16)
+#define FMC2_CSQCFGR1_CMD1T            BIT(24)
+#define FMC2_CSQCFGR1_CMD2T            BIT(25)
+
+/* Register: FMC2_CSQCFGR2 */
+#define FMC2_CSQCFGR2_SQSDTEN          BIT(0)
+#define FMC2_CSQCFGR2_RCMD2EN          BIT(1)
+#define FMC2_CSQCFGR2_DMASEN           BIT(2)
+#define FMC2_CSQCFGR2_RCMD1(x)         (((x) & 0xff) << 8)
+#define FMC2_CSQCFGR2_RCMD2(x)         (((x) & 0xff) << 16)
+#define FMC2_CSQCFGR2_RCMD1T           BIT(24)
+#define FMC2_CSQCFGR2_RCMD2T           BIT(25)
+
+/* Register: FMC2_CSQCFGR3 */
+#define FMC2_CSQCFGR3_SNBR(x)          (((x) & 0x1f) << 8)
+#define FMC2_CSQCFGR3_AC1T             BIT(16)
+#define FMC2_CSQCFGR3_AC2T             BIT(17)
+#define FMC2_CSQCFGR3_AC3T             BIT(18)
+#define FMC2_CSQCFGR3_AC4T             BIT(19)
+#define FMC2_CSQCFGR3_AC5T             BIT(20)
+#define FMC2_CSQCFGR3_SDT              BIT(21)
+#define FMC2_CSQCFGR3_RAC1T            BIT(22)
+#define FMC2_CSQCFGR3_RAC2T            BIT(23)
+
+/* Register: FMC2_CSQCAR1 */
+#define FMC2_CSQCAR1_ADDC1(x)          (((x) & 0xff) << 0)
+#define FMC2_CSQCAR1_ADDC2(x)          (((x) & 0xff) << 8)
+#define FMC2_CSQCAR1_ADDC3(x)          (((x) & 0xff) << 16)
+#define FMC2_CSQCAR1_ADDC4(x)          (((x) & 0xff) << 24)
+
+/* Register: FMC2_CSQCAR2 */
+#define FMC2_CSQCAR2_ADDC5(x)          (((x) & 0xff) << 0)
+#define FMC2_CSQCAR2_NANDCEN(x)                (((x) & 0x3) << 10)
+#define FMC2_CSQCAR2_SAO(x)            (((x) & 0xffff) << 16)
+
+/* Register: FMC2_CSQIER */
+#define FMC2_CSQIER_TCIE               BIT(0)
+
+/* Register: FMC2_CSQICR */
+#define FMC2_CSQICR_CLEAR_IRQ          GENMASK(4, 0)
+
+/* Register: FMC2_CSQEMSR */
+#define FMC2_CSQEMSR_SEM               GENMASK(15, 0)
+
+/* Register: FMC2_BCHIER */
+#define FMC2_BCHIER_DERIE              BIT(1)
+#define FMC2_BCHIER_EPBRIE             BIT(4)
+
+/* Register: FMC2_BCHICR */
+#define FMC2_BCHICR_CLEAR_IRQ          GENMASK(4, 0)
+
+/* Register: FMC2_BCHDSR0 */
+#define FMC2_BCHDSR0_DUE               BIT(0)
+#define FMC2_BCHDSR0_DEF               BIT(1)
+#define FMC2_BCHDSR0_DEN_MASK          GENMASK(7, 4)
+#define FMC2_BCHDSR0_DEN_SHIFT         4
+
+/* Register: FMC2_BCHDSR1 */
+#define FMC2_BCHDSR1_EBP1_MASK         GENMASK(12, 0)
+#define FMC2_BCHDSR1_EBP2_MASK         GENMASK(28, 16)
+#define FMC2_BCHDSR1_EBP2_SHIFT                16
+
+/* Register: FMC2_BCHDSR2 */
+#define FMC2_BCHDSR2_EBP3_MASK         GENMASK(12, 0)
+#define FMC2_BCHDSR2_EBP4_MASK         GENMASK(28, 16)
+#define FMC2_BCHDSR2_EBP4_SHIFT                16
+
+/* Register: FMC2_BCHDSR3 */
+#define FMC2_BCHDSR3_EBP5_MASK         GENMASK(12, 0)
+#define FMC2_BCHDSR3_EBP6_MASK         GENMASK(28, 16)
+#define FMC2_BCHDSR3_EBP6_SHIFT                16
+
+/* Register: FMC2_BCHDSR4 */
+#define FMC2_BCHDSR4_EBP7_MASK         GENMASK(12, 0)
+#define FMC2_BCHDSR4_EBP8_MASK         GENMASK(28, 16)
+#define FMC2_BCHDSR4_EBP8_SHIFT                16
+
+enum stm32_fmc2_ecc {
+       FMC2_ECC_HAM = 1,
+       FMC2_ECC_BCH4 = 4,
+       FMC2_ECC_BCH8 = 8
+};
+
+enum stm32_fmc2_irq_state {
+       FMC2_IRQ_UNKNOWN = 0,
+       FMC2_IRQ_BCH,
+       FMC2_IRQ_SEQ
+};
+
+struct stm32_fmc2_timings {
+       u8 tclr;
+       u8 tar;
+       u8 thiz;
+       u8 twait;
+       u8 thold_mem;
+       u8 tset_mem;
+       u8 thold_att;
+       u8 tset_att;
+};
+
+struct stm32_fmc2_nand {
+       struct nand_chip chip;
+       struct stm32_fmc2_timings timings;
+       int ncs;
+       int cs_used[FMC2_MAX_CE];
+};
+
+static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
+{
+       return container_of(chip, struct stm32_fmc2_nand, chip);
+}
+
+struct stm32_fmc2_nfc {
+       struct nand_controller base;
+       struct stm32_fmc2_nand nand;
+       struct device *dev;
+       void __iomem *io_base;
+       void __iomem *data_base[FMC2_MAX_CE];
+       void __iomem *cmd_base[FMC2_MAX_CE];
+       void __iomem *addr_base[FMC2_MAX_CE];
+       phys_addr_t io_phys_addr;
+       phys_addr_t data_phys_addr[FMC2_MAX_CE];
+       struct clk *clk;
+       u8 irq_state;
+
+       struct dma_chan *dma_tx_ch;
+       struct dma_chan *dma_rx_ch;
+       struct dma_chan *dma_ecc_ch;
+       struct sg_table dma_data_sg;
+       struct sg_table dma_ecc_sg;
+       u8 *ecc_buf;
+       int dma_ecc_len;
+
+       struct completion complete;
+       struct completion dma_data_complete;
+       struct completion dma_ecc_complete;
+
+       u8 cs_assigned;
+       int cs_sel;
+};
+
+static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base)
+{
+       return container_of(base, struct stm32_fmc2_nfc, base);
+}
+
+/* Timings configuration */
+static void stm32_fmc2_timings_init(struct nand_chip *chip)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
+       struct stm32_fmc2_timings *timings = &nand->timings;
+       u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
+       u32 pmem, patt;
+
+       /* Set tclr/tar timings */
+       pcr &= ~FMC2_PCR_TCLR_MASK;
+       pcr |= FMC2_PCR_TCLR(timings->tclr);
+       pcr &= ~FMC2_PCR_TAR_MASK;
+       pcr |= FMC2_PCR_TAR(timings->tar);
+
+       /* Set tset/twait/thold/thiz timings in common bank */
+       pmem = FMC2_PMEM_MEMSET(timings->tset_mem);
+       pmem |= FMC2_PMEM_MEMWAIT(timings->twait);
+       pmem |= FMC2_PMEM_MEMHOLD(timings->thold_mem);
+       pmem |= FMC2_PMEM_MEMHIZ(timings->thiz);
+
+       /* Set tset/twait/thold/thiz timings in attribut bank */
+       patt = FMC2_PATT_ATTSET(timings->tset_att);
+       patt |= FMC2_PATT_ATTWAIT(timings->twait);
+       patt |= FMC2_PATT_ATTHOLD(timings->thold_att);
+       patt |= FMC2_PATT_ATTHIZ(timings->thiz);
+
+       writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
+       writel_relaxed(pmem, fmc2->io_base + FMC2_PMEM);
+       writel_relaxed(patt, fmc2->io_base + FMC2_PATT);
+}
+
+/* Controller configuration */
+static void stm32_fmc2_setup(struct nand_chip *chip)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
+
+       /* Configure ECC algorithm (default configuration is Hamming) */
+       pcr &= ~FMC2_PCR_ECCALG;
+       pcr &= ~FMC2_PCR_BCHECC;
+       if (chip->ecc.strength == FMC2_ECC_BCH8) {
+               pcr |= FMC2_PCR_ECCALG;
+               pcr |= FMC2_PCR_BCHECC;
+       } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
+               pcr |= FMC2_PCR_ECCALG;
+       }
+
+       /* Set buswidth */
+       pcr &= ~FMC2_PCR_PWID_MASK;
+       if (chip->options & NAND_BUSWIDTH_16)
+               pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
+
+       /* Set ECC sector size */
+       pcr &= ~FMC2_PCR_ECCSS_MASK;
+       pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512);
+
+       writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
+}
+
+/* Select target */
+static int stm32_fmc2_select_chip(struct nand_chip *chip, int chipnr)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
+       struct dma_slave_config dma_cfg;
+       int ret;
+
+       if (nand->cs_used[chipnr] == fmc2->cs_sel)
+               return 0;
+
+       fmc2->cs_sel = nand->cs_used[chipnr];
+
+       /* FMC2 setup routine */
+       stm32_fmc2_setup(chip);
+
+       /* Apply timings */
+       stm32_fmc2_timings_init(chip);
+
+       if (fmc2->dma_tx_ch && fmc2->dma_rx_ch) {
+               memset(&dma_cfg, 0, sizeof(dma_cfg));
+               dma_cfg.src_addr = fmc2->data_phys_addr[fmc2->cs_sel];
+               dma_cfg.dst_addr = fmc2->data_phys_addr[fmc2->cs_sel];
+               dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+               dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+               dma_cfg.src_maxburst = 32;
+               dma_cfg.dst_maxburst = 32;
+
+               ret = dmaengine_slave_config(fmc2->dma_tx_ch, &dma_cfg);
+               if (ret) {
+                       dev_err(fmc2->dev, "tx DMA engine slave config failed\n");
+                       return ret;
+               }
+
+               ret = dmaengine_slave_config(fmc2->dma_rx_ch, &dma_cfg);
+               if (ret) {
+                       dev_err(fmc2->dev, "rx DMA engine slave config failed\n");
+                       return ret;
+               }
+       }
+
+       if (fmc2->dma_ecc_ch) {
+               /*
+                * Hamming: we read HECCR register
+                * BCH4/BCH8: we read BCHDSRSx registers
+                */
+               memset(&dma_cfg, 0, sizeof(dma_cfg));
+               dma_cfg.src_addr = fmc2->io_phys_addr;
+               dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ?
+                                   FMC2_HECCR : FMC2_BCHDSR0;
+               dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+
+               ret = dmaengine_slave_config(fmc2->dma_ecc_ch, &dma_cfg);
+               if (ret) {
+                       dev_err(fmc2->dev, "ECC DMA engine slave config failed\n");
+                       return ret;
+               }
+
+               /* Calculate ECC length needed for one sector */
+               fmc2->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ?
+                                   FMC2_HECCR_LEN : FMC2_BCHDSRS_LEN;
+       }
+
+       return 0;
+}
+
+/* Set bus width to 16-bit or 8-bit */
+static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
+{
+       u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
+
+       pcr &= ~FMC2_PCR_PWID_MASK;
+       if (set)
+               pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
+       writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
+}
+
+/* Enable/disable ECC */
+static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
+{
+       u32 pcr = readl(fmc2->io_base + FMC2_PCR);
+
+       pcr &= ~FMC2_PCR_ECCEN;
+       if (enable)
+               pcr |= FMC2_PCR_ECCEN;
+       writel(pcr, fmc2->io_base + FMC2_PCR);
+}
+
+/* Enable irq sources in case of the sequencer is used */
+static inline void stm32_fmc2_enable_seq_irq(struct stm32_fmc2_nfc *fmc2)
+{
+       u32 csqier = readl_relaxed(fmc2->io_base + FMC2_CSQIER);
+
+       csqier |= FMC2_CSQIER_TCIE;
+
+       fmc2->irq_state = FMC2_IRQ_SEQ;
+
+       writel_relaxed(csqier, fmc2->io_base + FMC2_CSQIER);
+}
+
+/* Disable irq sources in case of the sequencer is used */
+static inline void stm32_fmc2_disable_seq_irq(struct stm32_fmc2_nfc *fmc2)
+{
+       u32 csqier = readl_relaxed(fmc2->io_base + FMC2_CSQIER);
+
+       csqier &= ~FMC2_CSQIER_TCIE;
+
+       writel_relaxed(csqier, fmc2->io_base + FMC2_CSQIER);
+
+       fmc2->irq_state = FMC2_IRQ_UNKNOWN;
+}
+
+/* Clear irq sources in case of the sequencer is used */
+static inline void stm32_fmc2_clear_seq_irq(struct stm32_fmc2_nfc *fmc2)
+{
+       writel_relaxed(FMC2_CSQICR_CLEAR_IRQ, fmc2->io_base + FMC2_CSQICR);
+}
+
+/* Enable irq sources in case of bch is used */
+static inline void stm32_fmc2_enable_bch_irq(struct stm32_fmc2_nfc *fmc2,
+                                            int mode)
+{
+       u32 bchier = readl_relaxed(fmc2->io_base + FMC2_BCHIER);
+
+       if (mode == NAND_ECC_WRITE)
+               bchier |= FMC2_BCHIER_EPBRIE;
+       else
+               bchier |= FMC2_BCHIER_DERIE;
+
+       fmc2->irq_state = FMC2_IRQ_BCH;
+
+       writel_relaxed(bchier, fmc2->io_base + FMC2_BCHIER);
+}
+
+/* Disable irq sources in case of bch is used */
+static inline void stm32_fmc2_disable_bch_irq(struct stm32_fmc2_nfc *fmc2)
+{
+       u32 bchier = readl_relaxed(fmc2->io_base + FMC2_BCHIER);
+
+       bchier &= ~FMC2_BCHIER_DERIE;
+       bchier &= ~FMC2_BCHIER_EPBRIE;
+
+       writel_relaxed(bchier, fmc2->io_base + FMC2_BCHIER);
+
+       fmc2->irq_state = FMC2_IRQ_UNKNOWN;
+}
+
+/* Clear irq sources in case of bch is used */
+static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)
+{
+       writel_relaxed(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
+}
+
+/*
+ * Enable ECC logic and reset syndrome/parity bits previously calculated
+ * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
+ */
+static void stm32_fmc2_hwctl(struct nand_chip *chip, int mode)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+
+       stm32_fmc2_set_ecc(fmc2, false);
+
+       if (chip->ecc.strength != FMC2_ECC_HAM) {
+               u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
+
+               if (mode == NAND_ECC_WRITE)
+                       pcr |= FMC2_PCR_WEN;
+               else
+                       pcr &= ~FMC2_PCR_WEN;
+               writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
+
+               reinit_completion(&fmc2->complete);
+               stm32_fmc2_clear_bch_irq(fmc2);
+               stm32_fmc2_enable_bch_irq(fmc2, mode);
+       }
+
+       stm32_fmc2_set_ecc(fmc2, true);
+}
+
+/*
+ * ECC Hamming calculation
+ * ECC is 3 bytes for 512 bytes of data (supports error correction up to
+ * max of 1-bit)
+ */
+static inline void stm32_fmc2_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
+{
+       ecc[0] = ecc_sta;
+       ecc[1] = ecc_sta >> 8;
+       ecc[2] = ecc_sta >> 16;
+}
+
+static int stm32_fmc2_ham_calculate(struct nand_chip *chip, const u8 *data,
+                                   u8 *ecc)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       u32 sr, heccr;
+       int ret;
+
+       ret = readl_relaxed_poll_timeout(fmc2->io_base + FMC2_SR,
+                                        sr, sr & FMC2_SR_NWRF, 10, 1000);
+       if (ret) {
+               dev_err(fmc2->dev, "ham timeout\n");
+               return ret;
+       }
+
+       heccr = readl_relaxed(fmc2->io_base + FMC2_HECCR);
+
+       stm32_fmc2_ham_set_ecc(heccr, ecc);
+
+       /* Disable ECC */
+       stm32_fmc2_set_ecc(fmc2, false);
+
+       return 0;
+}
+
+static int stm32_fmc2_ham_correct(struct nand_chip *chip, u8 *dat,
+                                 u8 *read_ecc, u8 *calc_ecc)
+{
+       u8 bit_position = 0, b0, b1, b2;
+       u32 byte_addr = 0, b;
+       u32 i, shifting = 1;
+
+       /* Indicate which bit and byte is faulty (if any) */
+       b0 = read_ecc[0] ^ calc_ecc[0];
+       b1 = read_ecc[1] ^ calc_ecc[1];
+       b2 = read_ecc[2] ^ calc_ecc[2];
+       b = b0 | (b1 << 8) | (b2 << 16);
+
+       /* No errors */
+       if (likely(!b))
+               return 0;
+
+       /* Calculate bit position */
+       for (i = 0; i < 3; i++) {
+               switch (b % 4) {
+               case 2:
+                       bit_position += shifting;
+               case 1:
+                       break;
+               default:
+                       return -EBADMSG;
+               }
+               shifting <<= 1;
+               b >>= 2;
+       }
+
+       /* Calculate byte position */
+       shifting = 1;
+       for (i = 0; i < 9; i++) {
+               switch (b % 4) {
+               case 2:
+                       byte_addr += shifting;
+               case 1:
+                       break;
+               default:
+                       return -EBADMSG;
+               }
+               shifting <<= 1;
+               b >>= 2;
+       }
+
+       /* Flip the bit */
+       dat[byte_addr] ^= (1 << bit_position);
+
+       return 1;
+}
+
+/*
+ * ECC BCH calculation and correction
+ * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
+ * max of 4-bit/8-bit)
+ */
+static int stm32_fmc2_bch_calculate(struct nand_chip *chip, const u8 *data,
+                                   u8 *ecc)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       u32 bchpbr;
+
+       /* Wait until the BCH code is ready */
+       if (!wait_for_completion_timeout(&fmc2->complete,
+                                        msecs_to_jiffies(1000))) {
+               dev_err(fmc2->dev, "bch timeout\n");
+               stm32_fmc2_disable_bch_irq(fmc2);
+               return -ETIMEDOUT;
+       }
+
+       /* Read parity bits */
+       bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR1);
+       ecc[0] = bchpbr;
+       ecc[1] = bchpbr >> 8;
+       ecc[2] = bchpbr >> 16;
+       ecc[3] = bchpbr >> 24;
+
+       bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR2);
+       ecc[4] = bchpbr;
+       ecc[5] = bchpbr >> 8;
+       ecc[6] = bchpbr >> 16;
+
+       if (chip->ecc.strength == FMC2_ECC_BCH8) {
+               ecc[7] = bchpbr >> 24;
+
+               bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR3);
+               ecc[8] = bchpbr;
+               ecc[9] = bchpbr >> 8;
+               ecc[10] = bchpbr >> 16;
+               ecc[11] = bchpbr >> 24;
+
+               bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR4);
+               ecc[12] = bchpbr;
+       }
+
+       /* Disable ECC */
+       stm32_fmc2_set_ecc(fmc2, false);
+
+       return 0;
+}
+
+/* BCH algorithm correction */
+static int stm32_fmc2_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)
+{
+       u32 bchdsr0 = ecc_sta[0];
+       u32 bchdsr1 = ecc_sta[1];
+       u32 bchdsr2 = ecc_sta[2];
+       u32 bchdsr3 = ecc_sta[3];
+       u32 bchdsr4 = ecc_sta[4];
+       u16 pos[8];
+       int i, den;
+       unsigned int nb_errs = 0;
+
+       /* No errors found */
+       if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
+               return 0;
+
+       /* Too many errors detected */
+       if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
+               return -EBADMSG;
+
+       pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK;
+       pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT;
+       pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK;
+       pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT;
+       pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK;
+       pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT;
+       pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK;
+       pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT;
+
+       den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT;
+       for (i = 0; i < den; i++) {
+               if (pos[i] < eccsize * 8) {
+                       change_bit(pos[i], (unsigned long *)dat);
+                       nb_errs++;
+               }
+       }
+
+       return nb_errs;
+}
+
+static int stm32_fmc2_bch_correct(struct nand_chip *chip, u8 *dat,
+                                 u8 *read_ecc, u8 *calc_ecc)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       u32 ecc_sta[5];
+
+       /* Wait until the decoding error is ready */
+       if (!wait_for_completion_timeout(&fmc2->complete,
+                                        msecs_to_jiffies(1000))) {
+               dev_err(fmc2->dev, "bch timeout\n");
+               stm32_fmc2_disable_bch_irq(fmc2);
+               return -ETIMEDOUT;
+       }
+
+       ecc_sta[0] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR0);
+       ecc_sta[1] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR1);
+       ecc_sta[2] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR2);
+       ecc_sta[3] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR3);
+       ecc_sta[4] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR4);
+
+       /* Disable ECC */
+       stm32_fmc2_set_ecc(fmc2, false);
+
+       return stm32_fmc2_bch_decode(chip->ecc.size, dat, ecc_sta);
+}
+
+static int stm32_fmc2_read_page(struct nand_chip *chip, u8 *buf,
+                               int oob_required, int page)
+{
+       struct mtd_info *mtd = nand_to_mtd(chip);
+       int ret, i, s, stat, eccsize = chip->ecc.size;
+       int eccbytes = chip->ecc.bytes;
+       int eccsteps = chip->ecc.steps;
+       int eccstrength = chip->ecc.strength;
+       u8 *p = buf;
+       u8 *ecc_calc = chip->ecc.calc_buf;
+       u8 *ecc_code = chip->ecc.code_buf;
+       unsigned int max_bitflips = 0;
+
+       ret = nand_read_page_op(chip, page, 0, NULL, 0);
+       if (ret)
+               return ret;
+
+       for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
+            s++, i += eccbytes, p += eccsize) {
+               chip->ecc.hwctl(chip, NAND_ECC_READ);
+
+               /* Read the nand page sector (512 bytes) */
+               ret = nand_change_read_column_op(chip, s * eccsize, p,
+                                                eccsize, false);
+               if (ret)
+                       return ret;
+
+               /* Read the corresponding ECC bytes */
+               ret = nand_change_read_column_op(chip, i, ecc_code,
+                                                eccbytes, false);
+               if (ret)
+                       return ret;
+
+               /* Correct the data */
+               stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc);
+               if (stat == -EBADMSG)
+                       /* Check for empty pages with bitflips */
+                       stat = nand_check_erased_ecc_chunk(p, eccsize,
+                                                          ecc_code, eccbytes,
+                                                          NULL, 0,
+                                                          eccstrength);
+
+               if (stat < 0) {
+                       mtd->ecc_stats.failed++;
+               } else {
+                       mtd->ecc_stats.corrected += stat;
+                       max_bitflips = max_t(unsigned int, max_bitflips, stat);
+               }
+       }
+
+       /* Read oob */
+       if (oob_required) {
+               ret = nand_change_read_column_op(chip, mtd->writesize,
+                                                chip->oob_poi, mtd->oobsize,
+                                                false);
+               if (ret)
+                       return ret;
+       }
+
+       return max_bitflips;
+}
+
+/* Sequencer read/write configuration */
+static void stm32_fmc2_rw_page_init(struct nand_chip *chip, int page,
+                                   int raw, bool write_data)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       struct mtd_info *mtd = nand_to_mtd(chip);
+       u32 csqcfgr1, csqcfgr2, csqcfgr3;
+       u32 csqar1, csqar2;
+       u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN;
+       u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
+
+       if (write_data)
+               pcr |= FMC2_PCR_WEN;
+       else
+               pcr &= ~FMC2_PCR_WEN;
+       writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
+
+       /*
+        * - Set Program Page/Page Read command
+        * - Enable DMA request data
+        * - Set timings
+        */
+       csqcfgr1 = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T;
+       if (write_data)
+               csqcfgr1 |= FMC2_CSQCFGR1_CMD1(NAND_CMD_SEQIN);
+       else
+               csqcfgr1 |= FMC2_CSQCFGR1_CMD1(NAND_CMD_READ0) |
+                           FMC2_CSQCFGR1_CMD2EN |
+                           FMC2_CSQCFGR1_CMD2(NAND_CMD_READSTART) |
+                           FMC2_CSQCFGR1_CMD2T;
+
+       /*
+        * - Set Random Data Input/Random Data Read command
+        * - Enable the sequencer to access the Spare data area
+        * - Enable  DMA request status decoding for read
+        * - Set timings
+        */
+       if (write_data)
+               csqcfgr2 = FMC2_CSQCFGR2_RCMD1(NAND_CMD_RNDIN);
+       else
+               csqcfgr2 = FMC2_CSQCFGR2_RCMD1(NAND_CMD_RNDOUT) |
+                          FMC2_CSQCFGR2_RCMD2EN |
+                          FMC2_CSQCFGR2_RCMD2(NAND_CMD_RNDOUTSTART) |
+                          FMC2_CSQCFGR2_RCMD1T |
+                          FMC2_CSQCFGR2_RCMD2T;
+       if (!raw) {
+               csqcfgr2 |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN;
+               csqcfgr2 |= FMC2_CSQCFGR2_SQSDTEN;
+       }
+
+       /*
+        * - Set the number of sectors to be written
+        * - Set timings
+        */
+       csqcfgr3 = FMC2_CSQCFGR3_SNBR(chip->ecc.steps - 1);
+       if (write_data) {
+               csqcfgr3 |= FMC2_CSQCFGR3_RAC2T;
+               if (chip->options & NAND_ROW_ADDR_3)
+                       csqcfgr3 |= FMC2_CSQCFGR3_AC5T;
+               else
+                       csqcfgr3 |= FMC2_CSQCFGR3_AC4T;
+       }
+
+       /*
+        * Set the fourth first address cycles
+        * Byte 1 and byte 2 => column, we start at 0x0
+        * Byte 3 and byte 4 => page
+        */
+       csqar1 = FMC2_CSQCAR1_ADDC3(page);
+       csqar1 |= FMC2_CSQCAR1_ADDC4(page >> 8);
+
+       /*
+        * - Set chip enable number
+        * - Set ECC byte offset in the spare area
+        * - Calculate the number of address cycles to be issued
+        * - Set byte 5 of address cycle if needed
+        */
+       csqar2 = FMC2_CSQCAR2_NANDCEN(fmc2->cs_sel);
+       if (chip->options & NAND_BUSWIDTH_16)
+               csqar2 |= FMC2_CSQCAR2_SAO(ecc_offset >> 1);
+       else
+               csqar2 |= FMC2_CSQCAR2_SAO(ecc_offset);
+       if (chip->options & NAND_ROW_ADDR_3) {
+               csqcfgr1 |= FMC2_CSQCFGR1_ACYNBR(5);
+               csqar2 |= FMC2_CSQCAR2_ADDC5(page >> 16);
+       } else {
+               csqcfgr1 |= FMC2_CSQCFGR1_ACYNBR(4);
+       }
+
+       writel_relaxed(csqcfgr1, fmc2->io_base + FMC2_CSQCFGR1);
+       writel_relaxed(csqcfgr2, fmc2->io_base + FMC2_CSQCFGR2);
+       writel_relaxed(csqcfgr3, fmc2->io_base + FMC2_CSQCFGR3);
+       writel_relaxed(csqar1, fmc2->io_base + FMC2_CSQAR1);
+       writel_relaxed(csqar2, fmc2->io_base + FMC2_CSQAR2);
+}
+
+static void stm32_fmc2_dma_callback(void *arg)
+{
+       complete((struct completion *)arg);
+}
+
+/* Read/write data from/to a page */
+static int stm32_fmc2_xfer(struct nand_chip *chip, const u8 *buf,
+                          int raw, bool write_data)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       struct dma_async_tx_descriptor *desc_data, *desc_ecc;
+       struct scatterlist *sg;
+       struct dma_chan *dma_ch = fmc2->dma_rx_ch;
+       enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE;
+       enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM;
+       u32 csqcr = readl_relaxed(fmc2->io_base + FMC2_CSQCR);
+       int eccsteps = chip->ecc.steps;
+       int eccsize = chip->ecc.size;
+       const u8 *p = buf;
+       int s, ret;
+
+       /* Configure DMA data */
+       if (write_data) {
+               dma_data_dir = DMA_TO_DEVICE;
+               dma_transfer_dir = DMA_MEM_TO_DEV;
+               dma_ch = fmc2->dma_tx_ch;
+       }
+
+       for_each_sg(fmc2->dma_data_sg.sgl, sg, eccsteps, s) {
+               sg_set_buf(sg, p, eccsize);
+               p += eccsize;
+       }
+
+       ret = dma_map_sg(fmc2->dev, fmc2->dma_data_sg.sgl,
+                        eccsteps, dma_data_dir);
+       if (ret < 0)
+               return ret;
+
+       desc_data = dmaengine_prep_slave_sg(dma_ch, fmc2->dma_data_sg.sgl,
+                                           eccsteps, dma_transfer_dir,
+                                           DMA_PREP_INTERRUPT);
+       if (!desc_data) {
+               ret = -ENOMEM;
+               goto err_unmap_data;
+       }
+
+       reinit_completion(&fmc2->dma_data_complete);
+       reinit_completion(&fmc2->complete);
+       desc_data->callback = stm32_fmc2_dma_callback;
+       desc_data->callback_param = &fmc2->dma_data_complete;
+       ret = dma_submit_error(dmaengine_submit(desc_data));
+       if (ret)
+               goto err_unmap_data;
+
+       dma_async_issue_pending(dma_ch);
+
+       if (!write_data && !raw) {
+               /* Configure DMA ECC status */
+               p = fmc2->ecc_buf;
+               for_each_sg(fmc2->dma_ecc_sg.sgl, sg, eccsteps, s) {
+                       sg_set_buf(sg, p, fmc2->dma_ecc_len);
+                       p += fmc2->dma_ecc_len;
+               }
+
+               ret = dma_map_sg(fmc2->dev, fmc2->dma_ecc_sg.sgl,
+                                eccsteps, dma_data_dir);
+               if (ret < 0)
+                       goto err_unmap_data;
+
+               desc_ecc = dmaengine_prep_slave_sg(fmc2->dma_ecc_ch,
+                                                  fmc2->dma_ecc_sg.sgl,
+                                                  eccsteps, dma_transfer_dir,
+                                                  DMA_PREP_INTERRUPT);
+               if (!desc_ecc) {
+                       ret = -ENOMEM;
+                       goto err_unmap_ecc;
+               }
+
+               reinit_completion(&fmc2->dma_ecc_complete);
+               desc_ecc->callback = stm32_fmc2_dma_callback;
+               desc_ecc->callback_param = &fmc2->dma_ecc_complete;
+               ret = dma_submit_error(dmaengine_submit(desc_ecc));
+               if (ret)
+                       goto err_unmap_ecc;
+
+               dma_async_issue_pending(fmc2->dma_ecc_ch);
+       }
+
+       stm32_fmc2_clear_seq_irq(fmc2);
+       stm32_fmc2_enable_seq_irq(fmc2);
+
+       /* Start the transfer */
+       csqcr |= FMC2_CSQCR_CSQSTART;
+       writel_relaxed(csqcr, fmc2->io_base + FMC2_CSQCR);
+
+       /* Wait end of sequencer transfer */
+       if (!wait_for_completion_timeout(&fmc2->complete,
+                                        msecs_to_jiffies(1000))) {
+               dev_err(fmc2->dev, "seq timeout\n");
+               stm32_fmc2_disable_seq_irq(fmc2);
+               dmaengine_terminate_all(dma_ch);
+               if (!write_data && !raw)
+                       dmaengine_terminate_all(fmc2->dma_ecc_ch);
+               ret = -ETIMEDOUT;
+               goto err_unmap_ecc;
+       }
+
+       /* Wait DMA data transfer completion */
+       if (!wait_for_completion_timeout(&fmc2->dma_data_complete,
+                                        msecs_to_jiffies(100))) {
+               dev_err(fmc2->dev, "data DMA timeout\n");
+               dmaengine_terminate_all(dma_ch);
+               ret = -ETIMEDOUT;
+       }
+
+       /* Wait DMA ECC transfer completion */
+       if (!write_data && !raw) {
+               if (!wait_for_completion_timeout(&fmc2->dma_ecc_complete,
+                                                msecs_to_jiffies(100))) {
+                       dev_err(fmc2->dev, "ECC DMA timeout\n");
+                       dmaengine_terminate_all(fmc2->dma_ecc_ch);
+                       ret = -ETIMEDOUT;
+               }
+       }
+
+err_unmap_ecc:
+       if (!write_data && !raw)
+               dma_unmap_sg(fmc2->dev, fmc2->dma_ecc_sg.sgl,
+                            eccsteps, dma_data_dir);
+
+err_unmap_data:
+       dma_unmap_sg(fmc2->dev, fmc2->dma_data_sg.sgl, eccsteps, dma_data_dir);
+
+       return ret;
+}
+
+static int stm32_fmc2_sequencer_write(struct nand_chip *chip,
+                                     const u8 *buf, int oob_required,
+                                     int page, int raw)
+{
+       struct mtd_info *mtd = nand_to_mtd(chip);
+       int ret;
+
+       /* Configure the sequencer */
+       stm32_fmc2_rw_page_init(chip, page, raw, true);
+
+       /* Write the page */
+       ret = stm32_fmc2_xfer(chip, buf, raw, true);
+       if (ret)
+               return ret;
+
+       /* Write oob */
+       if (oob_required) {
+               ret = nand_change_write_column_op(chip, mtd->writesize,
+                                                 chip->oob_poi, mtd->oobsize,
+                                                 false);
+               if (ret)
+                       return ret;
+       }
+
+       return nand_prog_page_end_op(chip);
+}
+
+static int stm32_fmc2_sequencer_write_page(struct nand_chip *chip,
+                                          const u8 *buf,
+                                          int oob_required,
+                                          int page)
+{
+       int ret;
+
+       /* Select the target */
+       ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
+       if (ret)
+               return ret;
+
+       return stm32_fmc2_sequencer_write(chip, buf, oob_required, page, false);
+}
+
+static int stm32_fmc2_sequencer_write_page_raw(struct nand_chip *chip,
+                                              const u8 *buf,
+                                              int oob_required,
+                                              int page)
+{
+       int ret;
+
+       /* Select the target */
+       ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
+       if (ret)
+               return ret;
+
+       return stm32_fmc2_sequencer_write(chip, buf, oob_required, page, true);
+}
+
+/* Get a status indicating which sectors have errors */
+static inline u16 stm32_fmc2_get_mapping_status(struct stm32_fmc2_nfc *fmc2)
+{
+       u32 csqemsr = readl_relaxed(fmc2->io_base + FMC2_CSQEMSR);
+
+       return csqemsr & FMC2_CSQEMSR_SEM;
+}
+
+static int stm32_fmc2_sequencer_correct(struct nand_chip *chip, u8 *dat,
+                                       u8 *read_ecc, u8 *calc_ecc)
+{
+       struct mtd_info *mtd = nand_to_mtd(chip);
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       int eccbytes = chip->ecc.bytes;
+       int eccsteps = chip->ecc.steps;
+       int eccstrength = chip->ecc.strength;
+       int i, s, eccsize = chip->ecc.size;
+       u32 *ecc_sta = (u32 *)fmc2->ecc_buf;
+       u16 sta_map = stm32_fmc2_get_mapping_status(fmc2);
+       unsigned int max_bitflips = 0;
+
+       for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, dat += eccsize) {
+               int stat = 0;
+
+               if (eccstrength == FMC2_ECC_HAM) {
+                       /* Ecc_sta = FMC2_HECCR */
+                       if (sta_map & BIT(s)) {
+                               stm32_fmc2_ham_set_ecc(*ecc_sta, &calc_ecc[i]);
+                               stat = stm32_fmc2_ham_correct(chip, dat,
+                                                             &read_ecc[i],
+                                                             &calc_ecc[i]);
+                       }
+                       ecc_sta++;
+               } else {
+                       /*
+                        * Ecc_sta[0] = FMC2_BCHDSR0
+                        * Ecc_sta[1] = FMC2_BCHDSR1
+                        * Ecc_sta[2] = FMC2_BCHDSR2
+                        * Ecc_sta[3] = FMC2_BCHDSR3
+                        * Ecc_sta[4] = FMC2_BCHDSR4
+                        */
+                       if (sta_map & BIT(s))
+                               stat = stm32_fmc2_bch_decode(eccsize, dat,
+                                                            ecc_sta);
+                       ecc_sta += 5;
+               }
+
+               if (stat == -EBADMSG)
+                       /* Check for empty pages with bitflips */
+                       stat = nand_check_erased_ecc_chunk(dat, eccsize,
+                                                          &read_ecc[i],
+                                                          eccbytes,
+                                                          NULL, 0,
+                                                          eccstrength);
+
+               if (stat < 0) {
+                       mtd->ecc_stats.failed++;
+               } else {
+                       mtd->ecc_stats.corrected += stat;
+                       max_bitflips = max_t(unsigned int, max_bitflips, stat);
+               }
+       }
+
+       return max_bitflips;
+}
+
+static int stm32_fmc2_sequencer_read_page(struct nand_chip *chip, u8 *buf,
+                                         int oob_required, int page)
+{
+       struct mtd_info *mtd = nand_to_mtd(chip);
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       u8 *ecc_calc = chip->ecc.calc_buf;
+       u8 *ecc_code = chip->ecc.code_buf;
+       u16 sta_map;
+       int ret;
+
+       /* Select the target */
+       ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
+       if (ret)
+               return ret;
+
+       /* Configure the sequencer */
+       stm32_fmc2_rw_page_init(chip, page, 0, false);
+
+       /* Read the page */
+       ret = stm32_fmc2_xfer(chip, buf, 0, false);
+       if (ret)
+               return ret;
+
+       sta_map = stm32_fmc2_get_mapping_status(fmc2);
+
+       /* Check if errors happen */
+       if (likely(!sta_map)) {
+               if (oob_required)
+                       return nand_change_read_column_op(chip, mtd->writesize,
+                                                         chip->oob_poi,
+                                                         mtd->oobsize, false);
+
+               return 0;
+       }
+
+       /* Read oob */
+       ret = nand_change_read_column_op(chip, mtd->writesize,
+                                        chip->oob_poi, mtd->oobsize, false);
+       if (ret)
+               return ret;
+
+       ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
+                                        chip->ecc.total);
+       if (ret)
+               return ret;
+
+       /* Correct data */
+       return chip->ecc.correct(chip, buf, ecc_code, ecc_calc);
+}
+
+static int stm32_fmc2_sequencer_read_page_raw(struct nand_chip *chip, u8 *buf,
+                                             int oob_required, int page)
+{
+       struct mtd_info *mtd = nand_to_mtd(chip);
+       int ret;
+
+       /* Select the target */
+       ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
+       if (ret)
+               return ret;
+
+       /* Configure the sequencer */
+       stm32_fmc2_rw_page_init(chip, page, 1, false);
+
+       /* Read the page */
+       ret = stm32_fmc2_xfer(chip, buf, 1, false);
+       if (ret)
+               return ret;
+
+       /* Read oob */
+       if (oob_required)
+               return nand_change_read_column_op(chip, mtd->writesize,
+                                                 chip->oob_poi, mtd->oobsize,
+                                                 false);
+
+       return 0;
+}
+
+static irqreturn_t stm32_fmc2_irq(int irq, void *dev_id)
+{
+       struct stm32_fmc2_nfc *fmc2 = (struct stm32_fmc2_nfc *)dev_id;
+
+       if (fmc2->irq_state == FMC2_IRQ_SEQ)
+               /* Sequencer is used */
+               stm32_fmc2_disable_seq_irq(fmc2);
+       else if (fmc2->irq_state == FMC2_IRQ_BCH)
+               /* BCH is used */
+               stm32_fmc2_disable_bch_irq(fmc2);
+
+       complete(&fmc2->complete);
+
+       return IRQ_HANDLED;
+}
+
+static void stm32_fmc2_read_data(struct nand_chip *chip, void *buf,
+                                unsigned int len, bool force_8bit)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       void __iomem *io_addr_r = fmc2->data_base[fmc2->cs_sel];
+
+       if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+               /* Reconfigure bus width to 8-bit */
+               stm32_fmc2_set_buswidth_16(fmc2, false);
+
+       if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
+               if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
+                       *(u8 *)buf = readb_relaxed(io_addr_r);
+                       buf += sizeof(u8);
+                       len -= sizeof(u8);
+               }
+
+               if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
+                   len >= sizeof(u16)) {
+                       *(u16 *)buf = readw_relaxed(io_addr_r);
+                       buf += sizeof(u16);
+                       len -= sizeof(u16);
+               }
+       }
+
+       /* Buf is aligned */
+       while (len >= sizeof(u32)) {
+               *(u32 *)buf = readl_relaxed(io_addr_r);
+               buf += sizeof(u32);
+               len -= sizeof(u32);
+       }
+
+       /* Read remaining bytes */
+       if (len >= sizeof(u16)) {
+               *(u16 *)buf = readw_relaxed(io_addr_r);
+               buf += sizeof(u16);
+               len -= sizeof(u16);
+       }
+
+       if (len)
+               *(u8 *)buf = readb_relaxed(io_addr_r);
+
+       if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+               /* Reconfigure bus width to 16-bit */
+               stm32_fmc2_set_buswidth_16(fmc2, true);
+}
+
+static void stm32_fmc2_write_data(struct nand_chip *chip, const void *buf,
+                                 unsigned int len, bool force_8bit)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       void __iomem *io_addr_w = fmc2->data_base[fmc2->cs_sel];
+
+       if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+               /* Reconfigure bus width to 8-bit */
+               stm32_fmc2_set_buswidth_16(fmc2, false);
+
+       if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
+               if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
+                       writeb_relaxed(*(u8 *)buf, io_addr_w);
+                       buf += sizeof(u8);
+                       len -= sizeof(u8);
+               }
+
+               if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
+                   len >= sizeof(u16)) {
+                       writew_relaxed(*(u16 *)buf, io_addr_w);
+                       buf += sizeof(u16);
+                       len -= sizeof(u16);
+               }
+       }
+
+       /* Buf is aligned */
+       while (len >= sizeof(u32)) {
+               writel_relaxed(*(u32 *)buf, io_addr_w);
+               buf += sizeof(u32);
+               len -= sizeof(u32);
+       }
+
+       /* Write remaining bytes */
+       if (len >= sizeof(u16)) {
+               writew_relaxed(*(u16 *)buf, io_addr_w);
+               buf += sizeof(u16);
+               len -= sizeof(u16);
+       }
+
+       if (len)
+               writeb_relaxed(*(u8 *)buf, io_addr_w);
+
+       if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+               /* Reconfigure bus width to 16-bit */
+               stm32_fmc2_set_buswidth_16(fmc2, true);
+}
+
+static int stm32_fmc2_exec_op(struct nand_chip *chip,
+                             const struct nand_operation *op,
+                             bool check_only)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       const struct nand_op_instr *instr = NULL;
+       unsigned int op_id, i;
+       int ret;
+
+       ret = stm32_fmc2_select_chip(chip, op->cs);
+       if (ret)
+               return ret;
+
+       if (check_only)
+               return ret;
+
+       for (op_id = 0; op_id < op->ninstrs; op_id++) {
+               instr = &op->instrs[op_id];
+
+               switch (instr->type) {
+               case NAND_OP_CMD_INSTR:
+                       writeb_relaxed(instr->ctx.cmd.opcode,
+                                      fmc2->cmd_base[fmc2->cs_sel]);
+                       break;
+
+               case NAND_OP_ADDR_INSTR:
+                       for (i = 0; i < instr->ctx.addr.naddrs; i++)
+                               writeb_relaxed(instr->ctx.addr.addrs[i],
+                                              fmc2->addr_base[fmc2->cs_sel]);
+                       break;
+
+               case NAND_OP_DATA_IN_INSTR:
+                       stm32_fmc2_read_data(chip, instr->ctx.data.buf.in,
+                                            instr->ctx.data.len,
+                                            instr->ctx.data.force_8bit);
+                       break;
+
+               case NAND_OP_DATA_OUT_INSTR:
+                       stm32_fmc2_write_data(chip, instr->ctx.data.buf.out,
+                                             instr->ctx.data.len,
+                                             instr->ctx.data.force_8bit);
+                       break;
+
+               case NAND_OP_WAITRDY_INSTR:
+                       ret = nand_soft_waitrdy(chip,
+                                               instr->ctx.waitrdy.timeout_ms);
+                       break;
+               }
+       }
+
+       return ret;
+}
+
+/* Controller initialization */
+static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
+{
+       u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
+       u32 bcr1 = readl_relaxed(fmc2->io_base + FMC2_BCR1);
+
+       /* Set CS used to undefined */
+       fmc2->cs_sel = -1;
+
+       /* Enable wait feature and nand flash memory bank */
+       pcr |= FMC2_PCR_PWAITEN;
+       pcr |= FMC2_PCR_PBKEN;
+
+       /* Set buswidth to 8 bits mode for identification */
+       pcr &= ~FMC2_PCR_PWID_MASK;
+
+       /* ECC logic is disabled */
+       pcr &= ~FMC2_PCR_ECCEN;
+
+       /* Default mode */
+       pcr &= ~FMC2_PCR_ECCALG;
+       pcr &= ~FMC2_PCR_BCHECC;
+       pcr &= ~FMC2_PCR_WEN;
+
+       /* Set default ECC sector size */
+       pcr &= ~FMC2_PCR_ECCSS_MASK;
+       pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048);
+
+       /* Set default tclr/tar timings */
+       pcr &= ~FMC2_PCR_TCLR_MASK;
+       pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT);
+       pcr &= ~FMC2_PCR_TAR_MASK;
+       pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT);
+
+       /* Enable FMC2 controller */
+       bcr1 |= FMC2_BCR1_FMC2EN;
+
+       writel_relaxed(bcr1, fmc2->io_base + FMC2_BCR1);
+       writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
+       writel_relaxed(FMC2_PMEM_DEFAULT, fmc2->io_base + FMC2_PMEM);
+       writel_relaxed(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);
+}
+
+/* Controller timings */
+static void stm32_fmc2_calc_timings(struct nand_chip *chip,
+                                   const struct nand_sdr_timings *sdrt)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
+       struct stm32_fmc2_timings *tims = &nand->timings;
+       unsigned long hclk = clk_get_rate(fmc2->clk);
+       unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
+       int tar, tclr, thiz, twait, tset_mem, tset_att, thold_mem, thold_att;
+
+       tar = hclkp;
+       if (tar < sdrt->tAR_min)
+               tar = sdrt->tAR_min;
+       tims->tar = DIV_ROUND_UP(tar, hclkp) - 1;
+       if (tims->tar > FMC2_PCR_TIMING_MASK)
+               tims->tar = FMC2_PCR_TIMING_MASK;
+
+       tclr = hclkp;
+       if (tclr < sdrt->tCLR_min)
+               tclr = sdrt->tCLR_min;
+       tims->tclr = DIV_ROUND_UP(tclr, hclkp) - 1;
+       if (tims->tclr > FMC2_PCR_TIMING_MASK)
+               tims->tclr = FMC2_PCR_TIMING_MASK;
+
+       tims->thiz = FMC2_THIZ;
+       thiz = (tims->thiz + 1) * hclkp;
+
+       /*
+        * tWAIT > tRP
+        * tWAIT > tWP
+        * tWAIT > tREA + tIO
+        */
+       twait = hclkp;
+       if (twait < sdrt->tRP_min)
+               twait = sdrt->tRP_min;
+       if (twait < sdrt->tWP_min)
+               twait = sdrt->tWP_min;
+       if (twait < sdrt->tREA_max + FMC2_TIO)
+               twait = sdrt->tREA_max + FMC2_TIO;
+       tims->twait = DIV_ROUND_UP(twait, hclkp);
+       if (tims->twait == 0)
+               tims->twait = 1;
+       else if (tims->twait > FMC2_PMEM_PATT_TIMING_MASK)
+               tims->twait = FMC2_PMEM_PATT_TIMING_MASK;
+
+       /*
+        * tSETUP_MEM > tCS - tWAIT
+        * tSETUP_MEM > tALS - tWAIT
+        * tSETUP_MEM > tDS - (tWAIT - tHIZ)
+        */
+       tset_mem = hclkp;
+       if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
+               tset_mem = sdrt->tCS_min - twait;
+       if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
+               tset_mem = sdrt->tALS_min - twait;
+       if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
+           (tset_mem < sdrt->tDS_min - (twait - thiz)))
+               tset_mem = sdrt->tDS_min - (twait - thiz);
+       tims->tset_mem = DIV_ROUND_UP(tset_mem, hclkp);
+       if (tims->tset_mem == 0)
+               tims->tset_mem = 1;
+       else if (tims->tset_mem > FMC2_PMEM_PATT_TIMING_MASK)
+               tims->tset_mem = FMC2_PMEM_PATT_TIMING_MASK;
+
+       /*
+        * tHOLD_MEM > tCH
+        * tHOLD_MEM > tREH - tSETUP_MEM
+        * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
+        */
+       thold_mem = hclkp;
+       if (thold_mem < sdrt->tCH_min)
+               thold_mem = sdrt->tCH_min;
+       if (sdrt->tREH_min > tset_mem &&
+           (thold_mem < sdrt->tREH_min - tset_mem))
+               thold_mem = sdrt->tREH_min - tset_mem;
+       if ((sdrt->tRC_min > tset_mem + twait) &&
+           (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
+               thold_mem = sdrt->tRC_min - (tset_mem + twait);
+       if ((sdrt->tWC_min > tset_mem + twait) &&
+           (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
+               thold_mem = sdrt->tWC_min - (tset_mem + twait);
+       tims->thold_mem = DIV_ROUND_UP(thold_mem, hclkp);
+       if (tims->thold_mem == 0)
+               tims->thold_mem = 1;
+       else if (tims->thold_mem > FMC2_PMEM_PATT_TIMING_MASK)
+               tims->thold_mem = FMC2_PMEM_PATT_TIMING_MASK;
+
+       /*
+        * tSETUP_ATT > tCS - tWAIT
+        * tSETUP_ATT > tCLS - tWAIT
+        * tSETUP_ATT > tALS - tWAIT
+        * tSETUP_ATT > tRHW - tHOLD_MEM
+        * tSETUP_ATT > tDS - (tWAIT - tHIZ)
+        */
+       tset_att = hclkp;
+       if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
+               tset_att = sdrt->tCS_min - twait;
+       if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
+               tset_att = sdrt->tCLS_min - twait;
+       if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
+               tset_att = sdrt->tALS_min - twait;
+       if (sdrt->tRHW_min > thold_mem &&
+           (tset_att < sdrt->tRHW_min - thold_mem))
+               tset_att = sdrt->tRHW_min - thold_mem;
+       if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
+           (tset_att < sdrt->tDS_min - (twait - thiz)))
+               tset_att = sdrt->tDS_min - (twait - thiz);
+       tims->tset_att = DIV_ROUND_UP(tset_att, hclkp);
+       if (tims->tset_att == 0)
+               tims->tset_att = 1;
+       else if (tims->tset_att > FMC2_PMEM_PATT_TIMING_MASK)
+               tims->tset_att = FMC2_PMEM_PATT_TIMING_MASK;
+
+       /*
+        * tHOLD_ATT > tALH
+        * tHOLD_ATT > tCH
+        * tHOLD_ATT > tCLH
+        * tHOLD_ATT > tCOH
+        * tHOLD_ATT > tDH
+        * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
+        * tHOLD_ATT > tADL - tSETUP_MEM
+        * tHOLD_ATT > tWH - tSETUP_MEM
+        * tHOLD_ATT > tWHR - tSETUP_MEM
+        * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
+        * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
+        */
+       thold_att = hclkp;
+       if (thold_att < sdrt->tALH_min)
+               thold_att = sdrt->tALH_min;
+       if (thold_att < sdrt->tCH_min)
+               thold_att = sdrt->tCH_min;
+       if (thold_att < sdrt->tCLH_min)
+               thold_att = sdrt->tCLH_min;
+       if (thold_att < sdrt->tCOH_min)
+               thold_att = sdrt->tCOH_min;
+       if (thold_att < sdrt->tDH_min)
+               thold_att = sdrt->tDH_min;
+       if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
+           (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
+               thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
+       if (sdrt->tADL_min > tset_mem &&
+           (thold_att < sdrt->tADL_min - tset_mem))
+               thold_att = sdrt->tADL_min - tset_mem;
+       if (sdrt->tWH_min > tset_mem &&
+           (thold_att < sdrt->tWH_min - tset_mem))
+               thold_att = sdrt->tWH_min - tset_mem;
+       if (sdrt->tWHR_min > tset_mem &&
+           (thold_att < sdrt->tWHR_min - tset_mem))
+               thold_att = sdrt->tWHR_min - tset_mem;
+       if ((sdrt->tRC_min > tset_att + twait) &&
+           (thold_att < sdrt->tRC_min - (tset_att + twait)))
+               thold_att = sdrt->tRC_min - (tset_att + twait);
+       if ((sdrt->tWC_min > tset_att + twait) &&
+           (thold_att < sdrt->tWC_min - (tset_att + twait)))
+               thold_att = sdrt->tWC_min - (tset_att + twait);
+       tims->thold_att = DIV_ROUND_UP(thold_att, hclkp);
+       if (tims->thold_att == 0)
+               tims->thold_att = 1;
+       else if (tims->thold_att > FMC2_PMEM_PATT_TIMING_MASK)
+               tims->thold_att = FMC2_PMEM_PATT_TIMING_MASK;
+}
+
+static int stm32_fmc2_setup_interface(struct nand_chip *chip, int chipnr,
+                                     const struct nand_data_interface *conf)
+{
+       const struct nand_sdr_timings *sdrt;
+
+       sdrt = nand_get_sdr_timings(conf);
+       if (IS_ERR(sdrt))
+               return PTR_ERR(sdrt);
+
+       if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
+               return 0;
+
+       stm32_fmc2_calc_timings(chip, sdrt);
+
+       /* Apply timings */
+       stm32_fmc2_timings_init(chip);
+
+       return 0;
+}
+
+/* DMA configuration */
+static int stm32_fmc2_dma_setup(struct stm32_fmc2_nfc *fmc2)
+{
+       int ret;
+
+       fmc2->dma_tx_ch = dma_request_slave_channel(fmc2->dev, "tx");
+       fmc2->dma_rx_ch = dma_request_slave_channel(fmc2->dev, "rx");
+       fmc2->dma_ecc_ch = dma_request_slave_channel(fmc2->dev, "ecc");
+
+       if (!fmc2->dma_tx_ch || !fmc2->dma_rx_ch || !fmc2->dma_ecc_ch) {
+               dev_warn(fmc2->dev, "DMAs not defined in the device tree, polling mode is used\n");
+               return 0;
+       }
+
+       ret = sg_alloc_table(&fmc2->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL);
+       if (ret)
+               return ret;
+
+       /* Allocate a buffer to store ECC status registers */
+       fmc2->ecc_buf = devm_kzalloc(fmc2->dev, FMC2_MAX_ECC_BUF_LEN,
+                                    GFP_KERNEL);
+       if (!fmc2->ecc_buf)
+               return -ENOMEM;
+
+       ret = sg_alloc_table(&fmc2->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL);
+       if (ret)
+               return ret;
+
+       init_completion(&fmc2->dma_data_complete);
+       init_completion(&fmc2->dma_ecc_complete);
+
+       return 0;
+}
+
+/* NAND callbacks setup */
+static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+
+       /*
+        * Specific callbacks to read/write a page depending on
+        * the mode (polling/sequencer) and the algo used (Hamming, BCH).
+        */
+       if (fmc2->dma_tx_ch && fmc2->dma_rx_ch && fmc2->dma_ecc_ch) {
+               /* DMA => use sequencer mode callbacks */
+               chip->ecc.correct = stm32_fmc2_sequencer_correct;
+               chip->ecc.write_page = stm32_fmc2_sequencer_write_page;
+               chip->ecc.read_page = stm32_fmc2_sequencer_read_page;
+               chip->ecc.write_page_raw = stm32_fmc2_sequencer_write_page_raw;
+               chip->ecc.read_page_raw = stm32_fmc2_sequencer_read_page_raw;
+       } else {
+               /* No DMA => use polling mode callbacks */
+               chip->ecc.hwctl = stm32_fmc2_hwctl;
+               if (chip->ecc.strength == FMC2_ECC_HAM) {
+                       /* Hamming is used */
+                       chip->ecc.calculate = stm32_fmc2_ham_calculate;
+                       chip->ecc.correct = stm32_fmc2_ham_correct;
+                       chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
+               } else {
+                       /* BCH is used */
+                       chip->ecc.calculate = stm32_fmc2_bch_calculate;
+                       chip->ecc.correct = stm32_fmc2_bch_correct;
+                       chip->ecc.read_page = stm32_fmc2_read_page;
+               }
+       }
+
+       /* Specific configurations depending on the algo used */
+       if (chip->ecc.strength == FMC2_ECC_HAM)
+               chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
+       else if (chip->ecc.strength == FMC2_ECC_BCH8)
+               chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
+       else
+               chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
+}
+
+/* FMC2 layout */
+static int stm32_fmc2_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
+                                        struct mtd_oob_region *oobregion)
+{
+       struct nand_chip *chip = mtd_to_nand(mtd);
+       struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+       if (section)
+               return -ERANGE;
+
+       oobregion->length = ecc->total;
+       oobregion->offset = FMC2_BBM_LEN;
+
+       return 0;
+}
+
+static int stm32_fmc2_nand_ooblayout_free(struct mtd_info *mtd, int section,
+                                         struct mtd_oob_region *oobregion)
+{
+       struct nand_chip *chip = mtd_to_nand(mtd);
+       struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+       if (section)
+               return -ERANGE;
+
+       oobregion->length = mtd->oobsize - ecc->total - FMC2_BBM_LEN;
+       oobregion->offset = ecc->total + FMC2_BBM_LEN;
+
+       return 0;
+}
+
+static const struct mtd_ooblayout_ops stm32_fmc2_nand_ooblayout_ops = {
+       .ecc = stm32_fmc2_nand_ooblayout_ecc,
+       .free = stm32_fmc2_nand_ooblayout_free,
+};
+
+/* FMC2 caps */
+static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)
+{
+       /* Hamming */
+       if (strength == FMC2_ECC_HAM)
+               return 4;
+
+       /* BCH8 */
+       if (strength == FMC2_ECC_BCH8)
+               return 14;
+
+       /* BCH4 */
+       return 8;
+}
+
+NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes,
+                    FMC2_ECC_STEP_SIZE,
+                    FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
+
+/* FMC2 controller ops */
+static int stm32_fmc2_attach_chip(struct nand_chip *chip)
+{
+       struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+       struct mtd_info *mtd = nand_to_mtd(chip);
+       int ret;
+
+       /*
+        * Only NAND_ECC_HW mode is actually supported
+        * Hamming => ecc.strength = 1
+        * BCH4 => ecc.strength = 4
+        * BCH8 => ecc.strength = 8
+        * ECC sector size = 512
+        */
+       if (chip->ecc.mode != NAND_ECC_HW) {
+               dev_err(fmc2->dev, "nand_ecc_mode is not well defined in the DT\n");
+               return -EINVAL;
+       }
+
+       ret = nand_ecc_choose_conf(chip, &stm32_fmc2_ecc_caps,
+                                  mtd->oobsize - FMC2_BBM_LEN);
+       if (ret) {
+               dev_err(fmc2->dev, "no valid ECC settings set\n");
+               return ret;
+       }
+
+       if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) {
+               dev_err(fmc2->dev, "nand page size is not supported\n");
+               return -EINVAL;
+       }
+
+       if (chip->bbt_options & NAND_BBT_USE_FLASH)
+               chip->bbt_options |= NAND_BBT_NO_OOB;
+
+       /* NAND callbacks setup */
+       stm32_fmc2_nand_callbacks_setup(chip);
+
+       /* Define ECC layout */
+       mtd_set_ooblayout(mtd, &stm32_fmc2_nand_ooblayout_ops);
+
+       /* Configure bus width to 16-bit */
+       if (chip->options & NAND_BUSWIDTH_16)
+               stm32_fmc2_set_buswidth_16(fmc2, true);
+
+       return 0;
+}
+
+static const struct nand_controller_ops stm32_fmc2_nand_controller_ops = {
+       .attach_chip = stm32_fmc2_attach_chip,
+       .exec_op = stm32_fmc2_exec_op,
+       .setup_data_interface = stm32_fmc2_setup_interface,
+};
+
+/* FMC2 probe */
+static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
+                                 struct device_node *dn)
+{
+       struct stm32_fmc2_nand *nand = &fmc2->nand;
+       u32 cs;
+       int ret, i;
+
+       if (!of_get_property(dn, "reg", &nand->ncs))
+               return -EINVAL;
+
+       nand->ncs /= sizeof(u32);
+       if (!nand->ncs) {
+               dev_err(fmc2->dev, "invalid reg property size\n");
+               return -EINVAL;
+       }
+
+       for (i = 0; i < nand->ncs; i++) {
+               ret = of_property_read_u32_index(dn, "reg", i, &cs);
+               if (ret) {
+                       dev_err(fmc2->dev, "could not retrieve reg property: %d\n",
+                               ret);
+                       return ret;
+               }
+
+               if (cs > FMC2_MAX_CE) {
+                       dev_err(fmc2->dev, "invalid reg value: %d\n", cs);
+                       return -EINVAL;
+               }
+
+               if (fmc2->cs_assigned & BIT(cs)) {
+                       dev_err(fmc2->dev, "cs already assigned: %d\n", cs);
+                       return -EINVAL;
+               }
+
+               fmc2->cs_assigned |= BIT(cs);
+               nand->cs_used[i] = cs;
+       }
+
+       nand_set_flash_node(&nand->chip, dn);
+
+       return 0;
+}
+
+static int stm32_fmc2_parse_dt(struct stm32_fmc2_nfc *fmc2)
+{
+       struct device_node *dn = fmc2->dev->of_node;
+       struct device_node *child;
+       int nchips = of_get_child_count(dn);
+       int ret = 0;
+
+       if (!nchips) {
+               dev_err(fmc2->dev, "NAND chip not defined\n");
+               return -EINVAL;
+       }
+
+       if (nchips > 1) {
+               dev_err(fmc2->dev, "too many NAND chips defined\n");
+               return -EINVAL;
+       }
+
+       for_each_child_of_node(dn, child) {
+               ret = stm32_fmc2_parse_child(fmc2, child);
+               if (ret < 0) {
+                       of_node_put(child);
+                       return ret;
+               }
+       }
+
+       return ret;
+}
+
+static int stm32_fmc2_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       struct reset_control *rstc;
+       struct stm32_fmc2_nfc *fmc2;
+       struct stm32_fmc2_nand *nand;
+       struct resource *res;
+       struct mtd_info *mtd;
+       struct nand_chip *chip;
+       int chip_cs, mem_region, ret, irq;
+
+       fmc2 = devm_kzalloc(dev, sizeof(*fmc2), GFP_KERNEL);
+       if (!fmc2)
+               return -ENOMEM;
+
+       fmc2->dev = dev;
+       nand_controller_init(&fmc2->base);
+       fmc2->base.ops = &stm32_fmc2_nand_controller_ops;
+
+       ret = stm32_fmc2_parse_dt(fmc2);
+       if (ret)
+               return ret;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       fmc2->io_base = devm_ioremap_resource(dev, res);
+       if (IS_ERR(fmc2->io_base))
+               return PTR_ERR(fmc2->io_base);
+
+       fmc2->io_phys_addr = res->start;
+
+       for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE;
+            chip_cs++, mem_region += 3) {
+               if (!(fmc2->cs_assigned & BIT(chip_cs)))
+                       continue;
+
+               res = platform_get_resource(pdev, IORESOURCE_MEM, mem_region);
+               fmc2->data_base[chip_cs] = devm_ioremap_resource(dev, res);
+               if (IS_ERR(fmc2->data_base[chip_cs]))
+                       return PTR_ERR(fmc2->data_base[chip_cs]);
+
+               fmc2->data_phys_addr[chip_cs] = res->start;
+
+               res = platform_get_resource(pdev, IORESOURCE_MEM,
+                                           mem_region + 1);
+               fmc2->cmd_base[chip_cs] = devm_ioremap_resource(dev, res);
+               if (IS_ERR(fmc2->cmd_base[chip_cs]))
+                       return PTR_ERR(fmc2->cmd_base[chip_cs]);
+
+               res = platform_get_resource(pdev, IORESOURCE_MEM,
+                                           mem_region + 2);
+               fmc2->addr_base[chip_cs] = devm_ioremap_resource(dev, res);
+               if (IS_ERR(fmc2->addr_base[chip_cs]))
+                       return PTR_ERR(fmc2->addr_base[chip_cs]);
+       }
+
+       irq = platform_get_irq(pdev, 0);
+       ret = devm_request_irq(dev, irq, stm32_fmc2_irq, 0,
+                              dev_name(dev), fmc2);
+       if (ret) {
+               dev_err(dev, "failed to request irq\n");
+               return ret;
+       }
+
+       init_completion(&fmc2->complete);
+
+       fmc2->clk = devm_clk_get(dev, NULL);
+       if (IS_ERR(fmc2->clk))
+               return PTR_ERR(fmc2->clk);
+
+       ret = clk_prepare_enable(fmc2->clk);
+       if (ret) {
+               dev_err(dev, "can not enable the clock\n");
+               return ret;
+       }
+
+       rstc = devm_reset_control_get(dev, NULL);
+       if (!IS_ERR(rstc)) {
+               reset_control_assert(rstc);
+               reset_control_deassert(rstc);
+       }
+
+       /* DMA setup */
+       ret = stm32_fmc2_dma_setup(fmc2);
+       if (ret)
+               return ret;
+
+       /* FMC2 init routine */
+       stm32_fmc2_init(fmc2);
+
+       nand = &fmc2->nand;
+       chip = &nand->chip;
+       mtd = nand_to_mtd(chip);
+       mtd->dev.parent = dev;
+
+       chip->controller = &fmc2->base;
+       chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
+                        NAND_USE_BOUNCE_BUFFER;
+
+       /* Default ECC settings */
+       chip->ecc.mode = NAND_ECC_HW;
+       chip->ecc.size = FMC2_ECC_STEP_SIZE;
+       chip->ecc.strength = FMC2_ECC_BCH8;
+
+       /* Scan to find existence of the device */
+       ret = nand_scan(chip, nand->ncs);
+       if (ret)
+               goto err_scan;
+
+       ret = mtd_device_register(mtd, NULL, 0);
+       if (ret)
+               goto err_device_register;
+
+       platform_set_drvdata(pdev, fmc2);
+
+       return 0;
+
+err_device_register:
+       nand_cleanup(chip);
+
+err_scan:
+       if (fmc2->dma_ecc_ch)
+               dma_release_channel(fmc2->dma_ecc_ch);
+       if (fmc2->dma_tx_ch)
+               dma_release_channel(fmc2->dma_tx_ch);
+       if (fmc2->dma_rx_ch)
+               dma_release_channel(fmc2->dma_rx_ch);
+
+       sg_free_table(&fmc2->dma_data_sg);
+       sg_free_table(&fmc2->dma_ecc_sg);
+
+       clk_disable_unprepare(fmc2->clk);
+
+       return ret;
+}
+
+static int stm32_fmc2_remove(struct platform_device *pdev)
+{
+       struct stm32_fmc2_nfc *fmc2 = platform_get_drvdata(pdev);
+       struct stm32_fmc2_nand *nand = &fmc2->nand;
+
+       nand_release(&nand->chip);
+
+       if (fmc2->dma_ecc_ch)
+               dma_release_channel(fmc2->dma_ecc_ch);
+       if (fmc2->dma_tx_ch)
+               dma_release_channel(fmc2->dma_tx_ch);
+       if (fmc2->dma_rx_ch)
+               dma_release_channel(fmc2->dma_rx_ch);
+
+       sg_free_table(&fmc2->dma_data_sg);
+       sg_free_table(&fmc2->dma_ecc_sg);
+
+       clk_disable_unprepare(fmc2->clk);
+
+       return 0;
+}
+
+static int __maybe_unused stm32_fmc2_suspend(struct device *dev)
+{
+       struct stm32_fmc2_nfc *fmc2 = dev_get_drvdata(dev);
+
+       clk_disable_unprepare(fmc2->clk);
+
+       pinctrl_pm_select_sleep_state(dev);
+
+       return 0;
+}
+
+static int __maybe_unused stm32_fmc2_resume(struct device *dev)
+{
+       struct stm32_fmc2_nfc *fmc2 = dev_get_drvdata(dev);
+       struct stm32_fmc2_nand *nand = &fmc2->nand;
+       int chip_cs, ret;
+
+       pinctrl_pm_select_default_state(dev);
+
+       ret = clk_prepare_enable(fmc2->clk);
+       if (ret) {
+               dev_err(dev, "can not enable the clock\n");
+               return ret;
+       }
+
+       stm32_fmc2_init(fmc2);
+
+       for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) {
+               if (!(fmc2->cs_assigned & BIT(chip_cs)))
+                       continue;
+
+               nand_reset(&nand->chip, chip_cs);
+       }
+
+       return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(stm32_fmc2_pm_ops, stm32_fmc2_suspend,
+                        stm32_fmc2_resume);
+
+static const struct of_device_id stm32_fmc2_match[] = {
+       {.compatible = "st,stm32mp15-fmc2"},
+       {}
+};
+MODULE_DEVICE_TABLE(of, stm32_fmc2_match);
+
+static struct platform_driver stm32_fmc2_driver = {
+       .probe  = stm32_fmc2_probe,
+       .remove = stm32_fmc2_remove,
+       .driver = {
+               .name = "stm32_fmc2_nand",
+               .of_match_table = stm32_fmc2_match,
+               .pm = &stm32_fmc2_pm_ops,
+       },
+};
+module_platform_driver(stm32_fmc2_driver);
+
+MODULE_ALIAS("platform:stm32_fmc2_nand");
+MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 nand driver");
+MODULE_LICENSE("GPL v2");
index e828ee50a201885632f015b81e98b5b21d66f937..4282bc47776177cc95dfa7bed5805b403c352688 100644 (file)
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
  *
  *
  *     Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
  *     Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <linux/dma-mapping.h>
 
 #define NFC_MAX_CS             7
 
-/*
- * Chip Select structure: stores information related to NAND Chip Select
+/**
+ * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
  *
- * @cs:                the NAND CS id used to communicate with a NAND Chip
- * @rb:                the Ready/Busy pin ID. -1 means no R/B pin connected to the
- *             NFC
+ * @cs: the NAND CS id used to communicate with a NAND Chip
+ * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
  */
 struct sunxi_nand_chip_sel {
        u8 cs;
        s8 rb;
 };
 
-/*
- * sunxi HW ECC infos: stores information related to HW ECC support
+/**
+ * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
  *
- * @mode:      the sunxi ECC mode field deduced from ECC requirements
+ * @mode: the sunxi ECC mode field deduced from ECC requirements
  */
 struct sunxi_nand_hw_ecc {
        int mode;
 };
 
-/*
- * NAND chip structure: stores NAND chip device related information
+/**
+ * struct sunxi_nand_chip - stores NAND chip device related information
  *
- * @node:              used to store NAND chips into a list
- * @nand:              base NAND chip structure
- * @mtd:               base MTD structure
- * @clk_rate:          clk_rate required for this NAND chip
- * @timing_cfg         TIMING_CFG register value for this NAND chip
- * @selected:          current active CS
- * @nsels:             number of CS lines required by the NAND chip
- * @sels:              array of CS lines descriptions
+ * @node: used to store NAND chips into a list
+ * @nand: base NAND chip structure
+ * @clk_rate: clk_rate required for this NAND chip
+ * @timing_cfg: TIMING_CFG register value for this NAND chip
+ * @timing_ctl: TIMING_CTL register value for this NAND chip
+ * @nsels: number of CS lines required by the NAND chip
+ * @sels: array of CS lines descriptions
  */
 struct sunxi_nand_chip {
        struct list_head node;
@@ -202,11 +191,6 @@ struct sunxi_nand_chip {
        unsigned long clk_rate;
        u32 timing_cfg;
        u32 timing_ctl;
-       int selected;
-       int addr_cycles;
-       u32 addr[2];
-       int cmd_cycles;
-       u8 cmd[2];
        int nsels;
        struct sunxi_nand_chip_sel sels[0];
 };
@@ -216,20 +200,21 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
        return container_of(nand, struct sunxi_nand_chip, nand);
 }
 
-/*
- * NAND Controller structure: stores sunxi NAND controller information
+/**
+ * struct sunxi_nfc - stores sunxi NAND controller information
  *
- * @controller:                base controller structure
- * @dev:               parent device (used to print error messages)
- * @regs:              NAND controller registers
- * @ahb_clk:           NAND Controller AHB clock
- * @mod_clk:           NAND Controller mod clock
- * @assigned_cs:       bitmask describing already assigned CS lines
- * @clk_rate:          NAND controller current clock rate
- * @chips:             a list containing all the NAND chips attached to
- *                     this NAND controller
- * @complete:          a completion object used to wait for NAND
- *                     controller events
+ * @controller: base controller structure
+ * @dev: parent device (used to print error messages)
+ * @regs: NAND controller registers
+ * @ahb_clk: NAND controller AHB clock
+ * @mod_clk: NAND controller mod clock
+ * @reset: NAND controller reset line
+ * @assigned_cs: bitmask describing already assigned CS lines
+ * @clk_rate: NAND controller current clock rate
+ * @chips: a list containing all the NAND chips attached to this NAND
+ *        controller
+ * @complete: a completion object used to wait for NAND controller events
+ * @dmac: the DMA channel attached to the NAND controller
  */
 struct sunxi_nfc {
        struct nand_controller controller;
@@ -339,13 +324,11 @@ static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
        return ret;
 }
 
-static int sunxi_nfc_dma_op_prepare(struct mtd_info *mtd, const void *buf,
+static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
                                    int chunksize, int nchunks,
                                    enum dma_data_direction ddir,
                                    struct scatterlist *sg)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
        struct dma_async_tx_descriptor *dmad;
        enum dma_transfer_direction tdir;
        dma_cookie_t dmat;
@@ -388,38 +371,16 @@ err_unmap_buf:
        return ret;
 }
 
-static void sunxi_nfc_dma_op_cleanup(struct mtd_info *mtd,
+static void sunxi_nfc_dma_op_cleanup(struct sunxi_nfc *nfc,
                                     enum dma_data_direction ddir,
                                     struct scatterlist *sg)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
-
        dma_unmap_sg(nfc->dev, sg, 1, ddir);
        writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
               nfc->regs + NFC_REG_CTL);
 }
 
-static int sunxi_nfc_dev_ready(struct nand_chip *nand)
-{
-       struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
-       struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
-       u32 mask;
-
-       if (sunxi_nand->selected < 0)
-               return 0;
-
-       if (sunxi_nand->sels[sunxi_nand->selected].rb < 0) {
-               dev_err(nfc->dev, "cannot check R/B NAND status!\n");
-               return 0;
-       }
-
-       mask = NFC_RB_STATE(sunxi_nand->sels[sunxi_nand->selected].rb);
-
-       return !!(readl(nfc->regs + NFC_REG_ST) & mask);
-}
-
-static void sunxi_nfc_select_chip(struct nand_chip *nand, int chip)
+static void sunxi_nfc_select_chip(struct nand_chip *nand, unsigned int cs)
 {
        struct mtd_info *mtd = nand_to_mtd(nand);
        struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
@@ -427,40 +388,27 @@ static void sunxi_nfc_select_chip(struct nand_chip *nand, int chip)
        struct sunxi_nand_chip_sel *sel;
        u32 ctl;
 
-       if (chip > 0 && chip >= sunxi_nand->nsels)
-               return;
-
-       if (chip == sunxi_nand->selected)
+       if (cs > 0 && cs >= sunxi_nand->nsels)
                return;
 
        ctl = readl(nfc->regs + NFC_REG_CTL) &
              ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
 
-       if (chip >= 0) {
-               sel = &sunxi_nand->sels[chip];
+       sel = &sunxi_nand->sels[cs];
+       ctl |= NFC_CE_SEL(sel->cs) | NFC_EN | NFC_PAGE_SHIFT(nand->page_shift);
+       if (sel->rb >= 0)
+               ctl |= NFC_RB_SEL(sel->rb);
 
-               ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
-                      NFC_PAGE_SHIFT(nand->page_shift);
-               if (sel->rb < 0) {
-                       nand->legacy.dev_ready = NULL;
-               } else {
-                       nand->legacy.dev_ready = sunxi_nfc_dev_ready;
-                       ctl |= NFC_RB_SEL(sel->rb);
-               }
-
-               writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
+       writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
 
-               if (nfc->clk_rate != sunxi_nand->clk_rate) {
-                       clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
-                       nfc->clk_rate = sunxi_nand->clk_rate;
-               }
+       if (nfc->clk_rate != sunxi_nand->clk_rate) {
+               clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
+               nfc->clk_rate = sunxi_nand->clk_rate;
        }
 
        writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
        writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
        writel(ctl, nfc->regs + NFC_REG_CTL);
-
-       sunxi_nand->selected = chip;
 }
 
 static void sunxi_nfc_read_buf(struct nand_chip *nand, uint8_t *buf, int len)
@@ -537,71 +485,6 @@ static void sunxi_nfc_write_buf(struct nand_chip *nand, const uint8_t *buf,
        }
 }
 
-static uint8_t sunxi_nfc_read_byte(struct nand_chip *nand)
-{
-       uint8_t ret = 0;
-
-       sunxi_nfc_read_buf(nand, &ret, 1);
-
-       return ret;
-}
-
-static void sunxi_nfc_cmd_ctrl(struct nand_chip *nand, int dat,
-                              unsigned int ctrl)
-{
-       struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
-       struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
-       int ret;
-
-       if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
-           !(ctrl & (NAND_CLE | NAND_ALE))) {
-               u32 cmd = 0;
-
-               if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
-                       return;
-
-               if (sunxi_nand->cmd_cycles--)
-                       cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
-
-               if (sunxi_nand->cmd_cycles--) {
-                       cmd |= NFC_SEND_CMD2;
-                       writel(sunxi_nand->cmd[1],
-                              nfc->regs + NFC_REG_RCMD_SET);
-               }
-
-               sunxi_nand->cmd_cycles = 0;
-
-               if (sunxi_nand->addr_cycles) {
-                       cmd |= NFC_SEND_ADR |
-                              NFC_ADR_NUM(sunxi_nand->addr_cycles);
-                       writel(sunxi_nand->addr[0],
-                              nfc->regs + NFC_REG_ADDR_LOW);
-               }
-
-               if (sunxi_nand->addr_cycles > 4)
-                       writel(sunxi_nand->addr[1],
-                              nfc->regs + NFC_REG_ADDR_HIGH);
-
-               ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
-               if (ret)
-                       return;
-
-               writel(cmd, nfc->regs + NFC_REG_CMD);
-               sunxi_nand->addr[0] = 0;
-               sunxi_nand->addr[1] = 0;
-               sunxi_nand->addr_cycles = 0;
-               sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
-       }
-
-       if (ctrl & NAND_CLE) {
-               sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
-       } else if (ctrl & NAND_ALE) {
-               sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
-                               dat << ((sunxi_nand->addr_cycles % 4) * 8);
-               sunxi_nand->addr_cycles++;
-       }
-}
-
 /* These seed values have been extracted from Allwinner's BSP */
 static const u16 sunxi_nfc_randomizer_page_seeds[] = {
        0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
@@ -684,8 +567,10 @@ static u16 sunxi_nfc_randomizer_step(u16 state, int count)
        return state;
 }
 
-static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
+static u16 sunxi_nfc_randomizer_state(struct nand_chip *nand, int page,
+                                     bool ecc)
 {
+       struct mtd_info *mtd = nand_to_mtd(nand);
        const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
        int mod = mtd_div_by_ws(mtd->erasesize, mtd);
 
@@ -702,10 +587,9 @@ static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
        return seeds[page % mod];
 }
 
-static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
-                                       int page, bool ecc)
+static void sunxi_nfc_randomizer_config(struct nand_chip *nand, int page,
+                                       bool ecc)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
        u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
        u16 state;
@@ -714,14 +598,13 @@ static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
                return;
 
        ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
-       state = sunxi_nfc_randomizer_state(mtd, page, ecc);
+       state = sunxi_nfc_randomizer_state(nand, page, ecc);
        ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
        writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
 }
 
-static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
+static void sunxi_nfc_randomizer_enable(struct nand_chip *nand)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 
        if (!(nand->options & NAND_NEED_SCRAMBLING))
@@ -731,9 +614,8 @@ static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
               nfc->regs + NFC_REG_ECC_CTL);
 }
 
-static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
+static void sunxi_nfc_randomizer_disable(struct nand_chip *nand)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 
        if (!(nand->options & NAND_NEED_SCRAMBLING))
@@ -743,36 +625,35 @@ static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
               nfc->regs + NFC_REG_ECC_CTL);
 }
 
-static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
+static void sunxi_nfc_randomize_bbm(struct nand_chip *nand, int page, u8 *bbm)
 {
-       u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
+       u16 state = sunxi_nfc_randomizer_state(nand, page, true);
 
        bbm[0] ^= state;
        bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
 }
 
-static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
+static void sunxi_nfc_randomizer_write_buf(struct nand_chip *nand,
                                           const uint8_t *buf, int len,
                                           bool ecc, int page)
 {
-       sunxi_nfc_randomizer_config(mtd, page, ecc);
-       sunxi_nfc_randomizer_enable(mtd);
-       sunxi_nfc_write_buf(mtd_to_nand(mtd), buf, len);
-       sunxi_nfc_randomizer_disable(mtd);
+       sunxi_nfc_randomizer_config(nand, page, ecc);
+       sunxi_nfc_randomizer_enable(nand);
+       sunxi_nfc_write_buf(nand, buf, len);
+       sunxi_nfc_randomizer_disable(nand);
 }
 
-static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
+static void sunxi_nfc_randomizer_read_buf(struct nand_chip *nand, uint8_t *buf,
                                          int len, bool ecc, int page)
 {
-       sunxi_nfc_randomizer_config(mtd, page, ecc);
-       sunxi_nfc_randomizer_enable(mtd);
-       sunxi_nfc_read_buf(mtd_to_nand(mtd), buf, len);
-       sunxi_nfc_randomizer_disable(mtd);
+       sunxi_nfc_randomizer_config(nand, page, ecc);
+       sunxi_nfc_randomizer_enable(nand);
+       sunxi_nfc_read_buf(nand, buf, len);
+       sunxi_nfc_randomizer_disable(nand);
 }
 
-static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
+static void sunxi_nfc_hw_ecc_enable(struct nand_chip *nand)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
        struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
        u32 ecc_ctl;
@@ -789,9 +670,8 @@ static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
        writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
 }
 
-static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
+static void sunxi_nfc_hw_ecc_disable(struct nand_chip *nand)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 
        writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
@@ -811,10 +691,9 @@ static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
        return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
 }
 
-static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct mtd_info *mtd, u8 *oob,
+static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct nand_chip *nand, u8 *oob,
                                                int step, bool bbm, int page)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 
        sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)),
@@ -822,21 +701,20 @@ static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct mtd_info *mtd, u8 *oob,
 
        /* De-randomize the Bad Block Marker. */
        if (bbm && (nand->options & NAND_NEED_SCRAMBLING))
-               sunxi_nfc_randomize_bbm(mtd, page, oob);
+               sunxi_nfc_randomize_bbm(nand, page, oob);
 }
 
-static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct mtd_info *mtd,
+static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip *nand,
                                                const u8 *oob, int step,
                                                bool bbm, int page)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
        u8 user_data[4];
 
        /* Randomize the Bad Block Marker. */
        if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) {
                memcpy(user_data, oob, sizeof(user_data));
-               sunxi_nfc_randomize_bbm(mtd, page, user_data);
+               sunxi_nfc_randomize_bbm(nand, page, user_data);
                oob = user_data;
        }
 
@@ -844,9 +722,11 @@ static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct mtd_info *mtd,
               nfc->regs + NFC_REG_USER_DATA(step));
 }
 
-static void sunxi_nfc_hw_ecc_update_stats(struct mtd_info *mtd,
+static void sunxi_nfc_hw_ecc_update_stats(struct nand_chip *nand,
                                          unsigned int *max_bitflips, int ret)
 {
+       struct mtd_info *mtd = nand_to_mtd(nand);
+
        if (ret < 0) {
                mtd->ecc_stats.failed++;
        } else {
@@ -855,10 +735,9 @@ static void sunxi_nfc_hw_ecc_update_stats(struct mtd_info *mtd,
        }
 }
 
-static int sunxi_nfc_hw_ecc_correct(struct mtd_info *mtd, u8 *data, u8 *oob,
+static int sunxi_nfc_hw_ecc_correct(struct nand_chip *nand, u8 *data, u8 *oob,
                                    int step, u32 status, bool *erased)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
        struct nand_ecc_ctrl *ecc = &nand->ecc;
        u32 tmp;
@@ -892,14 +771,13 @@ static int sunxi_nfc_hw_ecc_correct(struct mtd_info *mtd, u8 *data, u8 *oob,
        return NFC_ECC_ERR_CNT(step, tmp);
 }
 
-static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
+static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip *nand,
                                       u8 *data, int data_off,
                                       u8 *oob, int oob_off,
                                       int *cur_off,
                                       unsigned int *max_bitflips,
                                       bool bbm, bool oob_required, int page)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
        struct nand_ecc_ctrl *ecc = &nand->ecc;
        int raw_mode = 0;
@@ -909,7 +787,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
        if (*cur_off != data_off)
                nand_change_read_column_op(nand, data_off, NULL, 0, false);
 
-       sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
+       sunxi_nfc_randomizer_read_buf(nand, NULL, ecc->size, false, page);
 
        if (data_off + ecc->size != oob_off)
                nand_change_read_column_op(nand, oob_off, NULL, 0, false);
@@ -918,18 +796,18 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
        if (ret)
                return ret;
 
-       sunxi_nfc_randomizer_enable(mtd);
+       sunxi_nfc_randomizer_enable(nand);
        writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
               nfc->regs + NFC_REG_CMD);
 
        ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
-       sunxi_nfc_randomizer_disable(mtd);
+       sunxi_nfc_randomizer_disable(nand);
        if (ret)
                return ret;
 
        *cur_off = oob_off + ecc->bytes + 4;
 
-       ret = sunxi_nfc_hw_ecc_correct(mtd, data, oob_required ? oob : NULL, 0,
+       ret = sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0,
                                       readl(nfc->regs + NFC_REG_ECC_ST),
                                       &erased);
        if (erased)
@@ -961,24 +839,24 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
                if (oob_required) {
                        nand_change_read_column_op(nand, oob_off, NULL, 0,
                                                   false);
-                       sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4,
+                       sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + 4,
                                                      true, page);
 
-                       sunxi_nfc_hw_ecc_get_prot_oob_bytes(mtd, oob, 0,
+                       sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, 0,
                                                            bbm, page);
                }
        }
 
-       sunxi_nfc_hw_ecc_update_stats(mtd, max_bitflips, ret);
+       sunxi_nfc_hw_ecc_update_stats(nand, max_bitflips, ret);
 
        return raw_mode;
 }
 
-static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
+static void sunxi_nfc_hw_ecc_read_extra_oob(struct nand_chip *nand,
                                            u8 *oob, int *cur_off,
                                            bool randomize, int page)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(nand);
        struct nand_ecc_ctrl *ecc = &nand->ecc;
        int offset = ((ecc->bytes + 4) * ecc->steps);
        int len = mtd->oobsize - offset;
@@ -993,20 +871,20 @@ static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
        if (!randomize)
                sunxi_nfc_read_buf(nand, oob + offset, len);
        else
-               sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
+               sunxi_nfc_randomizer_read_buf(nand, oob + offset, len,
                                              false, page);
 
        if (cur_off)
                *cur_off = mtd->oobsize + mtd->writesize;
 }
 
-static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
+static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand_chip *nand, uint8_t *buf,
                                            int oob_required, int page,
                                            int nchunks)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        bool randomized = nand->options & NAND_NEED_SCRAMBLING;
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
+       struct mtd_info *mtd = nand_to_mtd(nand);
        struct nand_ecc_ctrl *ecc = &nand->ecc;
        unsigned int max_bitflips = 0;
        int ret, i, raw_mode = 0;
@@ -1017,14 +895,14 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
        if (ret)
                return ret;
 
-       ret = sunxi_nfc_dma_op_prepare(mtd, buf, ecc->size, nchunks,
+       ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, nchunks,
                                       DMA_FROM_DEVICE, &sg);
        if (ret)
                return ret;
 
-       sunxi_nfc_hw_ecc_enable(mtd);
-       sunxi_nfc_randomizer_config(mtd, page, false);
-       sunxi_nfc_randomizer_enable(mtd);
+       sunxi_nfc_hw_ecc_enable(nand);
+       sunxi_nfc_randomizer_config(nand, page, false);
+       sunxi_nfc_randomizer_enable(nand);
 
        writel((NAND_CMD_RNDOUTSTART << 16) | (NAND_CMD_RNDOUT << 8) |
               NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET);
@@ -1038,10 +916,10 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
        if (ret)
                dmaengine_terminate_all(nfc->dmac);
 
-       sunxi_nfc_randomizer_disable(mtd);
-       sunxi_nfc_hw_ecc_disable(mtd);
+       sunxi_nfc_randomizer_disable(nand);
+       sunxi_nfc_hw_ecc_disable(nand);
 
-       sunxi_nfc_dma_op_cleanup(mtd, DMA_FROM_DEVICE, &sg);
+       sunxi_nfc_dma_op_cleanup(nfc, DMA_FROM_DEVICE, &sg);
 
        if (ret)
                return ret;
@@ -1055,7 +933,7 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
                u8 *oob = nand->oob_poi + oob_off;
                bool erased;
 
-               ret = sunxi_nfc_hw_ecc_correct(mtd, randomized ? data : NULL,
+               ret = sunxi_nfc_hw_ecc_correct(nand, randomized ? data : NULL,
                                               oob_required ? oob : NULL,
                                               i, status, &erased);
 
@@ -1069,14 +947,14 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
                                                   mtd->writesize + oob_off,
                                                   oob, ecc->bytes + 4, false);
 
-                       sunxi_nfc_hw_ecc_get_prot_oob_bytes(mtd, oob, i,
+                       sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, i,
                                                            !i, page);
                }
 
                if (erased)
                        raw_mode = 1;
 
-               sunxi_nfc_hw_ecc_update_stats(mtd, &max_bitflips, ret);
+               sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret);
        }
 
        if (status & NFC_ECC_ERR_MSK) {
@@ -1111,25 +989,24 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
                        if (ret >= 0)
                                raw_mode = 1;
 
-                       sunxi_nfc_hw_ecc_update_stats(mtd, &max_bitflips, ret);
+                       sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret);
                }
        }
 
        if (oob_required)
-               sunxi_nfc_hw_ecc_read_extra_oob(mtd, nand->oob_poi,
+               sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi,
                                                NULL, !raw_mode,
                                                page);
 
        return max_bitflips;
 }
 
-static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
+static int sunxi_nfc_hw_ecc_write_chunk(struct nand_chip *nand,
                                        const u8 *data, int data_off,
                                        const u8 *oob, int oob_off,
                                        int *cur_off, bool bbm,
                                        int page)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
        struct nand_ecc_ctrl *ecc = &nand->ecc;
        int ret;
@@ -1137,7 +1014,7 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
        if (data_off != *cur_off)
                nand_change_write_column_op(nand, data_off, NULL, 0, false);
 
-       sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
+       sunxi_nfc_randomizer_write_buf(nand, data, ecc->size, false, page);
 
        if (data_off + ecc->size != oob_off)
                nand_change_write_column_op(nand, oob_off, NULL, 0, false);
@@ -1146,15 +1023,15 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
        if (ret)
                return ret;
 
-       sunxi_nfc_randomizer_enable(mtd);
-       sunxi_nfc_hw_ecc_set_prot_oob_bytes(mtd, oob, 0, bbm, page);
+       sunxi_nfc_randomizer_enable(nand);
+       sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page);
 
        writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
               NFC_ACCESS_DIR | NFC_ECC_OP,
               nfc->regs + NFC_REG_CMD);
 
        ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
-       sunxi_nfc_randomizer_disable(mtd);
+       sunxi_nfc_randomizer_disable(nand);
        if (ret)
                return ret;
 
@@ -1163,11 +1040,11 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
        return 0;
 }
 
-static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
+static void sunxi_nfc_hw_ecc_write_extra_oob(struct nand_chip *nand,
                            &nbs