Merge tag 'stm32-dt-for-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorOlof Johansson <olof@lixom.net>
Sat, 14 Jul 2018 21:27:22 +0000 (14:27 -0700)
committerOlof Johansson <olof@lixom.net>
Sat, 14 Jul 2018 21:27:22 +0000 (14:27 -0700)
STM32 DT updates for v4.19, round 1

Highlights:
----------

-MCU platforms update:
 -Update RTC syscfg bindings on stm32f746 and stm32f429
 -Update IWDG node with LSI clock name on stm32f429

-MPU STM32MP157 platform update:
 -Add HASH support
 -Add m_can support and enable it on EV1 board
 -Add RTC suppoort and enable it on ED1 board
 -Add USB OTG HS support and enable it on EV1 board
 -Enable USB Host EHCI on EV1 board
 -Add DFSDM support
 -Add SPI support
 -Add ETH support and enable it on EV1 board
 -Add IWDG support and enable it on ED1 board
 -Fix useless GPIO aliases and reorder nodes

* tag 'stm32-dt-for-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (22 commits)
  ARM: dts: stm32: update iwdg with lsi clock name for stm32f429
  ARM: dts: stm32: add iwdg2 support for stm32mp157c-ed1
  ARM: dts: stm32: add iwdg2 support for stm32mp157c
  ARM: dts: stm32: Reorder nodes in stm32mp157c-ed1
  ARM: dts: stm32: remove gpio aliases for stm32mp157c
  ARM: dts: stm32: add support of ethernet on stm32mp157c-ev1
  ARM: dts: stm32: Add ethernet dwmac on stm32mp1
  ARM: dts: stm32: Add syscfg on stm32mp1
  ARM: dts: stm32: add SPI1 support on stm32mp157c-ev1
  ARM: dts: stm32: add SPI support on stm32mp157c
  ARM: dts: stm32: Add DFSDM support to stm32mp157c
  ARM: dts: stm32: Add ADC support to stm32mp157c
  ARM: dts: stm32: enable USB OTG HS on stm32mp157c-ev1
  ARM: dts: stm32: add USB OTG HS support for stm32mp157c SoC
  ARM: dts: stm32: enable USB Host (USBH) EHCI controller on stm32mp157c-ev1
  ARM: dts: stm32: enable RTC on stm32mp157c-ed1
  ARM: dts: stm32: add RTC support to stm32mp157c
  ARM: dts: stm32: m_can activation on stm32mp157c-ev1
  ARM: dts: stm32: m_can support to stm32mp157c
  ARM: dts: stm32: Add HASH support on stm32mp157c
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
arch/arm/boot/dts/stm32f429.dtsi
arch/arm/boot/dts/stm32f746.dtsi
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
arch/arm/boot/dts/stm32mp157c-ed1.dts
arch/arm/boot/dts/stm32mp157c-ev1.dts
arch/arm/boot/dts/stm32mp157c.dtsi

index ede77e0f1c41d044829bf7488959800736e3e514..e35d782e7e5f2f0281d1c8936bb90ea70b8d83b8 100644 (file)
                        interrupt-parent = <&exti>;
                        interrupts = <17 1>;
                        interrupt-names = "alarm";
-                       st,syscfg = <&pwrcfg>;
+                       st,syscfg = <&pwrcfg 0x00 0x100>;
                        status = "disabled";
                };
 
                        compatible = "st,stm32-iwdg";
                        reg = <0x40003000 0x400>;
                        clocks = <&clk_lsi>;
+                       clock-names = "lsi";
                        status = "disabled";
                };
 
index 1479e3eb05fa455d88dbbbc2c25dc6cc1961ea10..f48d06a80d1d67e09cb2e0ba2a9873583df28947 100644 (file)
                        interrupt-parent = <&exti>;
                        interrupts = <17 1>;
                        interrupt-names = "alarm";
-                       st,syscfg = <&pwrcfg>;
+                       st,syscfg = <&pwrcfg 0x00 0x100>;
                        status = "disabled";
                };
 
index 4839db146890fd59480ce7c00b075cf381b7d498..c4851271e8105ebe4f92196cd808d64ccea626d9 100644 (file)
                                };
                        };
 
+                       ethernet0_rgmii_pins_a: rgmii-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+                                                <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+                                                <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+                                                <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+                                                <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+                                                <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+                                                <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+                                                <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+                                                <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <3>;
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+                                                <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+                                                <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
+                                                <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+                                                <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+                                                <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+                                       bias-disable;
+                               };
+                       };
+
+                       ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+                                                <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+                                                <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+                                                <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+                                                <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+                                                <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+                                                <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+                                                <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+                                                <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
+                                                <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+                                                <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+                                                <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
+                                                <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
+                                                <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+                                                <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+                               };
+                       };
+
                        i2c1_pins_a: i2c1-0 {
                                pins {
                                        pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
                                };
                        };
 
+                       m_can1_pins_a: m-can1-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
+                                       slew-rate = <1>;
+                                       drive-push-pull;
+                                       bias-disable;
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
+                                       bias-disable;
+                               };
+                       };
+
                        pwm2_pins_a: pwm2-0 {
                                pins {
                                        pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
                        pins-are-numbered;
                        interrupt-parent = <&exti>;
                        st,syscfg = <&exti 0x60 0xff>;
-                       status = "disabled";
 
                        gpioz: gpio@54004000 {
                                gpio-controller;
                                        slew-rate = <0>;
                                };
                        };
+
+                       spi1_pins_a: spi1-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
+                                                <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <1>;
+                               };
+
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
+                                       bias-disable;
+                               };
+                       };
                };
        };
 };
index ae336530b59b8ec0970a9baef8eabc76378414d6..f77bea49c0793f4f07cb2cd912945f4c199c9e10 100644 (file)
        };
 };
 
+&i2c4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c4_pins_a>;
+       i2c-scl-rising-time-ns = <185>;
+       i2c-scl-falling-time-ns = <20>;
+       status = "okay";
+};
+
+&iwdg2 {
+       timeout-sec = <32>;
+       status = "okay";
+};
+
 &rng1 {
        status = "okay";
 };
 
+&rtc {
+       status = "okay";
+};
+
 &timers6 {
        status = "okay";
        timer@5 {
        };
 };
 
-&i2c4 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&i2c4_pins_a>;
-       i2c-scl-rising-time-ns = <185>;
-       i2c-scl-falling-time-ns = <20>;
-       status = "okay";
-};
-
 &uart4 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart4_pins_a>;
index 9382d80630318dde15d69d0b9fa9e62b65b70594..372bc2ea6b92192422368bf8413fe62849321d08 100644 (file)
 
        aliases {
                serial0 = &uart4;
+               ethernet0 = &ethernet0;
+       };
+};
+
+&ethernet0 {
+       status = "okay";
+       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
+       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
+       pinctrl-names = "default", "sleep";
+       phy-mode = "rgmii";
+       max-speed = <1000>;
+       phy-handle = <&phy0>;
+
+       mdio0 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "snps,dwmac-mdio";
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+               };
        };
 };
 
        status = "okay";
 };
 
+&m_can1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&m_can1_pins_a>;
+       status = "okay";
+};
+
 &qspi {
        pinctrl-names = "default";
        pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
        };
 };
 
+&spi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi1_pins_a>;
+       status = "disabled";
+};
+
 &timers2 {
        status = "disabled";
        pwm {
        };
 };
 
+&usbh_ehci {
+       phys = <&usbphyc_port0>;
+       phy-names = "usb";
+       status = "okay";
+};
+
+&usbotg_hs {
+       dr_mode = "peripheral";
+       phys = <&usbphyc_port1 0>;
+       phy-names = "usb2-phy";
+       status = "okay";
+};
+
 &usbphyc {
        status = "okay";
 };
index 7d17538934538239c7634e7cdde7eb5cd2117971..661be948ab7424759ebfdb2d1c780822d17f38b0 100644 (file)
                cpu_on = <0x84000003>;
        };
 
-       aliases {
-               gpio0 = &gpioa;
-               gpio1 = &gpiob;
-               gpio2 = &gpioc;
-               gpio3 = &gpiod;
-               gpio4 = &gpioe;
-               gpio5 = &gpiof;
-               gpio6 = &gpiog;
-               gpio7 = &gpioh;
-               gpio8 = &gpioi;
-               gpio9 = &gpioj;
-               gpio10 = &gpiok;
-       };
-
        intc: interrupt-controller@a0021000 {
                compatible = "arm,cortex-a7-gic";
                #interrupt-cells = <3>;
                        };
                };
 
+               spi2: spi@4000b000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32h7-spi";
+                       reg = <0x4000b000 0x400>;
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&rcc SPI2_K>;
+                       resets = <&rcc SPI2_R>;
+                       dmas = <&dmamux1 39 0x400 0x05>,
+                              <&dmamux1 40 0x400 0x05>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               spi3: spi@4000c000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32h7-spi";
+                       reg = <0x4000c000 0x400>;
+                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&rcc SPI3_K>;
+                       resets = <&rcc SPI3_R>;
+                       dmas = <&dmamux1 61 0x400 0x05>,
+                              <&dmamux1 62 0x400 0x05>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
                usart2: serial@4000e000 {
                        compatible = "st,stm32h7-uart";
                        reg = <0x4000e000 0x400>;
                        status = "disabled";
                };
 
+               spi1: spi@44004000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32h7-spi";
+                       reg = <0x44004000 0x400>;
+                       interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&rcc SPI1_K>;
+                       resets = <&rcc SPI1_R>;
+                       dmas = <&dmamux1 37 0x400 0x05>,
+                              <&dmamux1 38 0x400 0x05>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               spi4: spi@44005000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32h7-spi";
+                       reg = <0x44005000 0x400>;
+                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&rcc SPI4_K>;
+                       resets = <&rcc SPI4_R>;
+                       dmas = <&dmamux1 83 0x400 0x05>,
+                              <&dmamux1 84 0x400 0x05>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
                timers15: timer@44006000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        };
                };
 
+               spi5: spi@44009000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32h7-spi";
+                       reg = <0x44009000 0x400>;
+                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&rcc SPI5_K>;
+                       resets = <&rcc SPI5_R>;
+                       dmas = <&dmamux1 85 0x400 0x05>,
+                              <&dmamux1 86 0x400 0x05>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               dfsdm: dfsdm@4400d000 {
+                       compatible = "st,stm32mp1-dfsdm";
+                       reg = <0x4400d000 0x800>;
+                       clocks = <&rcc DFSDM_K>;
+                       clock-names = "dfsdm";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+
+                       dfsdm0: filter@0 {
+                               compatible = "st,stm32-dfsdm-adc";
+                               #io-channel-cells = <1>;
+                               reg = <0>;
+                               interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dmamux1 101 0x400 0x01>;
+                               dma-names = "rx";
+                               status = "disabled";
+                       };
+
+                       dfsdm1: filter@1 {
+                               compatible = "st,stm32-dfsdm-adc";
+                               #io-channel-cells = <1>;
+                               reg = <1>;
+                               interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dmamux1 102 0x400 0x01>;
+                               dma-names = "rx";
+                               status = "disabled";
+                       };
+
+                       dfsdm2: filter@2 {
+                               compatible = "st,stm32-dfsdm-adc";
+                               #io-channel-cells = <1>;
+                               reg = <2>;
+                               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dmamux1 103 0x400 0x01>;
+                               dma-names = "rx";
+                               status = "disabled";
+                       };
+
+                       dfsdm3: filter@3 {
+                               compatible = "st,stm32-dfsdm-adc";
+                               #io-channel-cells = <1>;
+                               reg = <3>;
+                               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dmamux1 104 0x400 0x01>;
+                               dma-names = "rx";
+                               status = "disabled";
+                       };
+
+                       dfsdm4: filter@4 {
+                               compatible = "st,stm32-dfsdm-adc";
+                               #io-channel-cells = <1>;
+                               reg = <4>;
+                               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dmamux1 91 0x400 0x01>;
+                               dma-names = "rx";
+                               status = "disabled";
+                       };
+
+                       dfsdm5: filter@5 {
+                               compatible = "st,stm32-dfsdm-adc";
+                               #io-channel-cells = <1>;
+                               reg = <5>;
+                               interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dmamux1 92 0x400 0x01>;
+                               dma-names = "rx";
+                               status = "disabled";
+                       };
+               };
+
+               m_can1: can@4400e000 {
+                       compatible = "bosch,m_can";
+                       reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
+                       reg-names = "m_can", "message_ram";
+                       interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "int0", "int1";
+                       clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+                       clock-names = "hclk", "cclk";
+                       bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+                       status = "disabled";
+               };
+
+               m_can2: can@4400f000 {
+                       compatible = "bosch,m_can";
+                       reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+                       reg-names = "m_can", "message_ram";
+                       interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "int0", "int1";
+                       clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+                       clock-names = "hclk", "cclk";
+                       bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+                       status = "disabled";
+               };
+
                dma1: dma@48000000 {
                        compatible = "st,stm32-dma";
                        reg = <0x48000000 0x400>;
                        clocks = <&rcc DMAMUX>;
                };
 
+               adc: adc@48003000 {
+                       compatible = "st,stm32mp1-adc-core";
+                       reg = <0x48003000 0x400>;
+                       interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+                       clock-names = "bus", "adc";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+
+                       adc1: adc@0 {
+                               compatible = "st,stm32mp1-adc";
+                               #io-channel-cells = <1>;
+                               reg = <0x0>;
+                               interrupt-parent = <&adc>;
+                               interrupts = <0>;
+                               dmas = <&dmamux1 9 0x400 0x01>;
+                               dma-names = "rx";
+                               status = "disabled";
+                       };
+
+                       adc2: adc@100 {
+                               compatible = "st,stm32mp1-adc";
+                               #io-channel-cells = <1>;
+                               reg = <0x100>;
+                               interrupt-parent = <&adc>;
+                               interrupts = <1>;
+                               dmas = <&dmamux1 10 0x400 0x01>;
+                               dma-names = "rx";
+                               status = "disabled";
+                       };
+               };
+
+               usbotg_hs: usb-otg@49000000 {
+                       compatible = "snps,dwc2";
+                       reg = <0x49000000 0x10000>;
+                       clocks = <&rcc USBO_K>;
+                       clock-names = "otg";
+                       resets = <&rcc USBO_R>;
+                       reset-names = "dwc2";
+                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+                       g-rx-fifo-size = <256>;
+                       g-np-tx-fifo-size = <32>;
+                       g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+                       dr_mode = "otg";
+                       status = "disabled";
+               };
+
                rcc: rcc@50000000 {
                        compatible = "st,stm32mp1-rcc", "syscon";
                        reg = <0x50000000 0x1000>;
                        reg = <0x5000d000 0x400>;
                };
 
+               syscfg: syscon@50020000 {
+                       compatible = "st,stm32mp157-syscfg", "syscon";
+                       reg = <0x50020000 0x400>;
+               };
+
                lptimer2: timer@50021000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
                };
 
+               hash1: hash@54002000 {
+                       compatible = "st,stm32f756-hash";
+                       reg = <0x54002000 0x400>;
+                       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&rcc HASH1>;
+                       resets = <&rcc HASH1_R>;
+                       dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0 0x0>;
+                       dma-names = "in";
+                       dma-maxburst = <2>;
+                       status = "disabled";
+               };
+
                rng1: rng@54003000 {
                        compatible = "st,stm32-rng";
                        reg = <0x54003000 0x400>;
                        status = "disabled";
                };
 
+               stmmac_axi_config_0: stmmac-axi-config {
+                       snps,wr_osr_lmt = <0x7>;
+                       snps,rd_osr_lmt = <0x7>;
+                       snps,blen = <0 0 0 0 16 8 4>;
+               };
+
+               ethernet0: ethernet@5800a000 {
+                       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+                       reg = <0x5800a000 0x2000>;
+                       reg-names = "stmmaceth";
+                       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq";
+                       clock-names = "stmmaceth",
+                                     "mac-clk-tx",
+                                     "mac-clk-rx",
+                                     "ethstp",
+                                     "syscfg-clk";
+                       clocks = <&rcc ETHMAC>,
+                                <&rcc ETHTX>,
+                                <&rcc ETHRX>,
+                                <&rcc ETHSTP>,
+                                <&rcc SYSCFG>;
+                       st,syscon = <&syscfg 0x4>;
+                       snps,mixed-burst;
+                       snps,pbl = <2>;
+                       snps,axi-config = <&stmmac_axi_config_0>;
+                       snps,tso;
+                       status = "disabled";
+               };
+
                usbh_ohci: usbh-ohci@5800c000 {
                        compatible = "generic-ohci";
                        reg = <0x5800c000 0x1000>;
                        status = "disabled";
                };
 
+               iwdg2: watchdog@5a002000 {
+                       compatible = "st,stm32mp1-iwdg";
+                       reg = <0x5a002000 0x400>;
+                       clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
+                       clock-names = "pclk", "lsi";
+                       status = "disabled";
+               };
+
                usbphyc: usbphyc@5a006000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
                };
 
+               spi6: spi@5c001000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32h7-spi";
+                       reg = <0x5c001000 0x400>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&rcc SPI6_K>;
+                       resets = <&rcc SPI6_R>;
+                       dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0>,
+                              <&mdma1 35 0x0 0x40002 0x0 0x0 0>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
                i2c4: i2c@5c002000 {
                        compatible = "st,stm32f7-i2c";
                        reg = <0x5c002000 0x400>;
                        status = "disabled";
                };
 
+               rtc: rtc@5c004000 {
+                       compatible = "st,stm32mp1-rtc";
+                       reg = <0x5c004000 0x400>;
+                       clocks = <&rcc RTCAPB>, <&rcc RTC>;
+                       clock-names = "pclk", "rtc_ck";
+                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
                i2c6: i2c@5c009000 {
                        compatible = "st,stm32f7-i2c";
                        reg = <0x5c009000 0x400>;