Merge branch 'bt-fix' (bluetooth fixes from Marcel)
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 11 Sep 2017 19:45:47 +0000 (12:45 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 11 Sep 2017 19:45:47 +0000 (12:45 -0700)
Pull bluetooth fix from Marcel Holtmann:
 "All of our mgmt-tester, l2cap-test and rfcomm-tester unit tests are
  passing with this patch"

* emailed patch from Marcel Holtmann <marcel@holtmann.org>:
  Bluetooth: Properly check L2CAP config option output buffer length

677 files changed:
Documentation/devicetree/bindings/arm/amlogic.txt
Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
Documentation/devicetree/bindings/arm/bhf.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/cpus.txt
Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt [new file with mode: 0644]
Documentation/devicetree/bindings/arm/mediatek.txt
Documentation/devicetree/bindings/arm/omap/omap.txt
Documentation/devicetree/bindings/arm/qcom.txt
Documentation/devicetree/bindings/arm/rockchip.txt
Documentation/devicetree/bindings/arm/shmobile.txt
Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt
Documentation/devicetree/bindings/display/renesas,du.txt
Documentation/devicetree/bindings/dma/ti-edma.txt
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
Documentation/devicetree/bindings/net/can/c_can.txt
Documentation/devicetree/bindings/net/mediatek-net.txt
Documentation/devicetree/bindings/pci/mvebu-pci.txt
Documentation/devicetree/bindings/power/renesas,apmu.txt
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
Documentation/devicetree/bindings/reset/renesas,rst.txt
Documentation/devicetree/bindings/reset/uniphier-reset.txt
Documentation/devicetree/bindings/serial/mtk-uart.txt
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
Documentation/devicetree/bindings/soc/rockchip/grf.txt
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
Documentation/devicetree/bindings/sram/renesas,smp-sram.txt [new file with mode: 0644]
Documentation/devicetree/bindings/sram/sunxi-sram.txt
Documentation/devicetree/bindings/vendor-prefixes.txt
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
Documentation/driver-api/firmware/request_firmware.rst
MAINTAINERS
arch/arm/Kconfig.debug
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/am335x-bone-common.dtsi
arch/arm/boot/dts/am335x-chiliboard.dts
arch/arm/boot/dts/am335x-evm.dts
arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts [new file with mode: 0644]
arch/arm/boot/dts/am437x-gp-evm.dts
arch/arm/boot/dts/am43x-epos-evm.dts
arch/arm/boot/dts/am571x-idk.dts
arch/arm/boot/dts/am572x-idk.dts
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
arch/arm/boot/dts/am57xx-beagle-x15-revc.dts [new file with mode: 0644]
arch/arm/boot/dts/am57xx-beagle-x15.dts
arch/arm/boot/dts/am57xx-idk-common.dtsi
arch/arm/boot/dts/armada-370.dtsi
arch/arm/boot/dts/armada-375.dtsi
arch/arm/boot/dts/armada-380.dtsi
arch/arm/boot/dts/armada-385-db-ap.dts
arch/arm/boot/dts/armada-385-turris-omnia.dts
arch/arm/boot/dts/armada-385.dtsi
arch/arm/boot/dts/armada-388-clearfog.dts
arch/arm/boot/dts/armada-388-clearfog.dtsi
arch/arm/boot/dts/armada-388-db.dts
arch/arm/boot/dts/armada-388-gp.dts
arch/arm/boot/dts/armada-388-rd.dts
arch/arm/boot/dts/armada-38x.dtsi
arch/arm/boot/dts/armada-390-db.dts
arch/arm/boot/dts/armada-395-gp.dts
arch/arm/boot/dts/armada-398-db.dts
arch/arm/boot/dts/armada-39x.dtsi
arch/arm/boot/dts/armada-xp-98dx3236.dtsi
arch/arm/boot/dts/armada-xp-db.dts
arch/arm/boot/dts/armada-xp-gp.dts
arch/arm/boot/dts/armada-xp-mv78230.dtsi
arch/arm/boot/dts/armada-xp-mv78260.dtsi
arch/arm/boot/dts/armada-xp-mv78460.dtsi
arch/arm/boot/dts/aspeed-g4.dtsi
arch/arm/boot/dts/at91-sama5d27_som1.dtsi [new file with mode: 0644]
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts [new file with mode: 0644]
arch/arm/boot/dts/at91-sama5d2_xplained.dts
arch/arm/boot/dts/at91sam9g45.dtsi
arch/arm/boot/dts/at91sam9m10g45ek.dts
arch/arm/boot/dts/bcm-cygnus.dtsi
arch/arm/boot/dts/bcm-nsp.dtsi
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
arch/arm/boot/dts/bcm2835-rpi-a.dts
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
arch/arm/boot/dts/bcm2835-rpi-b.dts
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts [new file with mode: 0644]
arch/arm/boot/dts/bcm2835-rpi-zero.dts
arch/arm/boot/dts/bcm2835-rpi.dtsi
arch/arm/boot/dts/bcm2836-rpi-2-b.dts
arch/arm/boot/dts/bcm2836.dtsi
arch/arm/boot/dts/bcm2837-rpi-3-b.dts
arch/arm/boot/dts/bcm2837.dtsi [new file with mode: 0644]
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
arch/arm/boot/dts/bcm47189-tenda-ac9.dts
arch/arm/boot/dts/bcm5301x.dtsi
arch/arm/boot/dts/bcm53573.dtsi
arch/arm/boot/dts/bcm911360_entphn.dts
arch/arm/boot/dts/bcm947189acdbmr.dts [new file with mode: 0644]
arch/arm/boot/dts/bcm958522er.dts
arch/arm/boot/dts/bcm958525er.dts
arch/arm/boot/dts/bcm958525xmc.dts
arch/arm/boot/dts/bcm958622hr.dts
arch/arm/boot/dts/bcm958623hr.dts
arch/arm/boot/dts/bcm958625hr.dts
arch/arm/boot/dts/bcm958625k.dts
arch/arm/boot/dts/da850-lego-ev3.dts
arch/arm/boot/dts/dove-d3plug.dts
arch/arm/boot/dts/dove.dtsi
arch/arm/boot/dts/dra7-evm-common.dtsi [new file with mode: 0644]
arch/arm/boot/dts/dra7-evm.dts
arch/arm/boot/dts/dra7.dtsi
arch/arm/boot/dts/dra71-evm.dts
arch/arm/boot/dts/dra72-evm-common.dtsi
arch/arm/boot/dts/dra72-evm-revc.dts
arch/arm/boot/dts/dra72-evm-tps65917.dtsi
arch/arm/boot/dts/dra72-evm.dts
arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi [new file with mode: 0644]
arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi [new file with mode: 0644]
arch/arm/boot/dts/dra76-evm.dts [new file with mode: 0644]
arch/arm/boot/dts/dra76x.dtsi [new file with mode: 0644]
arch/arm/boot/dts/exynos3250-artik5-eval.dts
arch/arm/boot/dts/exynos3250-artik5.dtsi
arch/arm/boot/dts/exynos3250-monk.dts
arch/arm/boot/dts/exynos3250-rinato.dts
arch/arm/boot/dts/exynos4210-trats.dts
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
arch/arm/boot/dts/exynos4412-origen.dts
arch/arm/boot/dts/exynos4412-trats2.dts
arch/arm/boot/dts/exynos5250-arndale.dts
arch/arm/boot/dts/exynos5250-smdk5250.dts
arch/arm/boot/dts/exynos5250-snow-common.dtsi
arch/arm/boot/dts/exynos5250-spring.dts
arch/arm/boot/dts/exynos5260-xyref5260.dts
arch/arm/boot/dts/exynos5410-smdk5410.dts
arch/arm/boot/dts/exynos5420-peach-pit.dts
arch/arm/boot/dts/exynos5440.dtsi
arch/arm/boot/dts/exynos5800-peach-pi.dts
arch/arm/boot/dts/gemini-dlink-dir-685.dts [new file with mode: 0644]
arch/arm/boot/dts/gemini-nas4220b.dts
arch/arm/boot/dts/gemini-rut1xx.dts
arch/arm/boot/dts/gemini-sq201.dts
arch/arm/boot/dts/gemini-wbd111.dts
arch/arm/boot/dts/gemini-wbd222.dts
arch/arm/boot/dts/gemini.dtsi
arch/arm/boot/dts/imx25.dtsi
arch/arm/boot/dts/imx53-cx9020.dts [new file with mode: 0644]
arch/arm/boot/dts/imx53-pinfunc.h
arch/arm/boot/dts/imx53.dtsi
arch/arm/boot/dts/imx6dl-gw52xx.dts
arch/arm/boot/dts/imx6dl-gw53xx.dts
arch/arm/boot/dts/imx6dl-gw54xx.dts
arch/arm/boot/dts/imx6dl-riotboard.dts
arch/arm/boot/dts/imx6q-apalis-eval.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6q-apalis-ixora.dts
arch/arm/boot/dts/imx6q-b850v3.dts
arch/arm/boot/dts/imx6q-bx50v3.dtsi
arch/arm/boot/dts/imx6q-gw52xx.dts
arch/arm/boot/dts/imx6q-gw53xx.dts
arch/arm/boot/dts/imx6q-gw54xx.dts
arch/arm/boot/dts/imx6qdl-apalis.dtsi
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
arch/arm/boot/dts/imx6qdl-gw553x.dtsi
arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
arch/arm/boot/dts/imx6qdl.dtsi
arch/arm/boot/dts/imx6sl.dtsi
arch/arm/boot/dts/imx6sx.dtsi
arch/arm/boot/dts/imx6ul-14x14-evk.dts
arch/arm/boot/dts/imx6ul-geam-kit.dts [deleted file]
arch/arm/boot/dts/imx6ul-geam.dts [new file with mode: 0644]
arch/arm/boot/dts/imx6ul-geam.dtsi [deleted file]
arch/arm/boot/dts/imx6ul-isiot-common.dtsi [deleted file]
arch/arm/boot/dts/imx6ul-isiot-emmc.dts
arch/arm/boot/dts/imx6ul-isiot-nand.dts
arch/arm/boot/dts/imx6ul-isiot.dtsi
arch/arm/boot/dts/imx6ul-liteboard.dts
arch/arm/boot/dts/imx6ul.dtsi
arch/arm/boot/dts/imx7-colibri.dtsi
arch/arm/boot/dts/imx7d-sdb.dts
arch/arm/boot/dts/imx7s.dtsi
arch/arm/boot/dts/keystone-k2e-evm.dts
arch/arm/boot/dts/keystone-k2e.dtsi
arch/arm/boot/dts/keystone-k2g-evm.dts
arch/arm/boot/dts/keystone-k2g-ice.dts
arch/arm/boot/dts/keystone-k2g.dtsi
arch/arm/boot/dts/keystone-k2hk-evm.dts
arch/arm/boot/dts/keystone-k2hk.dtsi
arch/arm/boot/dts/keystone-k2l-evm.dts
arch/arm/boot/dts/keystone-k2l.dtsi
arch/arm/boot/dts/kirkwood-6192.dtsi
arch/arm/boot/dts/kirkwood-6281.dtsi
arch/arm/boot/dts/kirkwood-6282.dtsi
arch/arm/boot/dts/kirkwood-98dx4122.dtsi
arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
arch/arm/boot/dts/meson.dtsi
arch/arm/boot/dts/meson6.dtsi
arch/arm/boot/dts/meson8.dtsi
arch/arm/boot/dts/meson8b.dtsi
arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
arch/arm/boot/dts/mt2701.dtsi
arch/arm/boot/dts/mt6323.dtsi [new file with mode: 0644]
arch/arm/boot/dts/mt7623-evb.dts [deleted file]
arch/arm/boot/dts/mt7623.dtsi
arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts [new file with mode: 0644]
arch/arm/boot/dts/mt7623n-rfb-nand.dts [new file with mode: 0644]
arch/arm/boot/dts/mt7623n-rfb.dtsi [new file with mode: 0644]
arch/arm/boot/dts/omap3-beagle-xm.dts
arch/arm/boot/dts/omap3-beagle.dts
arch/arm/boot/dts/omap3-cm-t3517.dts
arch/arm/boot/dts/omap3-cm-t3730.dts
arch/arm/boot/dts/omap3-devkit8000-common.dtsi
arch/arm/boot/dts/omap3-evm-common.dtsi
arch/arm/boot/dts/omap3-n900.dts
arch/arm/boot/dts/omap3-overo-base.dtsi
arch/arm/boot/dts/omap3-tao3530.dtsi
arch/arm/boot/dts/omap3-zoom3.dts
arch/arm/boot/dts/omap3.dtsi
arch/arm/boot/dts/omap3430-sdp.dts
arch/arm/boot/dts/omap4-droid4-xt894.dts
arch/arm/boot/dts/omap4-duovero-parlor.dts
arch/arm/boot/dts/omap4-panda-common.dtsi
arch/arm/boot/dts/omap4-sdp-es23plus.dts
arch/arm/boot/dts/omap4-sdp.dts
arch/arm/boot/dts/omap4-var-om44customboard.dtsi
arch/arm/boot/dts/omap5-board-common.dtsi
arch/arm/boot/dts/omap5-cm-t54.dts
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
arch/arm/boot/dts/qcom-ipq4019.dtsi
arch/arm/boot/dts/qcom-msm8974.dtsi
arch/arm/boot/dts/r7s72100-genmai.dts
arch/arm/boot/dts/r7s72100-rskrza1.dts
arch/arm/boot/dts/r7s72100.dtsi
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
arch/arm/boot/dts/r8a7743-iwg20m.dtsi
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
arch/arm/boot/dts/r8a7743.dtsi
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
arch/arm/boot/dts/r8a7745.dtsi
arch/arm/boot/dts/r8a7790.dtsi
arch/arm/boot/dts/r8a7791-koelsch.dts
arch/arm/boot/dts/r8a7791.dtsi
arch/arm/boot/dts/r8a7792.dtsi
arch/arm/boot/dts/r8a7793.dtsi
arch/arm/boot/dts/r8a7794.dtsi
arch/arm/boot/dts/rk3036-kylin.dts
arch/arm/boot/dts/rk3036.dtsi
arch/arm/boot/dts/rk3066a-bqcurie2.dts
arch/arm/boot/dts/rk3066a-mk808.dts
arch/arm/boot/dts/rk3066a-rayeager.dts
arch/arm/boot/dts/rk3188-px3-evb.dts
arch/arm/boot/dts/rk3188-radxarock.dts
arch/arm/boot/dts/rk3229-evb.dts
arch/arm/boot/dts/rk3229.dtsi [new file with mode: 0644]
arch/arm/boot/dts/rk322x.dtsi
arch/arm/boot/dts/rk3288-evb.dtsi
arch/arm/boot/dts/rk3288-fennec.dts
arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
arch/arm/boot/dts/rk3288-firefly-reload.dts
arch/arm/boot/dts/rk3288-firefly.dtsi
arch/arm/boot/dts/rk3288-miqi.dts
arch/arm/boot/dts/rk3288-phycore-rdk.dts
arch/arm/boot/dts/rk3288-phycore-som.dtsi
arch/arm/boot/dts/rk3288-popmetal.dts
arch/arm/boot/dts/rk3288-r89.dts
arch/arm/boot/dts/rk3288-rock2-som.dtsi
arch/arm/boot/dts/rk3288-rock2-square.dts
arch/arm/boot/dts/rk3288-tinker.dts
arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
arch/arm/boot/dts/rk3288-veyron.dtsi
arch/arm/boot/dts/rk3288.dtsi
arch/arm/boot/dts/rv1108-evb.dts
arch/arm/boot/dts/rv1108.dtsi
arch/arm/boot/dts/sama5d2.dtsi
arch/arm/boot/dts/spear1310.dtsi
arch/arm/boot/dts/spear1340.dtsi
arch/arm/boot/dts/ste-dbx5x0.dtsi
arch/arm/boot/dts/stm32429i-eval.dts
arch/arm/boot/dts/stm32f429-disco.dts
arch/arm/boot/dts/stm32f429.dtsi
arch/arm/boot/dts/stm32f469-disco.dts
arch/arm/boot/dts/stm32f746.dtsi
arch/arm/boot/dts/stm32f769-disco.dts
arch/arm/boot/dts/stm32h743.dtsi
arch/arm/boot/dts/stm32h743i-eval.dts
arch/arm/boot/dts/sun6i-a31.dtsi
arch/arm/boot/dts/sun7i-a20-cubietruck.dts
arch/arm/boot/dts/sun8i-a23-a33.dtsi
arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts [new file with mode: 0644]
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
arch/arm/boot/dts/sun8i-a83t.dtsi
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts [new file with mode: 0644]
arch/arm/boot/dts/tegra114-dalmore.dts
arch/arm/boot/dts/tegra124-jetson-tk1.dts
arch/arm/boot/dts/tegra124.dtsi
arch/arm/boot/dts/tegra20-paz00.dts
arch/arm/boot/dts/tegra30-beaver.dts
arch/arm/boot/dts/tps65217.dtsi
arch/arm/boot/dts/uniphier-ld4-ref.dts
arch/arm/boot/dts/uniphier-ld4.dtsi
arch/arm/boot/dts/uniphier-ld6b-ref.dts
arch/arm/boot/dts/uniphier-ld6b.dtsi
arch/arm/boot/dts/uniphier-pinctrl.dtsi
arch/arm/boot/dts/uniphier-pro4-ace.dts
arch/arm/boot/dts/uniphier-pro4-ref.dts
arch/arm/boot/dts/uniphier-pro4-sanji.dts
arch/arm/boot/dts/uniphier-pro4.dtsi
arch/arm/boot/dts/uniphier-pro5.dtsi
arch/arm/boot/dts/uniphier-pxs2-gentil.dts
arch/arm/boot/dts/uniphier-pxs2-vodka.dts
arch/arm/boot/dts/uniphier-pxs2.dtsi
arch/arm/boot/dts/uniphier-sld3-ref.dts [deleted file]
arch/arm/boot/dts/uniphier-sld3.dtsi [deleted file]
arch/arm/boot/dts/uniphier-sld8-ref.dts
arch/arm/boot/dts/uniphier-sld8.dtsi
arch/arm/boot/dts/versatile-pb.dts
arch/arm/boot/dts/zx296702-ad1.dts
arch/arm/boot/dts/zynq-7000.dtsi
arch/arm/boot/dts/zynq-parallella.dts
arch/arm/boot/dts/zynq-zc702.dts
arch/arm/boot/dts/zynq-zc706.dts
arch/arm/boot/dts/zynq-zed.dts
arch/arm/boot/dts/zynq-zybo.dts
arch/arm/configs/aspeed_g4_defconfig
arch/arm/configs/aspeed_g5_defconfig
arch/arm/configs/bcm2835_defconfig
arch/arm/configs/davinci_all_defconfig
arch/arm/configs/exynos_defconfig
arch/arm/configs/ezx_defconfig
arch/arm/configs/imx_v6_v7_defconfig
arch/arm/configs/ixp4xx_defconfig
arch/arm/configs/keystone_defconfig
arch/arm/configs/multi_v7_defconfig
arch/arm/configs/omap2plus_defconfig
arch/arm/configs/qcom_defconfig
arch/arm/configs/shmobile_defconfig
arch/arm/configs/sunxi_defconfig
arch/arm/configs/tegra_defconfig
arch/arm/configs/vexpress_defconfig
arch/arm/include/debug/omap2plus.S
arch/arm/kernel/cpuidle.c
arch/arm/kernel/devtree.c
arch/arm/kernel/topology.c
arch/arm/mach-ep93xx/clock.c
arch/arm/mach-ep93xx/core.c
arch/arm/mach-ep93xx/edb93xx.c
arch/arm/mach-ep93xx/include/mach/platform.h
arch/arm/mach-ep93xx/soc.h
arch/arm/mach-exynos/suspend.c
arch/arm/mach-gemini/Kconfig
arch/arm/mach-hisi/platsmp.c
arch/arm/mach-imx/gpc.c
arch/arm/mach-mediatek/mediatek.c
arch/arm/mach-mediatek/platsmp.c
arch/arm/mach-mvebu/Kconfig
arch/arm/mach-mvebu/kirkwood.c
arch/arm/mach-omap2/Kconfig
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/dma.c
arch/arm/mach-omap2/id.c
arch/arm/mach-omap2/omap-smp.c
arch/arm/mach-omap2/omap-wakeupgen.c
arch/arm/mach-omap2/omap_device.c
arch/arm/mach-omap2/omap_hwmod.c
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
arch/arm/mach-omap2/pdata-quirks.c
arch/arm/mach-omap2/powerdomains7xx_data.c
arch/arm/mach-omap2/prm3xxx.c
arch/arm/mach-omap2/prm44xx.c
arch/arm/mach-omap2/soc.h
arch/arm/mach-rockchip/Kconfig
arch/arm/mach-rockchip/platsmp.c
arch/arm/mach-s3c24xx/Kconfig
arch/arm/mach-s3c24xx/common.c
arch/arm/mach-s3c24xx/include/mach/regs-clock.h
arch/arm/mach-s3c24xx/mach-mini2440.c
arch/arm/mach-s3c24xx/mach-smdk2443.c
arch/arm/mach-s3c24xx/sleep.S
arch/arm/mach-shmobile/Kconfig
arch/arm/mach-shmobile/pm-rcar-gen2.c
arch/arm/mach-shmobile/pm-rmobile.c
arch/arm/mach-shmobile/setup-rcar-gen2.c
arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/tegra.c
arch/arm/plat-samsung/include/plat/map-s3c.h
arch/arm64/Kconfig.platforms
arch/arm64/boot/dts/allwinner/Makefile
arch/arm64/boot/dts/allwinner/axp803.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts [new file with mode: 0644]
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts [new file with mode: 0644]
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
arch/arm64/boot/dts/apm/apm-storm.dtsi
arch/arm64/boot/dts/arm/foundation-v8.dtsi
arch/arm64/boot/dts/arm/juno-base.dtsi
arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
arch/arm64/boot/dts/broadcom/Makefile
arch/arm64/boot/dts/broadcom/bcm2835-rpi.dtsi [deleted symlink]
arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
arch/arm64/boot/dts/broadcom/bcm2837.dtsi [deleted file]
arch/arm64/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi [deleted symlink]
arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi [deleted symlink]
arch/arm64/boot/dts/broadcom/bcm283x.dtsi [deleted symlink]
arch/arm64/boot/dts/broadcom/northstar2/Makefile [new file with mode: 0644]
arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts [new file with mode: 0644]
arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts [new file with mode: 0644]
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/broadcom/ns2-clock.dtsi [deleted file]
arch/arm64/boot/dts/broadcom/ns2-svk.dts [deleted file]
arch/arm64/boot/dts/broadcom/ns2-xmc.dts [deleted file]
arch/arm64/boot/dts/broadcom/ns2.dtsi [deleted file]
arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
arch/arm64/boot/dts/exynos/exynos5433.dtsi
arch/arm64/boot/dts/exynos/exynos7-espresso.dts
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
arch/arm64/boot/dts/hisilicon/hip07-d05.dts
arch/arm64/boot/dts/hisilicon/hip07.dtsi
arch/arm64/boot/dts/marvell/Makefile
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
arch/arm64/boot/dts/marvell/armada-7040-db.dts
arch/arm64/boot/dts/marvell/armada-8040-db.dts
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
arch/arm64/boot/dts/marvell/armada-8080-db.dts [new file with mode: 0644]
arch/arm64/boot/dts/marvell/armada-8080.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
arch/arm64/boot/dts/mediatek/Makefile
arch/arm64/boot/dts/mediatek/mt2712-evb.dts [new file with mode: 0644]
arch/arm64/boot/dts/mediatek/mt2712e.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/mediatek/mt6797.dtsi
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts [new file with mode: 0644]
arch/arm64/boot/dts/mediatek/mt7622.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/qcom/Makefile
arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts [new file with mode: 0644]
arch/arm64/boot/dts/qcom/ipq8074.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/qcom/msm8916.dtsi
arch/arm64/boot/dts/qcom/msm8996.dtsi
arch/arm64/boot/dts/qcom/pmi8994.dtsi
arch/arm64/boot/dts/renesas/Makefile
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
arch/arm64/boot/dts/renesas/r8a7795.dtsi
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
arch/arm64/boot/dts/renesas/r8a7796.dtsi
arch/arm64/boot/dts/renesas/r8a77995-draak.dts [new file with mode: 0644]
arch/arm64/boot/dts/renesas/r8a77995.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/renesas/salvator-common.dtsi
arch/arm64/boot/dts/renesas/salvator-xs.dtsi
arch/arm64/boot/dts/renesas/ulcb.dtsi
arch/arm64/boot/dts/rockchip/Makefile
arch/arm64/boot/dts/rockchip/rk3328-evb.dts
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts [new file with mode: 0644]
arch/arm64/boot/dts/rockchip/rk3328.dtsi
arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
arch/arm64/boot/dts/rockchip/rk3368-r88.dts
arch/arm64/boot/dts/rockchip/rk3368.dtsi
arch/arm64/boot/dts/rockchip/rk3399-evb.dts
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts [new file with mode: 0644]
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts [new file with mode: 0644]
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/rockchip/rk3399.dtsi
arch/arm64/boot/dts/socionext/Makefile
arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi [changed from symlink to file mode: 0644]
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts [new file with mode: 0644]
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi [changed from symlink to file mode: 0644]
arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi [changed from symlink to file mode: 0644]
arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
arch/arm64/boot/dts/zte/Makefile
arch/arm64/boot/dts/zte/zx296718-evb.dts
arch/arm64/boot/dts/zte/zx296718-pcbox.dts [new file with mode: 0644]
arch/arm64/boot/dts/zte/zx296718.dtsi
arch/arm64/configs/defconfig
arch/m68k/coldfire/clk.c
arch/m68k/coldfire/m5441x.c
arch/m68k/include/asm/page.h
arch/sparc/configs/sparc64_defconfig
arch/sparc/include/asm/hugetlb.h
arch/sparc/include/asm/hypervisor.h
arch/sparc/include/asm/page_64.h
arch/sparc/include/asm/pgtable_64.h
arch/sparc/include/asm/smp_64.h
arch/sparc/include/asm/trap_block.h
arch/sparc/include/asm/tsb.h
arch/sparc/include/asm/vio.h
arch/sparc/kernel/etrap_64.S
arch/sparc/kernel/head_64.S
arch/sparc/kernel/hvapi.c
arch/sparc/kernel/hvcalls.S
arch/sparc/kernel/ldc.c
arch/sparc/kernel/leon_pci_grpci1.c
arch/sparc/kernel/leon_pci_grpci2.c
arch/sparc/kernel/process_64.c
arch/sparc/kernel/rtrap_64.S
arch/sparc/kernel/setup_64.c
arch/sparc/kernel/smp_64.c
arch/sparc/kernel/traps_64.c
arch/sparc/kernel/tsb.S
arch/sparc/kernel/vio.c
arch/sparc/kernel/viohs.c
arch/sparc/kernel/vmlinux.lds.S
arch/sparc/lib/M7copy_from_user.S [new file with mode: 0644]
arch/sparc/lib/M7copy_to_user.S [new file with mode: 0644]
arch/sparc/lib/M7memcpy.S [new file with mode: 0644]
arch/sparc/lib/M7memset.S [new file with mode: 0644]
arch/sparc/lib/M7patch.S [new file with mode: 0644]
arch/sparc/lib/Makefile
arch/sparc/lib/Memcpy_utils.S [new file with mode: 0644]
arch/sparc/lib/NG4memcpy.S
arch/sparc/lib/U3memcpy.S
arch/sparc/mm/gup.c
arch/sparc/mm/hugetlbpage.c
arch/sparc/mm/init_64.c
arch/x86/mm/tlb.c
drivers/base/firmware_class.c
drivers/bus/Kconfig
drivers/bus/arm-cci.c
drivers/bus/imx-weim.c
drivers/bus/omap-ocp2scp.c
drivers/bus/sunxi-rsb.c
drivers/clk/meson/gxbb.c
drivers/clk/meson/gxbb.h
drivers/clk/meson/meson8b.c
drivers/clk/meson/meson8b.h
drivers/firmware/arm_scpi.c
drivers/firmware/psci.c
drivers/firmware/tegra/bpmp.c
drivers/memory/atmel-ebi.c
drivers/memory/jz4780-nemc.c
drivers/memory/mvebu-devbus.c
drivers/memory/omap-gpmc.c
drivers/reset/Kconfig
drivers/reset/Makefile
drivers/reset/core.c
drivers/reset/reset-gemini.c [deleted file]
drivers/reset/reset-hsdk-v1.c [new file with mode: 0644]
drivers/reset/reset-sunxi.c
drivers/reset/reset-uniphier.c
drivers/reset/reset-zx2967.c
drivers/soc/Kconfig
drivers/soc/Makefile
drivers/soc/amlogic/Kconfig [new file with mode: 0644]
drivers/soc/amlogic/Makefile [new file with mode: 0644]
drivers/soc/amlogic/meson-gx-socinfo.c [new file with mode: 0644]
drivers/soc/fsl/qbman/bman_ccsr.c
drivers/soc/fsl/qbman/bman_portal.c
drivers/soc/fsl/qbman/qman_ccsr.c
drivers/soc/fsl/qbman/qman_portal.c
drivers/soc/fsl/qe/gpio.c
drivers/soc/mediatek/mtk-pmic-wrap.c
drivers/soc/mediatek/mtk-scpsys.c
drivers/soc/qcom/Kconfig
drivers/soc/qcom/mdt_loader.c
drivers/soc/qcom/smsm.c
drivers/soc/qcom/wcnss_ctrl.c
drivers/soc/renesas/Kconfig
drivers/soc/renesas/Makefile
drivers/soc/renesas/r8a77995-sysc.c [new file with mode: 0644]
drivers/soc/renesas/rcar-rst.c
drivers/soc/renesas/rcar-sysc.c
drivers/soc/renesas/rcar-sysc.h
drivers/soc/renesas/renesas-soc.c
drivers/soc/rockchip/grf.c
drivers/soc/rockchip/pm_domains.c
drivers/soc/samsung/pm_domains.c
drivers/soc/sunxi/sunxi_sram.c
drivers/soc/tegra/Kconfig
drivers/soc/tegra/fuse/fuse-tegra.c
drivers/soc/tegra/pmc.c
drivers/soc/versatile/soc-realview.c
drivers/tee/optee/core.c
drivers/tee/optee/optee_smc.h
drivers/tee/optee/rpc.c
drivers/tee/tee_core.c
drivers/tee/tee_shm.c
drivers/tty/Kconfig
drivers/tty/Makefile
drivers/tty/vcc.c [new file with mode: 0644]
include/dt-bindings/clock/gxbb-aoclkc.h
include/dt-bindings/clock/gxbb-clkc.h
include/dt-bindings/clock/meson8b-clkc.h
include/dt-bindings/clock/rv1108-cru.h
include/dt-bindings/genpd/k2g.h [deleted file]
include/dt-bindings/pinctrl/dra.h
include/dt-bindings/power/mt7622-power.h [new file with mode: 0644]
include/dt-bindings/power/r8a77995-sysc.h [new file with mode: 0644]
include/dt-bindings/power/rk3366-power.h [new file with mode: 0644]
include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h [new file with mode: 0644]
include/dt-bindings/reset/snps,hsdk-v1-reset.h [new file with mode: 0644]
include/linux/platform_data/hsmmc-omap.h
include/linux/reset.h
include/linux/soc/mediatek/infracfg.h
include/linux/tee_drv.h
include/soc/tegra/fuse.h
include/uapi/linux/tee.h

index 0fff40a6330dd851f76424b88b4e116567f11b9e..4e4bc0bae597ad27b488a74c7b83762e7cb51a88 100644 (file)
@@ -1,6 +1,18 @@
 Amlogic MesonX device tree bindings
 -------------------------------------------
 
+Work in progress statement:
+
+Device tree files and bindings applying to Amlogic SoCs and boards are
+considered "unstable". Any Amlogic device tree binding may change at
+any time. Be sure to use a device tree binary and a kernel image
+generated from the same source tree.
+
+Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
+stable binding/ABI.
+
+---------------------------------------------------------------
+
 Boards with the Amlogic Meson6 SoC shall have the following properties:
   Required root node property:
     compatible: "amlogic,meson6"
@@ -61,3 +73,32 @@ Board compatible values (alphabetically, grouped by SoC):
   - "amlogic,q201" (Meson gxm s912)
   - "kingnovel,r-box-pro" (Meson gxm S912)
   - "nexbox,a1" (Meson gxm s912)
+
+Amlogic Meson Firmware registers Interface
+------------------------------------------
+
+The Meson SoCs have a register bank with status and data shared with the
+secure firmware.
+
+Required properties:
+ - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
+
+Properties should indentify components of this register interface :
+
+Meson GX SoC Information
+------------------------
+A firmware register encodes the SoC type, package and revision information on
+the Meson GX SoCs.
+If present, the following property should be added :
+
+Optional properties:
+  - amlogic,has-chip-id: If present, the interface gives the current SoC version.
+
+Example
+-------
+
+ao-secure@140 {
+       compatible = "amlogic,meson-gx-ao-secure", "syscon";
+       reg = <0x0 0x140 0x0 0x140>;
+       amlogic,has-chip-id;
+};
index 9c97de23919ae4312c3c42085393baf2536a727d..3e3efa046ac57ab49cee7d706cfff3b2d93c6247 100644 (file)
@@ -42,6 +42,10 @@ Raspberry Pi Zero
 Required root node properties:
 compatible = "raspberrypi,model-zero", "brcm,bcm2835";
 
+Raspberry Pi Zero W
+Required root node properties:
+compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
+
 Generic BCM2835 board
 Required root node properties:
 compatible = "brcm,bcm2835";
diff --git a/Documentation/devicetree/bindings/arm/bhf.txt b/Documentation/devicetree/bindings/arm/bhf.txt
new file mode 100644 (file)
index 0000000..886b503
--- /dev/null
@@ -0,0 +1,6 @@
+Beckhoff Automation Platforms Device Tree Bindings
+--------------------------------------------------
+
+CX9020 Embedded PC
+Required root node properties:
+    - compatible = "bhf,cx9020", "fsl,imx53";
index a44253cad2692e2c209e4fa1f148ccd89415496c..b92f12bd5244a7e6fe911f8000f7a37e499e0e40 100644 (file)
@@ -200,6 +200,7 @@ described below.
                            "arm,realview-smp"
                            "brcm,bcm11351-cpu-method"
                            "brcm,bcm23550"
+                           "brcm,bcm2836-smp"
                            "brcm,bcm-nsp-smp"
                            "brcm,brahma-b15"
                            "marvell,armada-375-smp"
diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-8kp.txt
new file mode 100644 (file)
index 0000000..f3e9624
--- /dev/null
@@ -0,0 +1,15 @@
+Marvell Armada 8KPlus Platforms Device Tree Bindings
+----------------------------------------------------
+
+Boards using a SoC of the Marvell Armada 8KP families must carry
+the following root node property:
+
+ - compatible, with one of the following values:
+
+   - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810"
+     when the SoC being used is the Armada 8080
+
+Example:
+
+compatible = "marvell,armada-8080-db", "marvell,armada-8080",
+            "marvell,armada-ap810-octa", "marvell,armada-ap810"
index da7bd138e6f2133bb43107e8b3cb8885f9791cb7..91d5178494834b57e2abe152bf5739a8930c0cd2 100644 (file)
@@ -1,12 +1,12 @@
-MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
+MediaTek SoC based Platforms Device Tree Bindings
 
-Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
-following property:
+Boards with a MediaTek SoC shall have the following property:
 
 Required root node property:
 
 compatible: Must contain one of
    "mediatek,mt2701"
+   "mediatek,mt2712"
    "mediatek,mt6580"
    "mediatek,mt6589"
    "mediatek,mt6592"
@@ -14,7 +14,8 @@ compatible: Must contain one of
    "mediatek,mt6795"
    "mediatek,mt6797"
    "mediatek,mt7622"
-   "mediatek,mt7623"
+   "mediatek,mt7623" which is referred to MT7623N SoC
+   "mediatek,mt7623a"
    "mediatek,mt8127"
    "mediatek,mt8135"
    "mediatek,mt8173"
@@ -25,6 +26,9 @@ Supported boards:
 - Evaluation board for MT2701:
     Required root node properties:
       - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+    Required root node properties:
+      - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
     Required root node properties:
       - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
@@ -46,9 +50,11 @@ Supported boards:
 - Reference board variant 1 for MT7622:
     Required root node properties:
       - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
-- Evaluation board for MT7623:
+- Reference  board for MT7623n with NAND:
     Required root node properties:
-      - compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
+      - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
+- Bananapi BPI-R2 board:
+      - compatible = "bananapi,bpi-r2", "mediatek,mt7623";
 - MTK mt8127 tablet moose EVB:
     Required root node properties:
       - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
index 8219b2c6bb29ab6862a65dd4adeae9d0b3aeafd9..2ecc712bf7075da21bd29104024a9c0fc15186f6 100644 (file)
@@ -80,6 +80,9 @@ SoCs:
 - OMAP5432
   compatible = "ti,omap5432", "ti,omap5"
 
+- DRA762
+  compatible = "ti,dra762", "ti,dra7"
+
 - DRA742
   compatible = "ti,dra742", "ti,dra74", "ti,dra7"
 
@@ -154,6 +157,9 @@ Boards:
 - AM335X phyCORE-AM335x: Development kit
   compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
 
+- AM335X UC-8100-ME-T: Communication-centric industrial computing platform
+  compatible = "moxa,uc-8100-me-t", "ti,am33xx";
+
 - OMAP5 EVM : Evaluation Module
   compatible = "ti,omap5-evm", "ti,omap5"
 
@@ -184,6 +190,9 @@ Boards:
 - AM5718 IDK
   compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"
 
+- DRA762 EVM:  Software Development Board for DRA762
+  compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"
+
 - DRA742 EVM:  Software Development Board for DRA742
   compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
 
index 028d16e721862effcf95ee4e9055856255e99879..0ed4d39d7fe1876ec439a713576dfc4bf8d18518 100644 (file)
@@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings:
        msm8994
        msm8996
        mdm9615
+       ipq8074
 
 The 'board' element must be one of the following strings:
 
@@ -33,6 +34,7 @@ The 'board' element must be one of the following strings:
        dragonboard
        mtp
        sbc
+       hk01
 
 The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
 where the minor number may be omitted when it's zero, i.e.  v1.0 is the same
index 11c0ac4a2d56686d04bd969c44ea3c9c7efeabe2..b003148e2945129ef834feacb5b198813195484e 100644 (file)
@@ -134,6 +134,10 @@ Rockchip platforms device tree bindings
     Required root node properties:
      - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
 
+- Pine64 Rock64 board:
+    Required root node properties:
+    - compatible = "pine64,rock64", "rockchip,rk3328";
+
 - Rockchip PX3 Evaluation board:
     Required root node properties:
       - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
@@ -173,6 +177,14 @@ Rockchip platforms device tree bindings
     Required root node properties:
       - compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
 
+- Rockchip RK3399 Sapphire Excavator board:
+    Required root node properties:
+      - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
+
+- Theobroma Systems RK3399-Q7 Haikou Baseboard:
+    Required root node properties:
+      - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
+
 - Tronsmart Orion R68 Meta
     Required root node properties:
       - compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
index 1a671e3298643d9eaaec617b2b6183f77b380bed..ae75cb3b1331f82782c95a814d3a6bbda3f63857 100644 (file)
@@ -39,6 +39,8 @@ SoCs:
     compatible = "renesas,r8a7795"
   - R-Car M3-W (R8A77960)
     compatible = "renesas,r8a7796"
+  - R-Car D3 (R8A77995)
+    compatible = "renesas,r8a77995"
 
 
 Boards:
@@ -53,6 +55,8 @@ Boards:
     compatible = "renesas,blanche", "renesas,r8a7792"
   - BOCK-W
     compatible = "renesas,bockw", "renesas,r8a7778"
+  - Draak (RTP0RC77995SEB0010S)
+    compatible = "renesas,draak", "renesas,r8a77995"
   - Genmai (RTK772100BC00000BR)
     compatible = "renesas,genmai", "renesas,r7s72100"
   - GR-Peach (X28A-M01-E/F)
@@ -64,6 +68,10 @@ Boards:
     compatible = "renesas,h3ulcb", "renesas,r8a7795";
   - Henninger
     compatible = "renesas,henninger", "renesas,r8a7791"
+  - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
+    compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
+  - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
+    compatible = "iwave,g22m", "renesas,r8a7745"
   - iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
     compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
   - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
index 207682647d33a41fd6bbee805dfebe2e8b04ef83..b455c5aa9139edba0223ba9c25270255b60a0d86 100644 (file)
@@ -16,18 +16,25 @@ Required Properties:
           mapped region.
 
 - #clock-cells: should be 1.
+- #reset-cells: should be 1.
 
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
 used in device tree sources.
 
+Similarly a preprocessor macro for each reset line is defined in
+dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
+device tree sources).
+
+
 Example: Clock controller node:
 
        clkc: clock-controller@c1104000 {
-               #clock-cells = <1>;
                compatible = "amlogic,meson8b-clkc";
                reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
        };
 
 
index cb7ffc58c564722a04e18c562e83155c2a051a57..b1a8929c2536cc324a1d34073dabc2fe2ddf53cf 100644 (file)
@@ -13,6 +13,7 @@ Required properties:
 
 - compatible : Shall contain one or more of
   - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
+  - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
   - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
 
     When compatible with generic versions, nodes must list the SoC-specific
index c6cb96a4fa939a5672b4770ba7f8673136cb0031..4bbd1e9bf3be40ee158be1e62a9be15167cec57c 100644 (file)
@@ -36,8 +36,10 @@ Required Properties:
       When supplied they must be named "dclkin.x" with "x" being the input
       clock numerical index.
 
-  - vsps: A list of phandles to the VSP nodes that handle the memory
-    interfaces for the DU channels.
+  - vsps: A list of phandle and channel index tuples to the VSPs that handle
+    the memory interfaces for the DU channels. The phandle identifies the VSP
+    instance that serves the DU channel, and the channel index identifies the
+    LIF instance in that VSP.
 
 Required nodes:
 
@@ -59,24 +61,24 @@ corresponding to each DU output.
  R8A7796 (M3-W)        DPAD            HDMI            LVDS            -
 
 
-Example: R8A7790 (R-Car H2) DU
+Example: R8A7795 (R-Car H3) ES2.0 DU
 
-       du: du@feb00000 {
-               compatible = "renesas,du-r8a7790";
-               reg = <0 0xfeb00000 0 0x70000>,
-                     <0 0xfeb90000 0 0x1c>,
-                     <0 0xfeb94000 0 0x1c>;
-               reg-names = "du", "lvds.0", "lvds.1";
-               interrupt-parent = <&gic>;
-               interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
-                            <0 268 IRQ_TYPE_LEVEL_HIGH>,
-                            <0 269 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&mstp7_clks R8A7790_CLK_DU0>,
-                        <&mstp7_clks R8A7790_CLK_DU1>,
-                        <&mstp7_clks R8A7790_CLK_DU2>,
-                        <&mstp7_clks R8A7790_CLK_LVDS0>,
-                        <&mstp7_clks R8A7790_CLK_LVDS1>;
-               clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+       du: display@feb00000 {
+               compatible = "renesas,du-r8a7795";
+               reg = <0 0xfeb00000 0 0x80000>,
+                     <0 0xfeb90000 0 0x14>;
+               reg-names = "du", "lvds.0";
+               interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 724>,
+                        <&cpg CPG_MOD 723>,
+                        <&cpg CPG_MOD 722>,
+                        <&cpg CPG_MOD 721>,
+                        <&cpg CPG_MOD 727>;
+               clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+               vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
 
                ports {
                        #address-cells = <1>;
@@ -89,12 +91,19 @@ Example: R8A7790 (R-Car H2) DU
                        };
                        port@1 {
                                reg = <1>;
-                               du_out_lvds0: endpoint {
+                               du_out_hdmi0: endpoint {
+                                       remote-endpoint = <&dw_hdmi0_in>;
                                };
                        };
                        port@2 {
                                reg = <2>;
-                               du_out_lvds1: endpoint {
+                               du_out_hdmi1: endpoint {
+                                       remote-endpoint = <&dw_hdmi1_in>;
+                               };
+                       };
+                       port@3 {
+                               reg = <3>;
+                               du_out_lvds0: endpoint {
                                };
                        };
                };
index 33d9e386dc45c457de837fe8d7209b4302d54003..41f0c1a07c562b754fd2324d7a41d9cb6df52158 100644 (file)
@@ -9,7 +9,12 @@ execute the actual DMA tansfer.
 eDMA3 Channel Controller
 
 Required properties:
-- compatible:  "ti,edma3-tpcc" for the channel controller(s)
+--------------------
+- compatible:  Should be:
+               - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
+                 AM33xx and AM43xx SoCs.
+               - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
+                 channel controller(s) on 66AK2G.
 - #dma-cells:  Should be set to <2>. The first number is the DMA request
                number and the second is the TC the channel is serviced on.
 - reg:         Memory map of eDMA CC
@@ -19,8 +24,19 @@ Required properties:
 - ti,tptcs:    List of TPTCs associated with the eDMA in the following form:
                <&tptc_phandle TC_priority_number>. The highest priority is 0.
 
+SoC-specific Required properties:
+--------------------------------
+The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
+- ti,hwmods:   Name of the hwmods associated to the eDMA CC.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+               and an args specifier containing the device id
+               value. This property is as per the binding,
+               Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+
 Optional properties:
-- ti,hwmods:   Name of the hwmods associated to the eDMA CC
+-------------------
 - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
                these channels will be SW triggered channels. See example.
 - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
@@ -31,17 +47,34 @@ Optional properties:
 eDMA3 Transfer Controller
 
 Required properties:
-- compatible:  "ti,edma3-tptc" for the transfer controller(s)
+--------------------
+- compatible:  Should be:
+               - "ti,edma3-tptc" for the transfer controller(s) on OMAP,
+                 AM33xx and AM43xx SoCs.
+               - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
+                 transfer controller(s) on 66AK2G.
 - reg:         Memory map of eDMA TC
 - interrupts:  Interrupt number for TCerrint.
 
+SoC-specific Required properties:
+--------------------------------
+The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
+- ti,hwmods:   Name of the hwmods associated to the eDMA TC.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+               and an args specifier containing the device id
+               value. This property is as per the binding,
+               Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+
 Optional properties:
-- ti,hwmods:   Name of the hwmods associated to the given eDMA TC
+-------------------
 - interrupt-names: "edma3_tcerrint"
 
 ------------------------------------------------------------------------------
-Example:
+Examples:
 
+1.
 edma: edma@49000000 {
        compatible = "ti,edma3-tpcc";
        ti,hwmods = "tpcc";
@@ -108,6 +141,58 @@ mcasp0: mcasp@48038000 {
        dma-names = "tx", "rx";
 };
 
+2.
+edma1: edma@02728000 {
+       compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
+       reg =   <0x02728000 0x8000>;
+       reg-names = "edma3_cc";
+       interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+                       <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
+                       <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
+       interrupt-names = "edma3_ccint", "emda3_mperr",
+                         "edma3_ccerrint";
+       dma-requests = <64>;
+       #dma-cells = <2>;
+
+       ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
+
+       /*
+        * memcpy is disabled, can be enabled with:
+        * ti,edma-memcpy-channels = <12 13 14 15>;
+        * for example.
+        */
+
+       power-domains = <&k2g_pds 0x4f>;
+};
+
+edma1_tptc0: tptc@027b0000 {
+       compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
+       reg =   <0x027b0000 0x400>;
+       power-domains = <&k2g_pds 0x4f>;
+};
+
+edma1_tptc1: tptc@027b8000 {
+       compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc";
+       reg =   <0x027b8000 0x400>;
+       power-domains = <&k2g_pds 0x4f>;
+};
+
+mmc0: mmc@23000000 {
+       compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
+       reg = <0x23000000 0x400>;
+       interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
+       dmas = <&edma1 24 0>, <&edma1 25 0>;
+       dma-names = "tx", "rx";
+       bus-width = <4>;
+       ti,needs-special-reset;
+       no-1-8-v;
+       max-frequency = <96000000>;
+       power-domains = <&k2g_pds 0xb>;
+       clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
+       clock-names = "fck", "mmchsdb_fck";
+       status = "disabled";
+};
+
 ------------------------------------------------------------------------------
 DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
 binding.
index 5aa5926029ee7286c4cd2e41a446574c13102021..039219df05c5f69836a39bac48bac64ce33d476a 100644 (file)
@@ -17,6 +17,7 @@ Required properties:
   * which must be preceded by one of the following vendor specifics:
     + "amlogic,meson-gxm-mali"
     + "rockchip,rk3288-mali"
+    + "rockchip,rk3399-mali"
 
 - reg : Physical base address of the device and length of the register area.
 
index 11cc87aeb276f0a25b869ba53ed2b6b9213888d8..07bf0b9a5139fed3d5297d495bab184111deb9f9 100644 (file)
@@ -17,6 +17,7 @@ Required properties:
        "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
        "mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
        "mediatek,mt6577-sysirq": for MT6577
+       "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
        "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
index 0e026c151c1c1a1aa3191129658dc5788f2ed4f2..3a4ac401e6f93a9d8ce3becd4d75410f95f1e50d 100644 (file)
@@ -1,33 +1,55 @@
-* TI Highspeed MMC host controller for OMAP
+* TI Highspeed MMC host controller for OMAP and 66AK2G family.
 
-The Highspeed MMC Host Controller on TI OMAP family
+The Highspeed MMC Host Controller on TI OMAP and 66AK2G family
 provides an interface for MMC, SD, and SDIO types of memory cards.
 
 This file documents differences between the core properties described
 by mmc.txt and the properties used by the omap_hsmmc driver.
 
 Required properties:
+--------------------
 - compatible:
  Should be "ti,omap2-hsmmc", for OMAP2 controllers
  Should be "ti,omap3-hsmmc", for OMAP3 controllers
  Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
  Should be "ti,omap4-hsmmc", for OMAP4 controllers
  Should be "ti,am33xx-hsmmc", for AM335x controllers
-- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
+ Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
+
+SoC specific required properties:
+---------------------------------
+The following are mandatory properties for OMAPs, AM33xx and AM43xx SoCs only:
+- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+               and an args specifier containing the MMC device id
+               value. This property is as per the binding,
+               Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+- clocks:      Must contain an entry for each entry in clock-names. Should
+               be defined as per the he appropriate clock bindings consumer
+               usage in Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+- clock-names: Shall be "fck" for the functional clock,
+               and "mmchsdb_fck" for the debounce clock.
+
 
 Optional properties:
-ti,dual-volt: boolean, supports dual voltage cards
-<supply-name>-supply: phandle to the regulator device tree node
-"supply-name" examples are "vmmc", "vmmc_aux"(deprecated)/"vqmmc" etc
-ti,non-removable: non-removable slot (like eMMC)
-ti,needs-special-reset: Requires a special softreset sequence
-ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
-dmas: List of DMA specifiers with the controller specific format
-as described in the generic DMA client binding. A tx and rx
-specifier is required.
-dma-names: List of DMA request names. These strings correspond
-1:1 with the DMA specifiers listed in dmas. The string naming is
-to be "rx" and "tx" for RX and TX DMA requests, respectively.
+--------------------
+- ti,dual-volt:                boolean, supports dual voltage cards
+- <supply-name>-supply:        phandle to the regulator device tree node
+                         "supply-name" examples are "vmmc",
+                         "vmmc_aux"(deprecated)/"vqmmc" etc
+- ti,non-removable:    non-removable slot (like eMMC)
+- ti,needs-special-reset:      Requires a special softreset sequence
+- ti,needs-special-hs-handling:        HSMMC IP needs special setting
+                                 for handling High Speed
+- dmas:                        List of DMA specifiers with the controller specific
+                       format as described in the generic DMA client
+                       binding. A tx and rx specifier is required.
+- dma-names:           List of DMA request names. These strings correspond
+                       1:1 with the DMA specifiers listed in dmas.
+                       The string naming is to be "rx" and "tx" for
+                       RX and TX DMA requests, respectively.
 
 Examples:
 
index 5a1d8b0c39e97af6d3ef56589f0196541d912a51..2d504256b0d8e73183ebe114158f194a85e964d8 100644 (file)
@@ -11,9 +11,20 @@ Required properties:
 - interrupts           : property with a value describing the interrupt
                          number
 
-Optional properties:
+The following are mandatory properties for DRA7x, AM33xx and AM43xx SoCs only:
 - ti,hwmods            : Must be "d_can<n>" or "c_can<n>", n being the
                          instance number
+
+The following are mandatory properties for Keystone 2 66AK2G SoCs only:
+- power-domains                : Should contain a phandle to a PM domain provider node
+                         and an args specifier containing the DCAN device id
+                         value. This property is as per the binding,
+                         Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+- clocks               : CAN functional clock phandle. This property is as per the
+                         binding,
+                         Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+
+Optional properties:
 - syscon-raminit       : Handle to system control region that contains the
                          RAMINIT register, register offset to the RAMINIT
                          register and the CAN instance number (0 offset).
index 1d1168b805cc8ab2e9607be5dd1068d391d89ff2..214eaa9a6683861fd529d2af6fb84e361b27d80d 100644 (file)
@@ -20,8 +20,10 @@ Required properties:
         "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
        "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
 - power-domains: phandle to the power domain that the ethernet is part of
-- resets: Should contain a phandle to the ethsys reset signal
-- reset-names: Should contain the reset signal name "eth"
+- resets: Should contain phandles to the ethsys reset signals
+- reset-names: Should contain the names of reset signal listed in the resets
+               property
+               These are "fe", "gmac" and "ppe"
 - mediatek,ethsys: phandle to the syscon node that handles the port setup
 - mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
        which is required for those SoCs equipped with SGMII such as MT7622 SoC.
index 127ae1f53e5a2d5b4da6893efc7fba898a14fd27..6173af6885f86731a9e81182737afc0a185cd212 100644 (file)
@@ -276,7 +276,7 @@ pcie-controller {
                clocks = <&gateclk 26>;
        };
 
-       pcie@10,0 {
+       pcie@a,0 {
                device_type = "pci";
                assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
                reg = <0x5000 0 0 0 0>;
index 84404c9edff73d97df9384fb0ce801343d780b0b..af21502e939c4b1f6866e80f7325342833b133c0 100644 (file)
@@ -1,12 +1,13 @@
 DT bindings for the Renesas Advanced Power Management Unit
 
-Renesas R-Car line of SoCs utilize one or more APMU hardware units
+Renesas R-Car and RZ/G1 SoCs utilize one or more APMU hardware units
 for CPU core power domain control including SMP boot and CPU Hotplug.
 
 Required properties:
 
 - compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
              Examples with soctypes are:
+               - "renesas,r8a7743-apmu" (RZ/G1M)
                - "renesas,r8a7790-apmu" (R-Car H2)
                - "renesas,r8a7791-apmu" (R-Car M2-W)
                - "renesas,r8a7792-apmu" (R-Car V2H)
index d91715bc8d52c22e7f159b6bca96f35fa5a68111..98cc8c09d02d5d857992250fd61a0199359e5933 100644 (file)
@@ -17,6 +17,7 @@ Required properties:
       - "renesas,r8a7794-sysc" (R-Car E2)
       - "renesas,r8a7795-sysc" (R-Car H3)
       - "renesas,r8a7796-sysc" (R-Car M3-W)
+      - "renesas,r8a77995-sysc" (R-Car D3)
   - reg: Address start and address range for the device.
   - #power-domain-cells: Must be 1.
 
index fe5e0f37b3c935794428cbe950e50dde3628ac89..e5a03ffe04fb2af74ed41b7aa36aee284edc437a 100644 (file)
@@ -26,6 +26,7 @@ Required properties:
                  - "renesas,r8a7794-rst" (R-Car E2)
                  - "renesas,r8a7795-rst" (R-Car H3)
                  - "renesas,r8a7796-rst" (R-Car M3-W)
+                 - "renesas,r8a77995-rst" (R-Car D3)
   - reg: Address start and address range for the device.
 
 
index 83ab0f599c4090712bb4c8bd4f52d8a5d5701947..68a6f487c4092f205eb4cae09ca962195c15c06e 100644 (file)
@@ -6,7 +6,6 @@ System reset
 
 Required properties:
 - compatible: should be one of the following:
-    "socionext,uniphier-sld3-reset" - for sLD3 SoC
     "socionext,uniphier-ld4-reset"  - for LD4 SoC
     "socionext,uniphier-pro4-reset" - for Pro4 SoC
     "socionext,uniphier-sld8-reset" - for sLD8 SoC
@@ -37,7 +36,6 @@ Media I/O (MIO) reset, SD reset
 
 Required properties:
 - compatible: should be one of the following:
-    "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC
     "socionext,uniphier-ld4-mio-reset"  - for LD4 SoC
     "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC
     "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC
@@ -92,3 +90,28 @@ Example:
 
                other nodes ...
        };
+
+
+Analog signal amplifier reset
+-----------------------------
+
+Required properties:
+- compatible: should be one of the following:
+    "socionext,uniphier-ld11-adamv-reset" - for LD11 SoC
+    "socionext,uniphier-ld20-adamv-reset" - for LD20 SoC
+- #reset-cells: should be 1.
+
+Example:
+
+       adamv@57920000 {
+               compatible = "socionext,uniphier-ld11-adamv",
+                            "simple-mfd", "syscon";
+               reg = <0x57920000 0x1000>;
+
+               adamv_rst: reset {
+                       compatible = "socionext,uniphier-ld11-adamv-reset";
+                       #reset-cells = <1>;
+               };
+
+               other nodes ...
+       };
index b6cf384597e1dabc5f5e090982235f0e0c56128a..f73abff3de43bcdb0ecdaabc0f4f23a470d7268d 100644 (file)
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
index b1d165b4d4b31104e4c137c18ad8079ff66943e9..40056f7990f86f337296fe9bc13343c5c6b2f446 100644 (file)
@@ -12,11 +12,13 @@ power/power_domain.txt. It provides the power domains defined in
 - include/dt-bindings/power/mt8173-power.h
 - include/dt-bindings/power/mt6797-power.h
 - include/dt-bindings/power/mt2701-power.h
+- include/dt-bindings/power/mt7622-power.h
 
 Required properties:
 - compatible: Should be one of:
        - "mediatek,mt2701-scpsys"
        - "mediatek,mt6797-scpsys"
+       - "mediatek,mt7622-scpsys"
        - "mediatek,mt8173-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
@@ -26,6 +28,7 @@ Required properties:
                       enabled before enabling certain power domains.
        Required clocks for MT2701: "mm", "mfg", "ethif"
        Required clocks for MT6797: "mm", "mfg", "vdec"
+       Required clocks for MT7622: "hif_sel"
        Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
 
 Optional properties:
index cc9f05d3cbc1a0b08a2a278364332b8114b027a3..7dc5ce858a0ee3a6659cc0be7a0d3194f7a6fa3e 100644 (file)
@@ -21,6 +21,7 @@ Required Properties:
    - "rockchip,rk3328-grf", "syscon": for rk3328
    - "rockchip,rk3368-grf", "syscon": for rk3368
    - "rockchip,rk3399-grf", "syscon": for rk3399
+   - "rockchip,rv1108-grf", "syscon": for rv1108
 - compatible: PMUGRF should be one of the following:
    - "rockchip,rk3368-pmugrf", "syscon": for rk3368
    - "rockchip,rk3399-pmugrf", "syscon": for rk3399
@@ -28,6 +29,8 @@ Required Properties:
    - "rockchip,rk3288-sgrf", "syscon": for rk3288
 - compatible: USB2PHYGRF should be one of the followings
    - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
+- compatible: USBGRF should be one of the following
+   - "rockchip,rv1108-usbgrf", "syscon": for rv1108
 - reg: physical base address of the controller and length of memory mapped
   region.
 
index 01bfb6745fbd79d77251392beb719d22fe73aef2..301d2a9bc1b8bb2ab0e213e6656b03691c2c71e8 100644 (file)
@@ -7,6 +7,7 @@ Required properties for power domain controller:
 - compatible: Should be one of the following.
        "rockchip,rk3288-power-controller" - for RK3288 SoCs.
        "rockchip,rk3328-power-controller" - for RK3328 SoCs.
+       "rockchip,rk3366-power-controller" - for RK3366 SoCs.
        "rockchip,rk3368-power-controller" - for RK3368 SoCs.
        "rockchip,rk3399-power-controller" - for RK3399 SoCs.
 - #power-domain-cells: Number of cells in a power-domain specifier.
@@ -18,6 +19,7 @@ Required properties for power domain sub nodes:
 - reg: index of the power domain, should use macros in:
        "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
        "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain.
+       "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain.
        "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain.
        "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain.
 - clocks (optional): phandles to clocks which need to be enabled while power domain
@@ -93,6 +95,7 @@ power domain to use.
 The index should use macros in:
        "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
        "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain.
+       "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain.
        "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain.
        "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain.
 
index c705db07d8206d74835c729cf6253d97a7227df0..66e6265fb0aa2f2af147c63a776c86bb9a52096f 100644 (file)
@@ -46,12 +46,13 @@ Required Properties:
 - power-domains: phandle pointing to the corresponding PM domain node
                 and an ID representing the device.
 
-See dt-bindings/genpd/k2g.h for the list of valid identifiers for k2g.
+See http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data for the list
+of valid identifiers for k2g.
 
 Example (K2G):
 --------------------
        uart0: serial@02530c00 {
                compatible = "ns16550a";
                ...
-               power-domains = <&k2g_pds K2G_DEV_UART0>;
+               power-domains = <&k2g_pds 0x002c>;
        };
diff --git a/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt b/Documentation/devicetree/bindings/sram/renesas,smp-sram.txt
new file mode 100644 (file)
index 0000000..712d05e
--- /dev/null
@@ -0,0 +1,27 @@
+* Renesas SMP SRAM
+
+Renesas R-Car Gen2 and RZ/G1 SoCs need a small piece of SRAM for the jump stub
+for secondary CPU bringup and CPU hotplug.
+This memory is reserved by adding a child node to a "mmio-sram" node, cfr.
+Documentation/devicetree/bindings/sram/sram.txt.
+
+Required child node properties:
+  - compatible: Must be "renesas,smp-sram",
+  - reg: Address and length of the reserved SRAM.
+    The full physical (bus) address must be aligned to a 256 KiB boundary.
+
+
+Example:
+
+       icram1: sram@e63c0000 {
+               compatible = "mmio-sram";
+               reg = <0 0xe63c0000 0 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0 0xe63c0000 0x1000>;
+
+               smp-sram@0 {
+                       compatible = "renesas,smp-sram";
+                       reg = <0 0x10>;
+               };
+       };
index 170034e6c8b0e3927f5a4d8b41b3b8cc1ba8ec36..6bb92a1df753e5ae7b74f17b435a511210acbe19 100644 (file)
@@ -9,7 +9,9 @@ Controller Node
 ---------------
 
 Required properties:
-- compatible : "allwinner,sun4i-a10-sram-controller"
+- compatible : should be:
+    - "allwinner,sun4i-a10-sram-controller"
+    - "allwinner,sun50i-a64-sram-controller"
 - reg : sram controller register offset + length
 
 SRAM nodes
@@ -22,10 +24,13 @@ Each SRAM will have SRAM sections that are going to be handled by the
 SRAM controller as subnodes. These sections are represented following
 once again the representation described in the mmio-sram binding.
 
-The valid sections compatible are:
+The valid sections compatible for A10 are:
     - allwinner,sun4i-a10-sram-a3-a4
     - allwinner,sun4i-a10-sram-d
 
+The valid sections compatible for A64 are:
+    - allwinner,sun50i-a64-sram-c
+
 Devices using SRAM sections
 ---------------------------
 
index 5a79aeb620b3a206434bd45bf2410a7ed47db7cb..69183f0fbc7873f13e9b4516a34e3dde41686ab7 100644 (file)
@@ -48,6 +48,7 @@ avic  Shanghai AVIC Optoelectronics Co., Ltd.
 axentia        Axentia Technologies AB
 axis   Axis Communications AB
 bananapi BIPAI KEJI LIMITED
+bhf    Beckhoff Automation GmbH & Co. KG
 boe    BOE Technology Group Co., Ltd.
 bosch  Bosch Sensortec GmbH
 boundary       Boundary Devices Inc.
index 6a00939a059a1185c5e4ece5bbcd388131bb4987..20ada673ab0c17a1647be7eeb80353aedea64ceb 100644 (file)
@@ -3,9 +3,9 @@ Mediatek SoCs Watchdog timer
 Required properties:
 
 - compatible should contain:
-       * "mediatek,mt2701-wdt" for MT2701 compatible watchdog timers
-       * "mediatek,mt6589-wdt" for all compatible watchdog timers (MT2701,
-               MT6589)
+       "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
+       "mediatek,mt6589-wdt": for MT6589
+       "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
 
 - reg : Specifies base physical address and size of the registers.
 
index 1c2c4967cd4336046efa56d78a88d9c03b570661..cc0aea88082441a0a6625b76cf0012c8103a4137 100644 (file)
@@ -44,17 +44,6 @@ request_firmware_nowait
 .. kernel-doc:: drivers/base/firmware_class.c
    :functions: request_firmware_nowait
 
-Considerations for suspend and resume
-=====================================
-
-During suspend and resume only the built-in firmware and the firmware cache
-elements of the firmware API can be used. This is managed by fw_pm_notify().
-
-fw_pm_notify
-------------
-.. kernel-doc:: drivers/base/firmware_class.c
-   :functions: fw_pm_notify
-
 request firmware API expected driver use
 ========================================
 
index a3231bd6541d783d4b2220b9b2099095f881713e..fbb269415f0672c408558289ec5c4a5d5cdafcc5 100644 (file)
@@ -2101,17 +2101,38 @@ F:      arch/arm/mach-pxa/include/mach/z2.h
 ARM/ZTE ARCHITECTURE
 M:     Jun Nie <jun.nie@linaro.org>
 M:     Baoyou Xie <baoyou.xie@linaro.org>
+M:     Shawn Guo <shawnguo@kernel.org>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:     Maintained
+F:     arch/arm/boot/dts/zx2967*
 F:     arch/arm/mach-zx/
+F:     arch/arm64/boot/dts/zte/
 F:     drivers/clk/zte/
+F:     drivers/dma/zx_dma.c
+F:     drivers/gpio/gpio-zx.c
+F:     drivers/i2c/busses/i2c-zx2967.c
+F:     drivers/mmc/host/dw_mmc-zx.*
+F:     drivers/pinctrl/zte/
 F:     drivers/reset/reset-zx2967.c
 F:     drivers/soc/zte/
+F:     drivers/thermal/zx2967_thermal.c
+F:     drivers/watchdog/zx2967_wdt.c
 F:     Documentation/devicetree/bindings/arm/zte.txt
-F:     Documentation/devicetree/bindings/clock/zx296702-clk.txt
+F:     Documentation/devicetree/bindings/clock/zx2967*.txt
+F:     Documentation/devicetree/bindings/dma/zxdma.txt
+F:     Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
+F:     Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
+F:     Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
+F:     Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
 F:     Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
 F:     Documentation/devicetree/bindings/soc/zte/
-F:     include/dt-bindings/soc/zx*.h
+F:     Documentation/devicetree/bindings/sound/zte,*.txt
+F:     Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
+F:     Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
+F:     include/dt-bindings/clock/zx2967*.h
+F:     include/dt-bindings/soc/zte,*.h
+F:     sound/soc/codecs/zx_aud96p22.c
+F:     sound/soc/zte/
 
 ARM/ZYNQ ARCHITECTURE
 M:     Michal Simek <michal.simek@xilinx.com>
@@ -3175,6 +3196,7 @@ S:        Supported
 F:     drivers/crypto/cavium/cpt/
 
 CAVIUM THUNDERX2 ARM64 SOC
+M:     Robert Richter <rrichter@cavium.com>
 M:     Jayachandran C <jnair@caviumnetworks.com>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:     Maintained
@@ -12489,6 +12511,7 @@ F:      drivers/tty/serial/sunsab.h
 F:     drivers/tty/serial/sunsu.c
 F:     drivers/tty/serial/sunzilog.c
 F:     drivers/tty/serial/sunzilog.h
+F:     drivers/tty/vcc.c
 
 SPARSE CHECKER
 M:     "Christopher Li" <sparse@chrisli.org>
@@ -12844,6 +12867,13 @@ L:     linux-mmc@vger.kernel.org
 S:     Maintained
 F:     drivers/mmc/host/dw_mmc*
 
+SYNOPSYS HSDK RESET CONTROLLER DRIVER
+M:     Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S:     Supported
+F:     drivers/reset/reset-hsdk-v1.c
+F:     include/dt-bindings/reset/snps,hsdk-v1-reset.h
+F:     Documentation/devicetree/bindings/reset/snps,hsdk-v1-reset.txt
+
 SYSTEM CONFIGURATION (SYSCON)
 M:     Lee Jones <lee.jones@linaro.org>
 M:     Arnd Bergmann <arnd@arndb.de>
index 447629d89884fd1ed600227a676b339fd9c256e1..6dcea8e8e941eabe79790f97e3e8f69ccd3220e9 100644 (file)
@@ -646,7 +646,7 @@ choice
        config DEBUG_OMAP2UART1
                bool "OMAP2/3/4 UART1 (omap2/3 sdp boards and some omap3 boards)"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
                help
                  This covers at least h4, 2430sdp, 3430sdp, 3630sdp,
                  omap3 torpedo and 3530 lv som.
@@ -654,17 +654,17 @@ choice
        config DEBUG_OMAP2UART2
                bool "Kernel low-level debugging messages via OMAP2/3/4 UART2"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
 
        config DEBUG_OMAP2UART3
                bool "Kernel low-level debugging messages via OMAP2 UART3 (n8x0)"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
 
        config DEBUG_OMAP3UART3
                bool "Kernel low-level debugging messages via OMAP3 UART3 (most omap3 boards)"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
                help
                  This covers at least cm_t3x, beagle, crane, devkit8000,
                  igep00x0, ldp, n900, n9(50), pandora, overo, touchbook,
@@ -673,17 +673,17 @@ choice
        config DEBUG_OMAP4UART3
                bool "Kernel low-level debugging messages via OMAP4/5 UART3 (omap4 blaze, panda, omap5 sevm)"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
 
        config DEBUG_OMAP3UART4
                bool "Kernel low-level debugging messages via OMAP36XX UART4"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
 
        config DEBUG_OMAP4UART4
                bool "Kernel low-level debugging messages via OMAP4/5 UART4"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
 
        config DEBUG_OMAP7XXUART1
                bool "Kernel low-level debugging via OMAP730 UART1"
@@ -712,22 +712,22 @@ choice
        config DEBUG_TI81XXUART1
                bool "Kernel low-level debugging messages via TI81XX UART1 (ti8148evm)"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
 
        config DEBUG_TI81XXUART2
                bool "Kernel low-level debugging messages via TI81XX UART2"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
 
        config DEBUG_TI81XXUART3
                bool "Kernel low-level debugging messages via TI81XX UART3 (ti8168evm)"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
 
        config DEBUG_AM33XXUART1
                bool "Kernel low-level debugging messages via AM33XX UART1"
                depends on ARCH_OMAP2PLUS
-               select DEBUG_OMAP2PLUS_UART
+               select DEBUG_UART_8250
 
        config DEBUG_ZOOM_UART
                bool "Kernel low-level debugging messages via Zoom2/3 UART"
@@ -896,12 +896,13 @@ choice
                  via SCIF2 on Renesas R-Car H1 (R8A7779).
 
        config DEBUG_RCAR_GEN2_SCIF0
-               bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7792/R8A7793"
-               depends on ARCH_R8A7790 || ARCH_R8A7791 || ARCH_R8A7792 || ARCH_R8A7793
+               bool "Kernel low-level debugging messages via SCIF0 on R-Car Gen2 and RZ/G1"
+               depends on ARCH_R8A7743 || ARCH_R8A7790 || ARCH_R8A7791 || \
+                       ARCH_R8A7792 || ARCH_R8A7793
                help
                  Say Y here if you want kernel low-level debugging support
-                 via SCIF0 on Renesas R-Car H2 (R8A7790), M2-W (R8A7791), V2H
-                 (R8A7792), or M2-N (R8A7793).
+                 via SCIF0 on Renesas RZ/G1M (R8A7743), R-Car H2 (R8A7790),
+                 M2-W (R8A7791), V2H (R8A7792), or M2-N (R8A7793).
 
        config DEBUG_RCAR_GEN2_SCIF2
                bool "Kernel low-level debugging messages via SCIF2 on R8A7794"
@@ -1523,6 +1524,17 @@ config DEBUG_UART_PHYS
        default 0x40090000 if DEBUG_LPC32XX
        default 0x40100000 if DEBUG_PXA_UART1
        default 0x42000000 if DEBUG_GEMINI
+       default 0x44e09000 if DEBUG_AM33XXUART1
+       default 0x48020000 if DEBUG_OMAP4UART3 || DEBUG_TI81XXUART1
+       default 0x48022000 if DEBUG_TI81XXUART2
+       default 0x48024000 if DEBUG_TI81XXUART3
+       default 0x4806a000 if DEBUG_OMAP2UART1 || DEBUG_OMAP3UART1 || \
+                               DEBUG_OMAP4UART1 || DEBUG_OMAP5UART1
+       default 0x4806c000 if DEBUG_OMAP2UART2 || DEBUG_OMAP3UART2 || \
+                               DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2
+       default 0x4806e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4
+       default 0x49020000 if DEBUG_OMAP3UART3
+       default 0x49042000 if DEBUG_OMAP3UART4
        default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
                                DEBUG_S3C2410_UART0)
        default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
@@ -1641,10 +1653,21 @@ config DEBUG_UART_VIRT
        default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
        default 0xf8ffee00 if DEBUG_AT91_SAM9263_DBGU
        default 0xf8fff200 if DEBUG_AT91_RM9200_DBGU
+       default 0xf9e09000 if DEBUG_AM33XXUART1
+       default 0xfa020000 if DEBUG_OMAP4UART3 || DEBUG_TI81XXUART1
+       default 0xfa022000 if DEBUG_TI81XXUART2
+       default 0xfa024000 if DEBUG_TI81XXUART3
+       default 0xfa06a000 if DEBUG_OMAP2UART1 || DEBUG_OMAP3UART1 || \
+                               DEBUG_OMAP4UART1 || DEBUG_OMAP5UART1
+       default 0xfa06c000 if DEBUG_OMAP2UART2 || DEBUG_OMAP3UART2 || \
+                               DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2
+       default 0xfa06e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4
        default 0xfa71e000 if DEBUG_QCOM_UARTDM
        default 0xfb002000 if DEBUG_CNS3XXX
        default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
        default 0xfb00c000 if DEBUG_AT91_SAMA5D4_USART3
+       default 0xfb020000 if DEBUG_OMAP3UART3
+       default 0xfb042000 if DEBUG_OMAP3UART4
        default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
        default 0xfc705000 if DEBUG_ZTE_ZX
        default 0xfcfe8600 if DEBUG_BCM63XX_UART
index 4b17f35dc9a7167bcce9b5c9c9b35b7375add15c..faf46abaa4a2773721a0c30b012a2ae52308daae 100644 (file)
@@ -46,6 +46,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
        at91sam9x35ek.dtb
 dtb-$(CONFIG_SOC_SAM_V7) += \
        at91-kizbox2.dtb \
+       at91-sama5d27_som1_ek.dtb \
        at91-sama5d2_xplained.dtb \
        at91-sama5d3_xplained.dtb \
        at91-tse850-3.dtb \
@@ -73,7 +74,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
        bcm2835-rpi-a-plus.dtb \
        bcm2836-rpi-2-b.dtb \
        bcm2837-rpi-3-b.dtb \
-       bcm2835-rpi-zero.dtb
+       bcm2835-rpi-zero.dtb \
+       bcm2835-rpi-zero-w.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += \
        bcm4708-asus-rt-ac56u.dtb \
        bcm4708-asus-rt-ac68u.dtb \
@@ -106,7 +108,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
        bcm953012hr.dtb \
        bcm953012k.dtb
 dtb-$(CONFIG_ARCH_BCM_53573) += \
-       bcm47189-tenda-ac9.dtb
+       bcm47189-tenda-ac9.dtb \
+       bcm947189acdbmr.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += \
        bcm963138dvt.dtb
 dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
@@ -180,6 +183,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
        exynos5440-ssdk5440.dtb \
        exynos5800-peach-pi.dtb
 dtb-$(CONFIG_ARCH_GEMINI) += \
+       gemini-dlink-dir-685.dtb \
        gemini-nas4220b.dtb \
        gemini-rut1xx.dtb \
        gemini-sq201.dtb \
@@ -340,6 +344,7 @@ dtb-$(CONFIG_SOC_IMX51) += \
        imx51-ts4800.dtb
 dtb-$(CONFIG_SOC_IMX53) += \
        imx53-ard.dtb \
+       imx53-cx9020.dtb \
        imx53-m53evk.dtb \
        imx53-mba53.dtb \
        imx53-qsb.dtb \
@@ -391,7 +396,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
        imx6dl-udoo.dtb \
        imx6dl-wandboard.dtb \
        imx6dl-wandboard-revb1.dtb \
+       imx6q-apalis-eval.dtb \
        imx6q-apalis-ixora.dtb \
+       imx6q-apalis-ixora-v1.1.dtb \
        imx6q-apf6dev.dtb \
        imx6q-arm2.dtb \
        imx6q-b450v3.dtb \
@@ -466,7 +473,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
        imx6sx-udoo-neo-full.dtb
 dtb-$(CONFIG_SOC_IMX6UL) += \
        imx6ul-14x14-evk.dtb \
-       imx6ul-geam-kit.dtb \
+       imx6ul-geam.dtb \
        imx6ul-isiot-emmc.dtb \
        imx6ul-isiot-nand.dtb \
        imx6ul-liteboard.dtb \
@@ -617,6 +624,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
        am335x-evmsk.dtb \
        am335x-icev2.dtb \
        am335x-lxm.dtb \
+       am335x-moxa-uc-8100-me-t.dtb \
        am335x-nano.dtb \
        am335x-pepper.dtb \
        am335x-phycore-rdk.dtb \
@@ -650,6 +658,7 @@ dtb-$(CONFIG_SOC_OMAP5) += \
 dtb-$(CONFIG_SOC_DRA7XX) += \
        am57xx-beagle-x15.dtb \
        am57xx-beagle-x15-revb1.dtb \
+       am57xx-beagle-x15-revc.dtb \
        am57xx-cl-som-am57x.dtb \
        am57xx-sbc-am57x.dtb \
        am572x-idk.dtb \
@@ -657,7 +666,8 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
        dra7-evm.dtb \
        dra72-evm.dtb \
        dra72-evm-revc.dtb \
-       dra71-evm.dtb
+       dra71-evm.dtb \
+       dra76-evm.dtb
 dtb-$(CONFIG_ARCH_ORION5X) += \
        orion5x-kuroboxpro.dtb \
        orion5x-lacie-d2-network.dtb \
@@ -903,6 +913,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
        sun8i-a33-q8-tablet.dtb \
        sun8i-a33-sinlinx-sina33.dtb \
        sun8i-a83t-allwinner-h8homlet-v2.dtb \
+       sun8i-a83t-bananapi-m3.dtb \
        sun8i-a83t-cubietruck-plus.dtb \
        sun8i-h2-plus-orangepi-zero.dtb \
        sun8i-h3-bananapi-m2-plus.dtb \
@@ -918,6 +929,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
        sun8i-h3-orangepi-pc-plus.dtb \
        sun8i-h3-orangepi-plus.dtb \
        sun8i-h3-orangepi-plus2e.dtb \
+       sun8i-r16-bananapi-m2m.dtb \
        sun8i-r16-parrot.dtb \
        sun8i-v3s-licheepi-zero.dtb \
        sun8i-v3s-licheepi-zero-dock.dtb
@@ -970,7 +982,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
        uniphier-pro4-sanji.dtb \
        uniphier-pxs2-gentil.dtb \
        uniphier-pxs2-vodka.dtb \
-       uniphier-sld3-ref.dtb \
        uniphier-sld8-ref.dtb
 dtb-$(CONFIG_ARCH_VERSATILE) += \
        versatile-ab.dtb \
@@ -1049,7 +1060,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
        mt6580-evbp1.dtb \
        mt6589-aquaris5.dtb \
        mt6592-evb.dtb \
-       mt7623-evb.dtb \
+       mt7623n-rfb-nand.dtb \
+       mt7623n-bananapi-bpi-r2.dtb \
        mt8127-moose.dtb \
        mt8135-evbp1.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
index 1d154444dfef245bf60e6336da038d1ff766512e..48a15fc641f22e40301c505625fc331efc4610e9 100644 (file)
        ti,pmic-shutdown-controller;
 
        charger {
-               interrupts = <0>, <1>;
-               interrupt-names = "USB", "AC";
                status = "okay";
        };
 
        pwrbutton {
-               interrupts = <2>;
                status = "okay";
        };
 
index d8769799772ea6cdacb0693427648cf61e0f0879..59431b23594489dd3f211c0be1a93c031d3c0c46 100644 (file)
        interrupts = <7>; /* NNMI */
 
        charger {
-               interrupts = <0>, <1>;
-               interrupt-names = "USB", "AC";
                status = "okay";
        };
 
        pwrbutton {
-               interrupts = <2>;
                status = "okay";
        };
 };
index 1c37a7c1ea17dd76fc2686c1bd9dd17acc250d99..ddd897556e035b6306306ca33eccc65c7ed45e3b 100644 (file)
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
                rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+               ti,nand-xfer-type = "prefetch-dma";
                ti,nand-ecc-opt = "bch8";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
new file mode 100644 (file)
index 0000000..f82233c
--- /dev/null
@@ -0,0 +1,525 @@
+/*
+ * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/
+ *
+ * Author: SZ Lin (林上智) <sz.lin@moxa.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+       model = "Moxa UC-8100-ME-T";
+       compatible = "moxa,uc-8100-me-t", "ti,am33xx";
+
+       cpus {
+               cpu@0 {
+                       cpu0-supply = <&vdd1_reg>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x20000000>; /* 512 MB */
+       };
+
+       vbat: vbat-regulator {
+               compatible = "regulator-fixed";
+       };
+
+       /* Power supply provides a fixed 3.3V @3A */
+       vmmcsd_fixed: vmmcsd-regulator {
+             compatible = "regulator-fixed";
+             regulator-name = "vmmcsd_fixed";
+             regulator-min-microvolt = <3300000>;
+             regulator-max-microvolt = <3300000>;
+             regulator-boot-on;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               led1 {
+                       label = "uc8100me:CEL1";
+                       gpios = <&gpio_xten 8 0>;
+                       default-state = "off";
+               };
+
+               led2 {
+                       label = "uc8100me:CEL2";
+                       gpios = <&gpio_xten 9 0>;
+                       default-state = "off";
+               };
+
+               led3 {
+                       label = "uc8100me:CEL3";
+                       gpios = <&gpio_xten 10 0>;
+                       default-state = "off";
+               };
+
+               led4 {
+                       label = "uc8100me:DIA1";
+                       gpios = <&gpio_xten 11 0>;
+                       default-state = "off";
+               };
+               led5 {
+                       label = "uc8100me:DIA2";
+                       gpios = <&gpio_xten 12 0>;
+                       default-state = "off";
+               };
+               led6 {
+                       label = "uc8100me:DIA3";
+                       gpios = <&gpio_xten 13 0>;
+                       default-state = "off";
+               };
+               led7 {
+                       label = "uc8100me:SD";
+                       gpios = <&gpio_xten 14 0>;
+                       default-state = "off";
+               };
+               led8 {
+                       label = "uc8100me:USB";
+                       gpios = <&gpio_xten 15 0>;
+                       default-state = "off";
+               };
+               led9 {
+                       label = "uc8100me:USER";
+                       gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+       };
+
+       buttons: push_button {
+               compatible = "gpio-keys";
+       };
+
+};
+
+&am33xx_pinmux {
+       pinctrl-names = "default";
+       pinctrl-0 = <&minipcie_pins>;
+
+       minipcie_pins: pinmux_minipcie {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_pclk.gpio2_24 */
+                       AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_ac_bias_en.gpio2_25 */
+                       AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_vsync.gpio2_22  Power off PIN*/
+               >;
+       };
+
+       push_button_pins: pinmux_push_button {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* mcasp0_ahcklx.gpio3_21 */
+               >;
+       };
+
+       i2c0_pins: pinmux_i2c0_pins {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                       AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+               >;
+       };
+
+
+       i2c1_pins: pinmux_i2c1_pins {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart0_ctsn.i2c1_sda */
+                       AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE3)       /* uart0_rtsn.i2c1_scl */
+               >;
+       };
+
+       uart0_pins: pinmux_uart0_pins {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
+                       AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+               >;
+       };
+
+       uart1_pins: pinmux_uart1_pins {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)              /* uart1_ctsn.uart1_ctsn */
+                       AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
+                       AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)    /* uart1_rxd.uart1_rxd */
+                       AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)             /* uart1_txd.uart1_txd */
+               >;
+       };
+
+       uart2_pins: pinmux_uart2_pins {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE6)              /* lcd_data14.uart5_ctsn */
+                       AM33XX_IOPAD(0x8dc, PIN_OUTPUT_PULLDOWN | MUX_MODE6)  /* lcd_data15.uart5_rtsn */
+                       AM33XX_IOPAD(0x8c4, PIN_INPUT_PULLUP | MUX_MODE4)     /* lcd_data9.uart5_rxd */
+                       AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE4)             /* lcd_data8.uart5_txd */
+               >;
+       };
+
+       cpsw_default: cpsw_default {
+               pinctrl-single,pins = <
+                       /* Slave 1 */
+                       AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs_dv */
+                       AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxerr.rmii1_rxerr */
+                       AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
+                       AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
+                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
+                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd1.rmii1_rxd1 */
+                       AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd0.rmii1_rxd0 */
+                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mii1_refclk.rmii1_refclk */
+
+                       /* Slave 2 */
+                       AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_crs_dv */
+                       AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rxer */
+                       AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_txen */
+                       AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_td1 */
+                       AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_td0 */
+                       AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rd1 */
+                       AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rd0 */
+                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii2_refclk */
+
+               >;
+       };
+
+       davinci_mdio_default: davinci_mdio_default {
+               pinctrl-single,pins = <
+                       /* MDIO */
+                       AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
+                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+               >;
+       };
+
+       mmc0_pins_default: pinmux_mmc0_pins {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3 */
+                       AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2 */
+                       AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1 */
+                       AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0 */
+                       AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk */
+                       AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd */
+                       AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE7)       /* mcasp0_aclkx.gpio3_14 */
+                       AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7)    /* mcasp0_aclkx.gpio3_18 */
+               >;
+       };
+
+       mmc2_pins_default: pinmux_mmc2_pins {
+               pinctrl-single,pins = <
+                       /* eMMC */
+                       AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad12.mmc2_dat0 */
+                       AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad13.mmc2_dat1 */
+                       AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad14.mmc2_dat2 */
+                       AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad15.mmc2_dat3 */
+                       AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad8.mmc2_dat4 */
+                       AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad9.mmc2_dat5 */
+                       AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad10.mmc2_dat6 */
+                       AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_ad11.mmc2_dat7 */
+                       AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_csn3.mmc2_cmd */
+                       AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)       /* gpmc_clk.mmc2_clk */
+               >;
+       };
+
+       spi0_pins: pinmux_spi0 {
+               pinctrl-single,pins = <
+                       AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
+                       AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
+                       AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
+                       AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
+               >;
+       };
+
+};
+
+&uart0 {
+       /* Console */
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+};
+
+&uart1 {
+       /* UART 1 setting */
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart1_pins>;
+};
+
+&uart5 {
+       /* UART 2 setting */
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart2_pins>;
+};
+
+&i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c0_pins>;
+
+       status = "okay";
+       clock-frequency = <400000>;
+
+       tpm: tpm@20 {
+               compatible = "infineon,slb9645tt";
+               reg = <0x20>;
+       };
+
+       tps: tps@2d {
+               compatible = "ti,tps65910";
+               reg = <0x2d>;
+       };
+
+       eeprom: eeprom@50 {
+               compatible = "atmel,24c16";
+               pagesize = <16>;
+               reg = <0x50>;
+       };
+
+       rtc_wdt: rtc_wdt@68 {
+               compatible = "dallas,ds1374";
+               reg = <0x68>;
+       };
+};
+
+&i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c1_pins>;
+
+       status = "okay";
+       clock-frequency = <400000>;
+       gpio_xten: gpio_xten@27 {
+               compatible = "nxp,pca9535";
+               gpio-controller;
+               #gpio-cells = <2>;
+               reg = <0x27>;
+       };
+};
+
+&usb {
+       status = "okay";
+};
+
+&usb_ctrl_mod {
+       status = "okay";
+};
+
+&usb0_phy {
+       status = "okay";
+};
+
+&usb1_phy {
+       status = "okay";
+};
+
+&usb0 {
+       status = "okay";
+       dr_mode = "host";
+};
+
+&usb1 {
+       status = "okay";
+       dr_mode = "host";
+};
+
+&cppi41dma  {
+       status = "okay";
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+       vcc1-supply = <&vbat>;
+       vcc2-supply = <&vbat>;
+       vcc3-supply = <&vbat>;
+       vcc4-supply = <&vbat>;
+       vcc5-supply = <&vbat>;
+       vcc6-supply = <&vbat>;
+       vcc7-supply = <&vbat>;
+       vccio-supply = <&vbat>;
+
+       regulators {
+               vrtc_reg: regulator@0 {
+                       regulator-always-on;
+               };
+
+               vio_reg: regulator@1 {
+                       regulator-always-on;
+               };
+
+               vdd1_reg: regulator@2 {
+                       /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                       regulator-name = "vdd_mpu";
+                       regulator-min-microvolt = <912500>;
+                       regulator-max-microvolt = <1378000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               vdd2_reg: regulator@3 {
+                       /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                       regulator-name = "vdd_core";
+                       regulator-min-microvolt = <912500>;
+                       regulator-max-microvolt = <1150000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               vdd3_reg: regulator@4 {
+                       regulator-always-on;
+               };
+
+               vdig1_reg: regulator@5 {
+                       regulator-always-on;
+               };
+
+               vdig2_reg: regulator@6 {
+                       regulator-always-on;
+               };
+
+               vpll_reg: regulator@7 {
+                       regulator-always-on;
+               };
+
+               vdac_reg: regulator@8 {
+                       regulator-always-on;
+               };
+
+               vaux1_reg: regulator@9 {
+                       regulator-always-on;
+               };
+
+               vaux2_reg: regulator@10 {
+                       regulator-always-on;
+               };
+
+               vaux33_reg: regulator@11 {
+                       regulator-always-on;
+               };
+
+               vmmc_reg: regulator@12 {
+                       compatible = "regulator-fixed";
+                       regulator-name = "vmmc_reg";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+               };
+       };
+};
+
+/* Power */
+&vbat {
+       regulator-name = "vbat";
+       regulator-min-microvolt = <5000000>;
+       regulator-max-microvolt = <5000000>;
+};
+
+&mac {
+       pinctrl-names = "default";
+       pinctrl-0 = <&cpsw_default>;
+       dual_emac = <1>;
+       status = "okay";
+};
+
+&davinci_mdio {
+       pinctrl-names = "default";
+       pinctrl-0 = <&davinci_mdio_default>;
+       status = "okay";
+};
+
+&cpsw_emac0 {
+       status = "okay";
+       phy_id = <&davinci_mdio>, <4>;
+       phy-mode = "rmii";
+       dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+       status = "okay";
+       phy_id = <&davinci_mdio>, <5>;
+       phy-mode = "rmii";
+       dual_emac_res_vlan = <2>;
+};
+
+&phy_sel {
+       reg= <0x44e10650 0xf5>;
+       rmii-clock-ext;
+};
+
+&sham {
+       status = "okay";
+};
+
+&aes {
+       status = "okay";
+};
+
+&gpio0 {
+       ti,no-reset-on-init;
+};
+
+&mmc1 {
+       pinctrl-names = "default";
+       vmmc-supply = <&vmmcsd_fixed>;
+       bus-width = <4>;
+       pinctrl-0 = <&mmc0_pins_default>;
+       cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+       wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&mmc3 {
+       dmas = <&edma_xbar 12 0 1
+                       &edma_xbar 13 0 2>;
+       dma-names = "tx", "rx";
+       pinctrl-names = "default";
+       vmmc-supply = <&vmmcsd_fixed>;
+       bus-width = <8>;
+       pinctrl-0 = <&mmc2_pins_default>;
+       ti,non-removable;
+       status = "okay";
+};
+
+&buttons {
+       pinctrl-names = "default";
+       pinctrl-0 = <&push_button_pins>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       button@0 {
+               label = "push_button";
+               linux,code = <0x100>;
+               gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+       };
+};
+
+/* SPI Busses */
+&spi0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi0_pins>;
+
+       m25p80@0 {
+               compatible = "mx25l6405d";
+               spi-max-frequency = <40000000>;
+
+               reg = <0>;
+               spi-cpol;
+               spi-cpha;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               /* reg : The partition's offset and size within the mtd bank. */
+               partitions@0 {
+                       label = "MLO";
+                       reg = <0x0 0x80000>;
+               };
+
+               partitions@1 {
+                       label = "U-Boot";
+                       reg = <0x80000 0x100000>;
+               };
+
+               partitions@2 {
+                       label = "U-Boot Env";
+                       reg = <0x180000 0x20000>;
+               };
+       };
+};
index 29a538ecd405db81959e839768dc2731d10a63aa..afb8eb0a0a16ee63ea1ece64e694ac847c249067 100644 (file)
                        system-clock-frequency = <12000000>;
                };
        };
+
+       beeper: beeper {
+               compatible = "gpio-beeper";
+               pinctrl-names = "default";
+               pinctrl-0 = <&beeper_pins>;
+               gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+       };
 };
 
 &am43xx_pinmux {
                        AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
                >;
        };
+
+       beeper_pins: beeper_pins {
+               pinctrl-single,pins = <
+                       AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* cam1_field.gpio4_12 */
+               >;
+       };
+
 };
 
 &uart0 {
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
                rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;  /* gpmc_wait0 */
+               ti,nand-xfer-type = "prefetch-dma";
                ti,nand-ecc-opt = "bch16";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
index 54f40f370011c211664a6583a845146b50b996af..9d276af7c539f3dd1cb382f12d4bca7d9bd2fb3d 100644 (file)
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
                rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;  /* gpmc_wait0 */
+               ti,nand-xfer-type = "prefetch-dma";
                ti,nand-ecc-opt = "bch16";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
index 7b207835b2d161244fc8e09126fe384bf7eae9fa..debf9464403ef52a5c4b7e27135b1a5ed5778fd2 100644 (file)
@@ -11,6 +11,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "am57xx-idk-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
 
 / {
        model = "TI AM5718 IDK";
        };
 };
 
-&mmc1 {
-       status = "okay";
-       vmmc-supply = <&ldo1_reg>;
-       bus-width = <4>;
-       cd-gpios = <&gpio6 27 0>; /* gpio 219 */
-};
-
 &omap_dwc3_2 {
        extcon = <&extcon_usb2>;
 };
                status = "okay";
        };
 };
+
+&pcie1_rc {
+       status = "okay";
+       gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
+       gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&mmc1 {
+       pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+       pinctrl-0 = <&mmc1_pins_default>;
+       pinctrl-1 = <&mmc1_pins_hs>;
+       pinctrl-2 = <&mmc1_pins_sdr12>;
+       pinctrl-3 = <&mmc1_pins_sdr25>;
+       pinctrl-4 = <&mmc1_pins_sdr50>;
+       pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
+       pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+};
+
+&mmc2 {
+       pinctrl-names = "default", "hs", "ddr_1_8v";
+       pinctrl-0 = <&mmc2_pins_default>;
+       pinctrl-1 = <&mmc2_pins_hs>;
+       pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
+};
index 9da6d83ca185e52c79ea4ebd180fb1d21144280c..a578fe97ba3bd9ec210df3f1827cc936a748d2bd 100644 (file)
@@ -12,6 +12,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "am57xx-idk-common.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
 
 / {
        model = "TI AM5728 IDK";
        };
 };
 
+&mmc1 {
+       pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+       pinctrl-0 = <&mmc1_pins_default>;
+       pinctrl-1 = <&mmc1_pins_hs>;
+       pinctrl-2 = <&mmc1_pins_sdr12>;
+       pinctrl-3 = <&mmc1_pins_sdr25>;
+       pinctrl-4 = <&mmc1_pins_sdr50>;
+       pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
+       pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+};
+
+&mmc2 {
+       pinctrl-names = "default", "hs", "ddr_1_8v";
+       pinctrl-0 = <&mmc2_pins_default>;
+       pinctrl-1 = <&mmc2_pins_hs>;
+       pinctrl-2 = <&mmc2_pins_ddr_rev20>;
+};
+
 &omap_dwc3_2 {
        extcon = <&extcon_usb2>;
 };
        vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
 };
 
-&mmc1 {
-       status = "okay";
-       vmmc-supply = <&v3_3d>;
-       vmmc_aux-supply = <&ldo1_reg>;
-       bus-width = <4>;
-       cd-gpios = <&gpio6 27 0>; /* gpio 219 */
-};
-
 &sn65hvs882 {
        load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
 };
 
-&pcie1 {
+&pcie1_rc {
+       status = "okay";
+       gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
        gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
 };
 
index fdfe5b16b806298a1aac3a136a873dfc2ab891df..49aeecd312b4b10af2cb3badd68a4982fa8a921d 100644 (file)
@@ -9,6 +9,7 @@
 
 #include "dra74x.dtsi"
 #include "am57xx-commercial-grade.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
        };
 };
 
-&dra7_pmx_core {
-       mmc1_pins_default: mmc1_pins_default {
-               pinctrl-single,pins = <
-                       DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)       /* mmc1sdcd.gpio219 */
-                       DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
-                       DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
-                       DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
-                       DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
-                       DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
-                       DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
-               >;
-       };
-
-       mmc2_pins_default: mmc2_pins_default {
-               pinctrl-single,pins = <
-                       DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
-                       DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
-                       DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
-                       DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
-                       DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
-                       DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
-                       DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
-                       DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
-                       DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
-                       DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
-               >;
-       };
-};
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
        };
 };
 
-&pcie1 {
+&pcie1_rc {
+       status = "ok";
+       gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+};
+
+&pcie1_ep {
        gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
 };
 
index 39a92aff0a0dc5338d29c13949001e2558f17474..5a77b334923d051f6943730b8d51849fe6161596 100644 (file)
 };
 
 &mmc1 {
+       pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+       pinctrl-0 = <&mmc1_pins_default>;
+       pinctrl-1 = <&mmc1_pins_hs>;
+       pinctrl-2 = <&mmc1_pins_sdr12>;
+       pinctrl-3 = <&mmc1_pins_sdr25>;
+       pinctrl-4 = <&mmc1_pins_sdr50>;
+       pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
+       pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
        vmmc-supply = <&vdd_3v3>;
-       vmmc-aux-supply = <&ldo1_reg>;
+       vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+       pinctrl-names = "default", "hs", "ddr_1_8v";
+       pinctrl-0 = <&mmc2_pins_default>;
+       pinctrl-1 = <&mmc2_pins_hs>;
+       pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
 };
 
 /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
new file mode 100644 (file)
index 0000000..17c41da
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am57xx-beagle-x15-common.dtsi"
+
+/ {
+       model = "TI AM5728 BeagleBoard-X15 rev C";
+};
+
+&tpd12s015 {
+       gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>,   /* gpio7_10, CT CP HPD */
+               <&gpio2 30 GPIO_ACTIVE_HIGH>,   /* gpio2_30, LS OE */
+               <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
+};
+
+&mmc1 {
+       pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+       pinctrl-0 = <&mmc1_pins_default>;
+       pinctrl-1 = <&mmc1_pins_hs>;
+       pinctrl-2 = <&mmc1_pins_sdr12>;
+       pinctrl-3 = <&mmc1_pins_sdr25>;
+       pinctrl-4 = <&mmc1_pins_sdr50>;
+       pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
+       pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+       vmmc-supply = <&vdd_3v3>;
+       vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+       pinctrl-names = "default", "hs", "ddr_1_8v";
+       pinctrl-0 = <&mmc2_pins_default>;
+       pinctrl-1 = <&mmc2_pins_hs>;
+       pinctrl-2 = <&mmc2_pins_ddr_rev20>;
+};
index 19a60a11c19890d49f608e12c4a4c3a5d3c822bc..d6689106d2a83935ea6ac98fd89f42ce06132879 100644 (file)
 };
 
 &mmc1 {
+       pinctrl-names = "default", "hs";
+       pinctrl-0 = <&mmc1_pins_default>;
+       pinctrl-1 = <&mmc1_pins_hs>;
+
        vmmc-supply = <&ldo1_reg>;
 };
 
+&mmc2 {
+       pinctrl-names = "default", "hs", "ddr_1_8v";
+       pinctrl-0 = <&mmc2_pins_default>;
+       pinctrl-1 = <&mmc2_pins_hs>;
+       pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
+};
+
 /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
 &phy1 {
        max-speed = <100>;
index c536b2f5389f2786930a48eb0f7446311c622121..97aa8e6a56da8f7c8722f5243e01fca0e944f629 100644 (file)
        dr_mode = "peripheral";
 };
 
+&mmc1 {
+       status = "okay";
+       vmmc-supply = <&v3_3d>;
+       vqmmc-supply = <&ldo1_reg>;
+       bus-width = <4>;
+       cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+};
+
 &mmc2 {
        status = "okay";
        vmmc-supply = <&v3_3d>;
index f9cf1273f35e0ae65dd4398037f9662bcf4ff28e..b1cf5a26f3c2a460b7b9d8fc41127c30cf2cc533 100644 (file)
@@ -72,7 +72,7 @@
                        reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
                };
 
-               pciec: pcie-controller@82000000 {
+               pciec: pcie@82000000 {
                        compatible = "marvell,armada-370-pcie";
                        status = "disabled";
                        device_type = "pci";
                                #interrupt-cells = <1>;
                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 58>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 62>;
                                marvell,pcie-port = <1>;
index 50c5e8417802cd42c3beee13bcf9a23b3a127791..7225c7ce9a8dbca5cb909c0c1b55376072c2e263 100644 (file)
                        };
                };
 
-               pciec: pcie-controller@82000000 {
+               pciec: pcie@82000000 {
                        compatible = "marvell,armada-370-pcie";
                        status = "disabled";
                        device_type = "pci";
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <0>;
index e392f6036f3956a7b2494d7fb502f5b5a3a99349..132596fd08603e68d458cb264ae23ca48c0c7929 100644 (file)
@@ -71,7 +71,7 @@
                        };
                };
 
-               pcie-controller {
+               pcie {
                        compatible = "marvell,armada-370-pcie";
                        status = "disabled";
                        device_type = "pci";
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <2>;
index db5b9f6b615d8f8ea430f7ae790bc82858add8e8..25d2d720dc0e2cacc98b402e609e0fe78eb01acb 100644 (file)
                        status = "okay";
                };
 
-               pcie-controller {
+               pcie {
                        status = "okay";
 
                        /*
index be16ce39fb3d659f4833722063a26aa043bace11..06831e1e3f808b8419b299e72d8dfbd94568de3f 100644 (file)
@@ -96,7 +96,7 @@
                        };
                };
 
-               pcie-controller {
+               pcie {
                        status = "okay";
 
                        pcie@1,0 {
index 7fcc4c4885cffa9b51fe8c1c9911e4ea3cfcc138..74863aff01c6e0259576403ae22ece1cc12a7d4d 100644 (file)
@@ -70,7 +70,7 @@
        };
 
        soc {
-               pciec: pcie-controller {
+               pciec: pcie {
                        compatible = "marvell,armada-370-pcie";
                        status = "disabled";
                        device_type = "pci";
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <2>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <3>;
index 0d5f1f06227568389c072194bf7da8ae6957012d..ee7b0089eff035a7f0fda7ed43b6878183c6c53a 100644 (file)
@@ -62,7 +62,7 @@
                        };
                };
 
-               pcie-controller {
+               pcie {
                        pcie@3,0 {
                                /* Port 2, Lane 0. CON2, nearest CPU. */
                                reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
index 0f5938bede53c30ce84f24a9a9b733517cc52118..68acfc9687069bf141c01309608b8806920bb446 100644 (file)
                        };
                };
 
-               pcie-controller {
+               pcie {
                        status = "okay";
                        /*
                         * The two PCIe units are accessible through
index 1ac923826445495edd6f725b44ce9c2134a5382f..a4ec1fa3752979fd30a1c9870a072d217c374b18 100644 (file)
                        status = "okay";
                };
 
-               pcie-controller {
+               pcie {
                        status = "okay";
                        /*
                         * The two PCIe units are accessible through
index 563901e0ec071f0c66a4590b17fe5c3f6cfcbd69..f503955dbd3b810db157344e3f9cf48dadd4b1ca 100644 (file)
                        status = "okay";
                };
 
-               pcie-controller {
+               pcie {
                        status = "okay";
                        /*
                         * One PCIe units is accessible through
index af82f275eac248791a2286b49c87bfd7c536db08..9cc3ca0376b934e10c863735f3e9a14ee72c0ee1 100644 (file)
                        };
                };
 
-               pcie-controller {
+               pcie {
                        status = "okay";
                        /*
                         * One PCIe units is accessible through
index af31f5d6c0e571f607fa47eb7aa00094d3ffdcb9..7ff0811e61db3ad73be8f0c9ea8f79ebde1681c7 100644 (file)
                                reg = <0xc000 0x58>;
                        };
 
+                       timer@c200 {
+                               compatible = "arm,cortex-a9-global-timer";
+                               reg = <0xc200 0x20>;
+                               interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
+                               clocks = <&coreclk 2>;
+                       };
+
                        timer@c600 {
                                compatible = "arm,cortex-a9-twd-timer";
                                reg = <0xc600 0x20>;
index 2afed2ce47412dce518785bdc1092c27b08766fb..c718a5242595f4157215ea476fccc998372bbccf 100644 (file)
                        };
                };
 
-               pcie-controller {
+               pcie {
                        status = "okay";
 
                        /* CON30 */
index 2cdbba804c1eaedf2034902e038e1696850c42f3..ef491b524fd6c4c39b391d4c022210c4744f9e37 100644 (file)
                        };
                };
 
-               pcie-controller {
+               pcie {
                        status = "okay";
 
                        /*
index e8604281c3c9916522d496937c73c1b31c6f22c9..f0e0379f7619220d39defb0f72887623ba850768 100644 (file)
                        };
                };
 
-               pcie-controller {
+               pcie {
                        status = "okay";
 
                        pcie@1,0 {
index 60fbfd5907c71049e75935cba303f795be38ad72..ea657071e27888c49294556e047f556d499f6300 100644 (file)
                        };
                };
 
-               pcie-controller {
+               pcie {
                        compatible = "marvell,armada-370-pcie";
                        status = "disabled";
                        device_type = "pci";
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <2>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
                                marvell,pcie-port = <3>;
index be22ec5236acfe5f11626a7f50447944564fda60..bdd4c7a45fbf43995f899982c499d9e9c99da5c5 100644 (file)
@@ -91,7 +91,7 @@
                /*
                 * 98DX3236 has 1 x1 PCIe unit Gen2.0
                 */
-               pciec: pcie-controller@82000000 {
+               pciec: pcie@82000000 {
                        compatible = "marvell,armada-xp-pcie";
                        status = "disabled";
                        device_type = "pci";
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 58>;
                                marvell,pcie-port = <0>;
index a33974254d8cddb36ee6538bc1eec767c0ce756d..065282c217897fdfdab6ecb0dd365614a6478468 100644 (file)
                /* Port 2, Lane 0 */
                status = "okay";
        };
-       pcie@10,0 {
+       pcie@a,0 {
                /* Port 3, Lane 0 */
                status = "okay";
        };
index d62bf7bea1df4db579d8d22311d40ef8f0eaa25e..ac9eab8ac186c78ba88e0e03907f429886953e04 100644 (file)
                /* Port 2, Lane 0 */
                status = "okay";
        };
-       pcie@10,0 {
+       pcie@a,0 {
                /* Port 3, Lane 0 */
                status = "okay";
        };
index 9f25814077f2b446f9c54ab22ee277a10288fae6..129738f7973d4b4c90cdd79d14864b8e34de76db 100644 (file)
@@ -86,7 +86,7 @@
                 * configured as x4 or quad x1 lanes. One unit is
                 * x1 only.
                 */
-               pciec: pcie-controller@82000000 {
+               pciec: pcie@82000000 {
                        compatible = "marvell,armada-xp-pcie";
                        status = "disabled";
                        device_type = "pci";
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 58>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 59>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 60>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 61>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
                                          0x81000000 0 0 0x81000000 0x5 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 62>;
                                marvell,pcie-port = <1>;
index 2bfe07aebf1aefae7611c2b7899b824c1527306a..e58d597e37b98a414aa430f4d2635c90315b3a82 100644 (file)
@@ -87,7 +87,7 @@
                 * configured as x4 or quad x1 lanes. One unit is
                 * x4 only.
                 */
-               pciec: pcie-controller@82000000 {
+               pciec: pcie@82000000 {
                        compatible = "marvell,armada-xp-pcie";
                        status = "disabled";
                        device_type = "pci";
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 58>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 59>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 60>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 61>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
                                          0x81000000 0 0 0x81000000 0x5 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 62>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
                                          0x81000000 0 0 0x81000000 0x6 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 63>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
                                          0x81000000 0 0 0x81000000 0x7 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 64>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
                                          0x81000000 0 0 0x81000000 0x8 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 65>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
                                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 99>;
                                marvell,pcie-port = <2>;
index 6c33935f7074730e193781173661ad717a202e32..a5c961cee7de3856d33046ca365d5d0f998d993c 100644 (file)
                 * configured as x4 or quad x1 lanes. Two units are
                 * x4/x1.
                 */
-               pciec: pcie-controller@82000000 {
+               pciec: pcie@82000000 {
                        compatible = "marvell,armada-xp-pcie";
                        status = "disabled";
                        device_type = "pci";
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 58>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 59>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 60>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 61>;
                                marvell,pcie-port = <0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
                                          0x81000000 0 0 0x81000000 0x5 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 62>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
                                          0x81000000 0 0 0x81000000 0x6 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 63>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
                                          0x81000000 0 0 0x81000000 0x7 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 64>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
                                          0x81000000 0 0 0x81000000 0x8 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 65>;
                                marvell,pcie-port = <1>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
                                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 99>;
                                marvell,pcie-port = <2>;
                                status = "disabled";
                        };
 
-                       pcie10: pcie@10,0 {
+                       pcie10: pcie@a,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
                                reg = <0x5000 0 0 0 0>;
                                #interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
                                          0x81000000 0 0 0x81000000 0xa 0 1 0>;
+                               bus-range = <0x00 0xff>;
                                interrupt-map-mask = <0 0 0 0>;
                                interrupt-map = <0 0 0 0 &mpic 103>;
                                marvell,pcie-port = <3>;
index 8a04c7e2d8185c9a72ea7824785ac93009672561..22b958537d31ada6dac768be3de7e2eddf31bfdb 100644 (file)
@@ -26,7 +26,7 @@
 
                fmc: flash-controller@1e620000 {
                        reg = < 0x1e620000 0x94
-                               0x20000000 0x02000000 >;
+                               0x20000000 0x10000000 >;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "aspeed,ast2400-fmc";
@@ -41,7 +41,7 @@
 
                spi: flash-controller@1e630000 {
                        reg = < 0x1e630000 0x18
-                               0x30000000 0x02000000 >;
+                               0x30000000 0x10000000 >;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "aspeed,ast2400-spi";
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
new file mode 100644 (file)
index 0000000..63a5af8
--- /dev/null
@@ -0,0 +1,102 @@
+/*
+ * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
+ *
+ *  Copyright (c) 2017, Microchip Technology Inc.
+ *                2017 Cristian Birsan <cristian.birsan@microchip.com>
+ *                2017 Claudiu Beznea <claudiu.beznea@microchip.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+
+/ {
+       model = "Atmel SAMA5D27 SoM1";
+       compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+       clocks {
+               slow_xtal {
+                       clock-frequency = <32768>;
+               };
+
+               main_xtal {
+                       clock-frequency = <24000000>;
+               };
+       };
+
+       ahb {
+               apb {
+                       macb0: ethernet@f8008000 {
+                               pinctrl-names = "default";
+                          &nbs