Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and 'clk...
authorStephen Boyd <sboyd@kernel.org>
Fri, 8 Mar 2019 18:29:15 +0000 (10:29 -0800)
committerStephen Boyd <sboyd@kernel.org>
Fri, 8 Mar 2019 18:29:15 +0000 (10:29 -0800)
 - Updates for qcom MSM8998 GCC clks
 - qcom MSM8998 RPM managed clks
 - Random static analysis fixes for clk drivers

* clk-qcom-msm8998:
  clk: qcom: Make common clk_hw registrations
  clk: qcom: smd: Add support for MSM8998 rpm clocks
  clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998
  clk: qcom: Add missing freq for usb30_master_clk on 8998
  clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocks

* clk-fractional-parent:
  clk: fractional-divider: check parent rate only if flag is set

* clk-x86-mv:
  clk: x86: Move clk-lpss.h to platform_data/x86

* clk-SA-fixes:
  clk: mediatek: fix platform_no_drv_owner.cocci warnings
  clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings
  clk: qoriq: Improve an error message

21 files changed:
Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
drivers/acpi/acpi_lpss.c
drivers/clk/clk-fractional-divider.c
drivers/clk/clk-qoriq.c
drivers/clk/mediatek/clk-mt2712.c
drivers/clk/qcom/clk-smd-rpm.c
drivers/clk/qcom/common.c
drivers/clk/qcom/common.h
drivers/clk/qcom/gcc-ipq8074.c
drivers/clk/qcom/gcc-mdm9615.c
drivers/clk/qcom/gcc-msm8996.c
drivers/clk/qcom/gcc-msm8998.c
drivers/clk/qcom/gcc-qcs404.c
drivers/clk/qcom/gcc-sdm660.c
drivers/clk/qcom/mmcc-msm8996.c
drivers/clk/tegra/clk-dfll.c
drivers/clk/x86/clk-lpt.c
include/dt-bindings/clock/qcom,rpmcc.h
include/linux/clk-provider.h
include/linux/platform_data/clk-lpss.h [deleted file]
include/linux/platform_data/x86/clk-lpss.h [new file with mode: 0644]

index 87b4949e9bc8e81c2cdaa5b8de040be571da006f..944719bd586f7f4e9a4a5e207affe26a1b60d51e 100644 (file)
@@ -16,6 +16,7 @@ Required properties :
                        "qcom,rpmcc-msm8974", "qcom,rpmcc"
                        "qcom,rpmcc-apq8064", "qcom,rpmcc"
                        "qcom,rpmcc-msm8996", "qcom,rpmcc"
+                       "qcom,rpmcc-msm8998", "qcom,rpmcc"
                        "qcom,rpmcc-qcs404", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1
index 5f94c35d165fe917151fa90127819b6f1d686db3..1e2a10a06b9dcec92accab9e1fd6e485cb19e052 100644 (file)
@@ -18,7 +18,7 @@
 #include <linux/mutex.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
-#include <linux/platform_data/clk-lpss.h>
+#include <linux/platform_data/x86/clk-lpss.h>
 #include <linux/platform_data/x86/pmc_atom.h>
 #include <linux/pm_domain.h>
 #include <linux/pm_runtime.h>
index 545dceec0bbf0230f72163a1d0506f1dc8401b49..fdfe2e423d1506e96a059cdb054796dd9c955bd6 100644 (file)
@@ -79,7 +79,7 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
        unsigned long m, n;
        u64 ret;
 
-       if (!rate || rate >= *parent_rate)
+       if (!rate || (!clk_hw_can_set_rate_parent(hw) && rate >= *parent_rate))
                return *parent_rate;
 
        if (fd->approximation)
index 0e84f6dfa54e85eb664bb8ca395e9cb8afd15327..1212a9be7e80f0d389b00670b1b345f409b63448 100644 (file)
@@ -1148,8 +1148,8 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
                pll->div[i].clk = clk;
                ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
                if (ret != 0)
-                       pr_err("%s: %s: register to lookup table failed %ld\n",
-                              __func__, pll->div[i].name, PTR_ERR(clk));
+                       pr_err("%s: %s: register to lookup table failed %d\n",
+                              __func__, pll->div[i].name, ret);
 
        }
 }
index 991d4093726e5c1a191af47895a2dd247a53f9dc..2895a5ae814d52f7e0640b0b6f4503c229f0a6d0 100644 (file)
@@ -1463,7 +1463,6 @@ static struct platform_driver clk_mt2712_drv = {
        .probe = clk_mt2712_probe,
        .driver = {
                .name = "clk-mt2712",
-               .owner = THIS_MODULE,
                .of_match_table = of_match_clk_mt2712,
        },
 };
index d3aadaeb2903348d7e31ed3c2e115badc200a4e3..22dd42ad922365a7bdf1564fa35f6807de74ef0d 100644 (file)
@@ -655,10 +655,73 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
        .num_clks = ARRAY_SIZE(qcs404_clks),
 };
 
+/* msm8998 */
+DEFINE_CLK_SMD_RPM(msm8998, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
+DEFINE_CLK_SMD_RPM(msm8998, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
+DEFINE_CLK_SMD_RPM(msm8998, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, div_clk1, div_clk1_a, 0xb);
+DEFINE_CLK_SMD_RPM(msm8998, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
+                                    3);
+DEFINE_CLK_SMD_RPM(msm8998, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
+                  QCOM_SMD_RPM_MMAXI_CLK, 0);
+DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
+                  QCOM_SMD_RPM_AGGR_CLK, 1);
+DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
+                  QCOM_SMD_RPM_AGGR_CLK, 2);
+DEFINE_CLK_SMD_RPM_QDSS(msm8998, qdss_clk, qdss_a_clk,
+                       QCOM_SMD_RPM_MISC_CLK, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk1, rf_clk1_a, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk2_pin, rf_clk2_a_pin, 5);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6);
+static struct clk_smd_rpm *msm8998_clks[] = {
+       [RPM_SMD_SNOC_CLK] = &msm8998_snoc_clk,
+       [RPM_SMD_SNOC_A_CLK] = &msm8998_snoc_a_clk,
+       [RPM_SMD_CNOC_CLK] = &msm8998_cnoc_clk,
+       [RPM_SMD_CNOC_A_CLK] = &msm8998_cnoc_a_clk,
+       [RPM_SMD_CE1_CLK] = &msm8998_ce1_clk,
+       [RPM_SMD_CE1_A_CLK] = &msm8998_ce1_a_clk,
+       [RPM_SMD_DIV_CLK1] = &msm8998_div_clk1,
+       [RPM_SMD_DIV_A_CLK1] = &msm8998_div_clk1_a,
+       [RPM_SMD_IPA_CLK] = &msm8998_ipa_clk,
+       [RPM_SMD_IPA_A_CLK] = &msm8998_ipa_a_clk,
+       [RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1,
+       [RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a,
+       [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2,
+       [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a,
+       [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
+       [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
+       [RPM_SMD_MMAXI_CLK] = &msm8998_mmssnoc_axi_rpm_clk,
+       [RPM_SMD_MMAXI_A_CLK] = &msm8998_mmssnoc_axi_rpm_a_clk,
+       [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
+       [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
+       [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
+       [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
+       [RPM_SMD_QDSS_CLK] = &msm8998_qdss_clk,
+       [RPM_SMD_QDSS_A_CLK] = &msm8998_qdss_a_clk,
+       [RPM_SMD_RF_CLK1] = &msm8998_rf_clk1,
+       [RPM_SMD_RF_CLK1_A] = &msm8998_rf_clk1_a,
+       [RPM_SMD_RF_CLK2_PIN] = &msm8998_rf_clk2_pin,
+       [RPM_SMD_RF_CLK2_A_PIN] = &msm8998_rf_clk2_a_pin,
+       [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
+       [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
+       [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
+       [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
+};
+
+static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
+       .clks = msm8998_clks,
+       .num_clks = ARRAY_SIZE(msm8998_clks),
+};
+
 static const struct of_device_id rpm_smd_clk_match_table[] = {
        { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
        { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
        { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
+       { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
        { .compatible = "qcom,rpmcc-qcs404",  .data = &rpm_clk_qcs404  },
        { }
 };
index 0a48ed56833b4b554a14c3d71b71edc50a72f348..a6b2f86112d8634d79c4fa912d99ecb41dd0e600 100644 (file)
@@ -231,6 +231,8 @@ int qcom_cc_really_probe(struct platform_device *pdev,
        struct gdsc_desc *scd;
        size_t num_clks = desc->num_clks;
        struct clk_regmap **rclks = desc->clks;
+       size_t num_clk_hws = desc->num_clk_hws;
+       struct clk_hw **clk_hws = desc->clk_hws;
 
        cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
        if (!cc)
@@ -269,6 +271,12 @@ int qcom_cc_really_probe(struct platform_device *pdev,
 
        qcom_cc_drop_protected(dev, cc);
 
+       for (i = 0; i < num_clk_hws; i++) {
+               ret = devm_clk_hw_register(dev, clk_hws[i]);
+               if (ret)
+                       return ret;
+       }
+
        for (i = 0; i < num_clks; i++) {
                if (!rclks[i])
                        continue;
index 4aa33ee70bae1031f459fc3a70adf4d60a5f6473..1e2a8bdac55a3781ec49ab988a27db6e7c8c5f0d 100644 (file)
@@ -27,6 +27,8 @@ struct qcom_cc_desc {
        size_t num_resets;
        struct gdsc **gdscs;
        size_t num_gdscs;
+       struct clk_hw **clk_hws;
+       size_t num_clk_hws;
 };
 
 /**
index 505c6263141d9e31fd7ff325976aa569dab7adfa..0e32892b438c78adcbe56bf6aefb40f2958013f4 100644 (file)
@@ -4715,18 +4715,12 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = {
        .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
        .resets = gcc_ipq8074_resets,
        .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
+       .clk_hws = gcc_ipq8074_hws,
+       .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
 };
 
 static int gcc_ipq8074_probe(struct platform_device *pdev)
 {
-       int ret, i;
-
-       for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) {
-               ret = devm_clk_hw_register(&pdev->dev, gcc_ipq8074_hws[i]);
-               if (ret)
-                       return ret;
-       }
-
        return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
 }
 
index 849046fbed6d40963c2100e267e048ab6a5bb981..8c6d93144b9ce2612fa713db7347ce1a57ebfd98 100644 (file)
@@ -1702,6 +1702,8 @@ static const struct qcom_cc_desc gcc_mdm9615_desc = {
        .num_clks = ARRAY_SIZE(gcc_mdm9615_clks),
        .resets = gcc_mdm9615_resets,
        .num_resets = ARRAY_SIZE(gcc_mdm9615_resets),
+       .clk_hws = gcc_mdm9615_hws,
+       .num_clk_hws = ARRAY_SIZE(gcc_mdm9615_hws),
 };
 
 static const struct of_device_id gcc_mdm9615_match_table[] = {
@@ -1712,21 +1714,12 @@ MODULE_DEVICE_TABLE(of, gcc_mdm9615_match_table);
 
 static int gcc_mdm9615_probe(struct platform_device *pdev)
 {
-       struct device *dev = &pdev->dev;
        struct regmap *regmap;
-       int ret;
-       int i;
 
        regmap = qcom_cc_map(pdev, &gcc_mdm9615_desc);
        if (IS_ERR(regmap))
                return PTR_ERR(regmap);
 
-       for (i = 0; i < ARRAY_SIZE(gcc_mdm9615_hws); i++) {
-               ret = devm_clk_hw_register(dev, gcc_mdm9615_hws[i]);
-               if (ret)
-                       return ret;
-       }
-
        return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap);
 }
 
index 9d136172c27ca460172bd913af850ee4a3e32d55..4632b9272b7f4f31547c20969425b928a7b0df0d 100644 (file)
@@ -3656,6 +3656,8 @@ static const struct qcom_cc_desc gcc_msm8996_desc = {
        .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
        .gdscs = gcc_msm8996_gdscs,
        .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
+       .clk_hws = gcc_msm8996_hws,
+       .num_clk_hws = ARRAY_SIZE(gcc_msm8996_hws),
 };
 
 static const struct of_device_id gcc_msm8996_match_table[] = {
@@ -3666,8 +3668,6 @@ MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
 
 static int gcc_msm8996_probe(struct platform_device *pdev)
 {
-       struct device *dev = &pdev->dev;
-       int i, ret;
        struct regmap *regmap;
 
        regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
@@ -3680,12 +3680,6 @@ static int gcc_msm8996_probe(struct platform_device *pdev)
         */
        regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
 
-       for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
-               ret = devm_clk_hw_register(dev, gcc_msm8996_hws[i]);
-               if (ret)
-                       return ret;
-       }
-
        return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
 }
 
index 1b779396e04fa30f02c09ab276b9fa1149a5dd13..c240fba794c7a25b882caa3e33fbd3ff386c797a 100644 (file)
@@ -1112,6 +1112,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
 
 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
        F(19200000, P_XO, 1, 0, 0),
+       F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
        F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
        F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
        { }
@@ -1189,6 +1190,7 @@ static struct clk_branch gcc_aggre1_ufs_axi_clk = {
                                "ufs_axi_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1206,6 +1208,7 @@ static struct clk_branch gcc_aggre1_usb3_axi_clk = {
                                "usb30_master_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1288,6 +1291,7 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
                                "blsp1_qup1_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1305,6 +1309,7 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
                                "blsp1_qup1_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1322,6 +1327,7 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
                                "blsp1_qup2_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1339,6 +1345,7 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
                                "blsp1_qup2_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1356,6 +1363,7 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
                                "blsp1_qup3_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1373,6 +1381,7 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
                                "blsp1_qup3_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1390,6 +1399,7 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
                                "blsp1_qup4_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1407,6 +1417,7 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
                                "blsp1_qup4_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1424,6 +1435,7 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
                                "blsp1_qup5_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1441,6 +1453,7 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
                                "blsp1_qup5_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1458,6 +1471,7 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
                                "blsp1_qup6_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1475,6 +1489,7 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
                                "blsp1_qup6_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1505,6 +1520,7 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
                                "blsp1_uart1_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1522,6 +1538,7 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
                                "blsp1_uart2_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1539,6 +1556,7 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
                                "blsp1_uart3_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1569,6 +1587,7 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
                                "blsp2_qup1_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1586,6 +1605,7 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
                                "blsp2_qup1_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1603,6 +1623,7 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
                                "blsp2_qup2_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1620,6 +1641,7 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
                                "blsp2_qup2_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1637,6 +1659,7 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
                                "blsp2_qup3_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1654,6 +1677,7 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
                                "blsp2_qup3_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1671,6 +1695,7 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
                                "blsp2_qup4_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1688,6 +1713,7 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
                                "blsp2_qup4_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1705,6 +1731,7 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
                                "blsp2_qup5_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1722,6 +1749,7 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
                                "blsp2_qup5_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1739,6 +1767,7 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
                                "blsp2_qup6_i2c_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1756,6 +1785,7 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
                                "blsp2_qup6_spi_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1786,6 +1816,7 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
                                "blsp2_uart1_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1803,6 +1834,7 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
                                "blsp2_uart2_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1820,6 +1852,7 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
                                "blsp2_uart3_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1837,6 +1870,7 @@ static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
                                "usb30_master_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1854,6 +1888,7 @@ static struct clk_branch gcc_gp1_clk = {
                                "gp1_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1871,6 +1906,7 @@ static struct clk_branch gcc_gp2_clk = {
                                "gp2_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1888,6 +1924,7 @@ static struct clk_branch gcc_gp3_clk = {
                                "gp3_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1957,6 +1994,7 @@ static struct clk_branch gcc_hmss_ahb_clk = {
                                "hmss_ahb_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1987,6 +2025,7 @@ static struct clk_branch gcc_hmss_rbcpr_clk = {
                                "hmss_rbcpr_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2088,6 +2127,7 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
                                "pcie_aux_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2157,6 +2197,7 @@ static struct clk_branch gcc_pcie_phy_aux_clk = {
                                "pcie_aux_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2174,6 +2215,7 @@ static struct clk_branch gcc_pdm2_clk = {
                                "pdm2_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2243,6 +2285,7 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
                                "sdcc2_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2273,6 +2316,7 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
                                "sdcc4_apps_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2316,6 +2360,7 @@ static struct clk_branch gcc_tsif_ref_clk = {
                                "tsif_ref_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2346,6 +2391,7 @@ static struct clk_branch gcc_ufs_axi_clk = {
                                "ufs_axi_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2441,6 +2487,7 @@ static struct clk_branch gcc_usb30_master_clk = {
                                "usb30_master_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2458,6 +2505,7 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
                                "usb30_mock_utmi_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2488,6 +2536,7 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
                                "usb3_phy_aux_clk_src",
                        },
                        .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -2495,7 +2544,7 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
 
 static struct clk_branch gcc_usb3_phy_pipe_clk = {
        .halt_reg = 0x50004,
-       .halt_check = BRANCH_HALT,
+       .halt_check = BRANCH_HALT_SKIP,
        .clkr = {
                .enable_reg = 0x50004,
                .enable_mask = BIT(0),
@@ -2910,6 +2959,10 @@ static const struct regmap_config gcc_msm8998_regmap_config = {
        .fast_io        = true,
 };
 
+static struct clk_hw *gcc_msm8998_hws[] = {
+       &xo.hw,
+};
+
 static const struct qcom_cc_desc gcc_msm8998_desc = {
        .config = &gcc_msm8998_regmap_config,
        .clks = gcc_msm8998_clocks,
@@ -2918,6 +2971,8 @@ static const struct qcom_cc_desc gcc_msm8998_desc = {
        .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
        .gdscs = gcc_msm8998_gdscs,
        .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
+       .clk_hws = gcc_msm8998_hws,
+       .num_clk_hws = ARRAY_SIZE(gcc_msm8998_hws),
 };
 
 static int gcc_msm8998_probe(struct platform_device *pdev)
@@ -2937,10 +2992,6 @@ static int gcc_msm8998_probe(struct platform_device *pdev)
        if (ret)
                return ret;
 
-       ret = devm_clk_hw_register(&pdev->dev, &xo.hw);
-       if (ret)
-               return ret;
-
        return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
 }
 
index 493e055299b48fa5f0ca1aee2bc5f14af474a805..5a62f64ada9305f358e479d08f939a084536729c 100644 (file)
@@ -2693,6 +2693,8 @@ static const struct qcom_cc_desc gcc_qcs404_desc = {
        .num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
        .resets = gcc_qcs404_resets,
        .num_resets = ARRAY_SIZE(gcc_qcs404_resets),
+       .clk_hws = gcc_qcs404_hws,
+       .num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws),
 };
 
 static const struct of_device_id gcc_qcs404_match_table[] = {
@@ -2704,7 +2706,6 @@ MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table);
 static int gcc_qcs404_probe(struct platform_device *pdev)
 {
        struct regmap *regmap;
-       int ret, i;
 
        regmap = qcom_cc_map(pdev, &gcc_qcs404_desc);
        if (IS_ERR(regmap))
@@ -2712,12 +2713,6 @@ static int gcc_qcs404_probe(struct platform_device *pdev)
 
        clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
 
-       for (i = 0; i < ARRAY_SIZE(gcc_qcs404_hws); i++) {
-               ret = devm_clk_hw_register(&pdev->dev, gcc_qcs404_hws[i]);
-               if (ret)
-                       return ret;
-       }
-
        return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
 }
 
index ba239ea4c842a42052cff211e5d0a132b6607865..8827db23066f5926894c3088ab71411346d8ec01 100644 (file)
@@ -2420,6 +2420,8 @@ static const struct qcom_cc_desc gcc_sdm660_desc = {
        .num_resets = ARRAY_SIZE(gcc_sdm660_resets),
        .gdscs = gcc_sdm660_gdscs,
        .num_gdscs = ARRAY_SIZE(gcc_sdm660_gdscs),
+       .clk_hws = gcc_sdm660_hws,
+       .num_clk_hws = ARRAY_SIZE(gcc_sdm660_hws),
 };
 
 static const struct of_device_id gcc_sdm660_match_table[] = {
@@ -2431,7 +2433,7 @@ MODULE_DEVICE_TABLE(of, gcc_sdm660_match_table);
 
 static int gcc_sdm660_probe(struct platform_device *pdev)
 {
-       int i, ret;
+       int ret;
        struct regmap *regmap;
 
        regmap = qcom_cc_map(pdev, &gcc_sdm660_desc);
@@ -2446,13 +2448,6 @@ static int gcc_sdm660_probe(struct platform_device *pdev)
        if (ret)
                return ret;
 
-       /* Register the hws */
-       for (i = 0; i < ARRAY_SIZE(gcc_sdm660_hws); i++) {
-               ret = devm_clk_hw_register(&pdev->dev, gcc_sdm660_hws[i]);
-               if (ret)
-                       return ret;
-       }
-
        return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
 }
 
index 7d4ee109435c3c5780b3663acac5358acd83effc..7235510eac944c05cd86d40ca7ae8381e90bd4d5 100644 (file)
@@ -3347,6 +3347,8 @@ static const struct qcom_cc_desc mmcc_msm8996_desc = {
        .num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
        .gdscs = mmcc_msm8996_gdscs,
        .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs),
+       .clk_hws = mmcc_msm8996_hws,
+       .num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws),
 };
 
 static const struct of_device_id mmcc_msm8996_match_table[] = {
@@ -3357,8 +3359,6 @@ MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
 
 static int mmcc_msm8996_probe(struct platform_device *pdev)
 {
-       struct device *dev = &pdev->dev;
-       int i, ret;
        struct regmap *regmap;
 
        regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
@@ -3370,12 +3370,6 @@ static int mmcc_msm8996_probe(struct platform_device *pdev)
        /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
        regmap_update_bits(regmap, 0x5054, BIT(15), 0);
 
-       for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) {
-               ret = devm_clk_hw_register(dev, mmcc_msm8996_hws[i]);
-               if (ret)
-                       return ret;
-       }
-
        return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
 }
 
index 609e363dabf81400378c84e4ce16e5a209095d8b..7ec752ed349986110f3ff1ad7ea130cc3281dc94 100644 (file)
@@ -1112,8 +1112,8 @@ static int attr_enable_set(void *data, u64 val)
 
        return val ? dfll_enable(td) : dfll_disable(td);
 }
-DEFINE_SIMPLE_ATTRIBUTE(enable_fops, attr_enable_get, attr_enable_set,
-                       "%llu\n");
+DEFINE_DEBUGFS_ATTRIBUTE(enable_fops, attr_enable_get, attr_enable_set,
+                        "%llu\n");
 
 static int attr_lock_get(void *data, u64 *val)
 {
@@ -1129,8 +1129,7 @@ static int attr_lock_set(void *data, u64 val)
 
        return val ? dfll_lock(td) :  dfll_unlock(td);
 }
-DEFINE_SIMPLE_ATTRIBUTE(lock_fops, attr_lock_get, attr_lock_set,
-                       "%llu\n");
+DEFINE_DEBUGFS_ATTRIBUTE(lock_fops, attr_lock_get, attr_lock_set, "%llu\n");
 
 static int attr_rate_get(void *data, u64 *val)
 {
@@ -1147,7 +1146,7 @@ static int attr_rate_set(void *data, u64 val)
 
        return dfll_request_rate(td, val);
 }
-DEFINE_SIMPLE_ATTRIBUTE(rate_fops, attr_rate_get, attr_rate_set, "%llu\n");
+DEFINE_DEBUGFS_ATTRIBUTE(rate_fops, attr_rate_get, attr_rate_set, "%llu\n");
 
 static int attr_registers_show(struct seq_file *s, void *data)
 {
@@ -1196,10 +1195,11 @@ static void dfll_debug_init(struct tegra_dfll *td)
        root = debugfs_create_dir("tegra_dfll_fcpu", NULL);
        td->debugfs_dir = root;
 
-       debugfs_create_file("enable", S_IRUGO | S_IWUSR, root, td, &enable_fops);
-       debugfs_create_file("lock", S_IRUGO, root, td, &lock_fops);
-       debugfs_create_file("rate", S_IRUGO, root, td, &rate_fops);
-       debugfs_create_file("registers", S_IRUGO, root, td, &attr_registers_fops);
+       debugfs_create_file_unsafe("enable", 0644, root, td,
+                                  &enable_fops);
+       debugfs_create_file_unsafe("lock", 0444, root, td, &lock_fops);
+       debugfs_create_file_unsafe("rate", 0444, root, td, &rate_fops);
+       debugfs_create_file("registers", 0444, root, td, &attr_registers_fops);
 }
 
 #else
index 6b40eb89ae190c7c05b3d12d235346662d162e3a..68bd3abaef2c677f98a89b457a0714c46e7da341 100644 (file)
@@ -13,7 +13,7 @@
 #include <linux/clk-provider.h>
 #include <linux/err.h>
 #include <linux/module.h>
-#include <linux/platform_data/clk-lpss.h>
+#include <linux/platform_data/x86/clk-lpss.h>
 #include <linux/platform_device.h>
 
 static int lpt_clk_probe(struct platform_device *pdev)
index 3658b0c14966767d01e5eadeac130e980f7fea7c..ede93a0ca1560eafadd04abd72079caaeff2a5c0 100644 (file)
 #define RPM_SMD_BIMC_GPU_A_CLK                 77
 #define RPM_SMD_QPIC_CLK                       78
 #define RPM_SMD_QPIC_CLK_A                     79
+#define RPM_SMD_LN_BB_CLK1                     80
+#define RPM_SMD_LN_BB_CLK1_A                   81
+#define RPM_SMD_LN_BB_CLK2                     82
+#define RPM_SMD_LN_BB_CLK2_A                   83
+#define RPM_SMD_LN_BB_CLK3_PIN                 84
+#define RPM_SMD_LN_BB_CLK3_A_PIN               85
+#define RPM_SMD_RF_CLK3                                86
+#define RPM_SMD_RF_CLK3_A                      87
+#define RPM_SMD_RF_CLK3_PIN                    88
+#define RPM_SMD_RF_CLK3_A_PIN                  89
 
 #endif
index e443fa9fa859020b27b666da58c6ef526e4d0b79..b7cf80a712939a1818fd1045133faafcda755271 100644 (file)
@@ -792,6 +792,9 @@ unsigned int __clk_get_enable_count(struct clk *clk);
 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
 unsigned long __clk_get_flags(struct clk *clk);
 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
+#define clk_hw_can_set_rate_parent(hw) \
+       (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
+
 bool clk_hw_is_prepared(const struct clk_hw *hw);
 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
 bool clk_hw_is_enabled(const struct clk_hw *hw);
diff --git a/include/linux/platform_data/clk-lpss.h b/include/linux/platform_data/clk-lpss.h
deleted file mode 100644 (file)
index 2390199..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Intel Low Power Subsystem clocks.
- *
- * Copyright (C) 2013, Intel Corporation
- * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
- *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __CLK_LPSS_H
-#define __CLK_LPSS_H
-
-struct lpss_clk_data {
-       const char *name;
-       struct clk *clk;
-};
-
-extern int lpt_clk_init(void);
-
-#endif /* __CLK_LPSS_H */
diff --git a/include/linux/platform_data/x86/clk-lpss.h b/include/linux/platform_data/x86/clk-lpss.h
new file mode 100644 (file)
index 0000000..2390199
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Intel Low Power Subsystem clocks.
+ *
+ * Copyright (C) 2013, Intel Corporation
+ * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
+ *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CLK_LPSS_H
+#define __CLK_LPSS_H
+
+struct lpss_clk_data {
+       const char *name;
+       struct clk *clk;
+};
+
+extern int lpt_clk_init(void);
+
+#endif /* __CLK_LPSS_H */