The Meson Timer IP block has two clock inputs:
- clk81 for using the system clock as timebase
- xtal for a timebase with 1us, 10us, 100us and 1ms resolution
The clocksource driver does not use these yet, but it's still a good
idea to add them as this describes how the hardware actually works
internally.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
+ timer_abcde: timer@9940 {
compatible = "amlogic,meson6-timer";
reg = <0x9940 0x18>;
interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
compatible = "amlogic,meson6-timer";
reg = <0x9940 0x18>;
interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
+&timer_abcde {
+ clocks = <&xtal>, <&clk81>;
+ clock-names = "xtal", "pclk";
+};
+
&uart_AO {
clocks = <&xtal>, <&clk81>, <&clk81>;
clock-names = "xtal", "pclk", "baud";
&uart_AO {
clocks = <&xtal>, <&clk81>, <&clk81>;
clock-names = "xtal", "pclk", "baud";
clocks = <&clkc CLKID_CLK81>;
};
clocks = <&clkc CLKID_CLK81>;
};
+&timer_abcde {
+ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "pclk";
+};
+
&uart_AO {
compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
&uart_AO {
compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
clock-names = "core", "clkin";
};
clock-names = "core", "clkin";
};
+&timer_abcde {
+ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "pclk";
+};
+
&uart_AO {
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
&uart_AO {
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;