Merge tag 'v4.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorOlof Johansson <olof@lixom.net>
Tue, 15 May 2018 20:52:13 +0000 (13:52 -0700)
committerOlof Johansson <olof@lixom.net>
Tue, 15 May 2018 20:52:13 +0000 (13:52 -0700)
All iommus got their clocks added and rk3399 got support for its
usb3-phy otg-port and better ajustment for the cpll child clocks.
On the board side, all rk3399 got their typec phys enabled - which
is needed for better usb support, the sapphire board got some more
properties moved to the excavator baseboard where they really belong,
kevin got a fix to use a real devicetree compatible and puma-haikou
got its hdmi port enabled.

* tag 'v4.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: enable hdmi on rk3399-puma-haikou
  arm64: dts: rockchip: use canonical compatible for touchpad/touchscreen on gru-kevin
  arm64: dts: rockchip: add clocks in iommu nodes
  arm64: dts: rockchip: add usb3-phy otg-port support for rk3399
  arm64: dts: rockchip: remove PCIe assigned-clocks in excavator baseboard
  arm64: dts: rockchip: move rk3399-sapphire PCIe to excavator baseboard
  arm64: dts: rockchip: assign clock rate for cpll child clocks on rk3399
  arm64: dts: rockchip: enable typec-phy0 for rk3399-puma-haikou
  arm64: dts: rockchip: enable typec-phy1 for rk3399-puma
  arm64: dts: rockchip: enable typec-phy for rk3399-firefly
  arm64: dts: rockchip: enable typec-phy for rk3399-sapphire

Signed-off-by: Olof Johansson <olof@lixom.net>
arch/arm64/boot/dts/rockchip/rk3328.dtsi
arch/arm64/boot/dts/rockchip/rk3368.dtsi
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
arch/arm64/boot/dts/rockchip/rk3399.dtsi

index be2bfbc6b4831a82e6567d91b036e46e583de036..b8e9da15e00c5b16ff444f681466d5454184f040 100644 (file)
                reg = <0x0 0xff330200 0 0x100>;
                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "h265e_mmu";
+               clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x0 0xff340800 0x0 0x40>;
                interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vepu_mmu";
+               clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x0 0xff350800 0x0 0x40>;
                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vpu_mmu";
+               clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "rkvdec_mmu";
+               clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x0 0xff373f00 0x0 0x100>;
                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vop_mmu";
+               clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
index 03458ac44201c7c66d0e991881ab24e292bfdee2..ad91ced786494afdb9428ea9c83adaf8e6f56e71 100644 (file)
                reg = <0x0 0xff900800 0x0 0x100>;
                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "iep_mmu";
+               clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                      <0x0 0xff915000 0x0 0x100>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "isp_mmu";
+               clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                rockchip,disable-mmu-reset;
                status = "disabled";
                reg = <0x0 0xff930300 0x0 0x100>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vop_mmu";
+               clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                      <0x0 0xff9a0480 0x0 0x40>;
                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "hevc_mmu";
+               clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vepu_mmu", "vdpu_mmu";
+               clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
index 4f28628aa09116f553b5e4fafa463bead619293e..2a352763c8489be969fa361ed0543d3163437d56 100644 (file)
        status = "okay";
 };
 
+&tcphy0 {
+       status = "okay";
+};
+
+&tcphy1 {
+       status = "okay";
+};
+
 &tsadc {
        /* tshut mode 0:CRU 1:GPIO */
        rockchip,hw-tshut-mode = <1>;
index 191a6bcb1704009830d4c3b5c0a201ffe7b2d670..82179125bfb7c78fcb0d3bc0beef209d1dbaf871 100644 (file)
@@ -255,7 +255,7 @@ ap_i2c_dig: &i2c2 {
 
 &ap_i2c_tp {
        trackpad@4a {
-               compatible = "atmel,atmel_mxt_tp";
+               compatible = "atmel,maxtouch";
                reg = <0x4a>;
                pinctrl-names = "default";
                pinctrl-0 = <&trackpad_int_l>;
@@ -271,7 +271,7 @@ ap_i2c_dig: &i2c2 {
 
 &ap_i2c_ts {
        touchscreen@4b {
-               compatible = "atmel,atmel_mxt_ts";
+               compatible = "atmel,maxtouch";
                reg = <0x4b>;
                pinctrl-names = "default";
                pinctrl-0 = <&touch_int_l>;
index 18f546f2dfd113d018e9935f2a03b18315c46efa..f49bfab75dd031640126b7c9ea50dd0c89b0a4fc 100644 (file)
                <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
                <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
                <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
-               <&cru ACLK_VIO>;
+               <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
+               <&cru ACLK_GIC_PRE>,
+               <&cru PCLK_DDR>;
        assigned-clock-rates =
                <600000000>, <800000000>,
                <1000000000>,
                <100000000>, <100000000>,
                <50000000>, <800000000>,
                <100000000>, <50000000>,
-               <400000000>;
+               <400000000>, <400000000>,
+               <200000000>,
+               <200000000>;
 };
 
 &emmc_phy {
index 7d3e8bfd51dd4f2fa9a73845ae5cbb0d51cc03b7..e0afdd8b62bd1887c106069ec987c7de30e72a87 100644 (file)
        };
 };
 
+&hdmi {
+       ddc-i2c-bus = <&i2c3>;
+       status = "okay";
+};
+
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
        status = "okay";
 };
 
+&tcphy0 {
+       status = "okay";
+};
+
 &u2phy0 {
        status = "okay";
 };
 &usb_host0_ohci {
        status = "okay";
 };
+
+&vopb {
+       status = "okay";
+};
+
+&vopb_mmu {
+       status = "okay";
+};
+
+&vopl {
+       status = "okay";
+};
+
+&vopl_mmu {
+       status = "okay";
+};
index 4a2d06abe9c1dc892e819d116f6ce3fa3241e9a9..14a0f19986390a7593cd3be04b23b0c7de1e493d 100644 (file)
        };
 };
 
+&tcphy1 {
+       status = "okay";
+};
+
 &tsadc {
        rockchip,hw-tshut-mode = <1>;
        rockchip,hw-tshut-polarity = <1>;
index 56952d1a3fb8bd271e4535f2638fe9f7e691f8e3..ad7548d3b93d50f073f0e93015a9dd107535413d 100644 (file)
        status = "okay";
 };
 
+&pcie_phy {
+       status = "okay";
+};
+
+&pcie0 {
+       ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+       num-lanes = <4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie_clkreqn_cpm>;
+       status = "okay";
+};
+
 &pinctrl {
        sdio-pwrseq {
                wifi_enable_h: wifi-enable-h {
index e5daed7d202633dd60fa4927f7fcd81093ed4393..941b627094d7f2dadcb61459fc7250dfef5634d7 100644 (file)
        gpio1830-supply = <&vcc_3v0>;
 };
 
-&pcie_phy {
-       status = "okay";
-};
-
-&pcie0 {
-       assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
-       assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
-       assigned-clock-rates = <100000000>;
-       ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
-       num-lanes = <4>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pcie_clkreqn_cpm>;
-       status = "okay";
-};
-
 &pmu_io_domains {
        pmu1830-supply = <&vcc_3v0>;
        status = "okay";
        status = "okay";
 };
 
+&tcphy0 {
+       status = "okay";
+};
+
+&tcphy1 {
+       status = "okay";
+};
+
 &tsadc {
        /* tshut mode 0:CRU 1:GPIO */
        rockchip,hw-tshut-mode = <1>;
index 4550c0f82be9021c3258ef18da864570800f1cda..e0040b648f4330909066b23fe2129e36435603d6 100644 (file)
                reg = <0x0 0xfe320000 0x0 0x4000>;
                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
                max-frequency = <150000000>;
+               assigned-clocks = <&cru HCLK_SD>;
+               assigned-clock-rates = <200000000>;
                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
                         <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                        reg = <0x0 0xfe800000 0x0 0x100000>;
                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
                        dr_mode = "otg";
-                       phys = <&u2phy0_otg>;
-                       phy-names = "usb2-phy";
+                       phys = <&u2phy0_otg>, <&tcphy0_usb3>;
+                       phy-names = "usb2-phy", "usb3-phy";
                        phy_type = "utmi_wide";
                        snps,dis_enblslpm_quirk;
                        snps,dis-u2-freeclk-exists-quirk;
                        reg = <0x0 0xfe900000 0x0 0x100000>;
                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
                        dr_mode = "otg";
-                       phys = <&u2phy1_otg>;
-                       phy-names = "usb2-phy";
+                       phys = <&u2phy1_otg>, <&tcphy1_usb3>;
+                       phy-names = "usb2-phy", "usb3-phy";
                        phy_type = "utmi_wide";
                        snps,dis_enblslpm_quirk;
                        snps,dis-u2-freeclk-exists-quirk;
                compatible = "rockchip,rk3399-cdn-dp";
                reg = <0x0 0xfec00000 0x0 0x100000>;
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
-               assigned-clocks = <&cru SCLK_DP_CORE>;
-               assigned-clock-rates = <100000000>;
+               assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
+               assigned-clock-rates = <100000000>, <200000000>;
                clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
                         <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
                clock-names = "core-clk", "pclk", "spdif", "grf";
                reg = <0x0 0xff650800 0x0 0x40>;
                interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupt-names = "vpu_mmu";
+               clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
                interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupt-names = "vdec_mmu";
+               clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x0 0xff670800 0x0 0x40>;
                interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupt-names = "iep_mmu";
+               clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                        <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
                        <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
                        <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
-                       <&cru ACLK_VIO>;
+                       <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
+                       <&cru ACLK_GIC_PRE>,
+                       <&cru PCLK_DDR>;
                assigned-clock-rates =
                         <594000000>,  <800000000>,
                        <1000000000>,
                         <100000000>,  <100000000>,
                          <50000000>, <600000000>,
                         <100000000>,   <50000000>,
-                        <400000000>;
+                        <400000000>, <400000000>,
+                        <200000000>,
+                        <200000000>;
        };
 
        grf: syscon@ff770000 {
                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupt-names = "vopl_mmu";
                clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
-               clock-names = "aclk", "hclk";
+               clock-names = "aclk", "iface";
                power-domains = <&power RK3399_PD_VOPL>;
                #iommu-cells = <0>;
                status = "disabled";
                interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupt-names = "vopb_mmu";
                clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
-               clock-names = "aclk", "hclk";
+               clock-names = "aclk", "iface";
                power-domains = <&power RK3399_PD_VOPB>;
                #iommu-cells = <0>;
                status = "disabled";
                reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupt-names = "isp0_mmu";
+               clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                rockchip,disable-mmu-reset;
                status = "disabled";
                reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
                interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupt-names = "isp1_mmu";
+               clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                rockchip,disable-mmu-reset;
                status = "disabled";