Merge tag 'am654-for-v4.19-signed' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorOlof Johansson <olof@lixom.net>
Sat, 21 Jul 2018 22:06:03 +0000 (15:06 -0700)
committerOlof Johansson <olof@lixom.net>
Sat, 21 Jul 2018 22:06:03 +0000 (15:06 -0700)
TI AM654 support for v4.19 merge window

This branch adds initial support for new Texas Instruments AM654
quad core A53 ARMv8 SoC. It's the first device for TI K3 multicore SoC
architecture.

Initially only basic devices are configured, support for more devices
will follow later on. And many of the internal devices familiar from
earlier TI SoCs should work with existing kernel device drivers.

* tag 'am654-for-v4.19-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  arm64: dts: ti: Add support for AM654 EVM base board
  soc: ti: Add Support for AM654 SoC config option
  arm64: dts: ti: Add Support for AM654 SoC
  arm64: Add support for TI's K3 Multicore SoC architecture
  dt-bindings: arm: ti: Add bindings for AM654 SoC

Signed-off-by: Olof Johansson <olof@lixom.net>
Documentation/devicetree/bindings/arm/ti/k3.txt [new file with mode: 0644]
MAINTAINERS
arch/arm64/Kconfig.platforms
arch/arm64/boot/dts/Makefile
arch/arm64/boot/dts/ti/Makefile [new file with mode: 0644]
arch/arm64/boot/dts/ti/k3-am65-main.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/ti/k3-am65.dtsi [new file with mode: 0644]
arch/arm64/boot/dts/ti/k3-am654-base-board.dts [new file with mode: 0644]
arch/arm64/boot/dts/ti/k3-am654.dtsi [new file with mode: 0644]
drivers/soc/ti/Kconfig

diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt
new file mode 100644 (file)
index 0000000..6a059ca
--- /dev/null
@@ -0,0 +1,23 @@
+Texas Instruments K3 Multicore SoC architecture device tree bindings
+--------------------------------------------------------------------
+
+Platforms based on Texas Instruments K3 Multicore SoC architecture
+shall follow the following scheme:
+
+SoCs
+----
+
+Each device tree root node must specify which exact SoC in K3 Multicore SoC
+architecture it uses, using one of the following compatible values:
+
+- AM654
+  compatible = "ti,am654";
+
+Boards
+------
+
+In addition, each device tree root node must specify which one or more
+of the following board-specific compatible values:
+
+- AM654 EVM
+  compatible = "ti,am654-evm", "ti,am654";
index 07d1576fc766069866471028009a17bf4c281db0..5f9bf6df6724d77198b391f678dc5311d735673b 100644 (file)
@@ -2087,6 +2087,15 @@ L:       linux-kernel@vger.kernel.org
 S:     Maintained
 F:     drivers/memory/*emif*
 
+ARM/TEXAS INSTRUMENTS K3 ARCHITECTURE
+M:     Tero Kristo <t-kristo@ti.com>
+M:     Nishanth Menon <nm@ti.com>
+L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:     Supported
+F:     Documentation/devicetree/bindings/arm/ti/k3.txt
+F:     arch/arm64/boot/dts/ti/Makefile
+F:     arch/arm64/boot/dts/ti/k3-*
+
 ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE
 M:     Santosh Shilimkar <ssantosh@kernel.org>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
index d5aeac351fc3a776ee840f09680f43a864b5307c..52df25bf4f8ce644c084023dd90fc1f88ed5a33f 100644 (file)
@@ -71,6 +71,13 @@ config ARCH_EXYNOS
        help
          This enables support for ARMv8 based Samsung Exynos SoC family.
 
+config ARCH_K3
+       bool "Texas Instruments Inc. K3 multicore SoC architecture"
+       select PM_GENERIC_DOMAINS if PM
+       help
+         This enables support for Texas Instruments' K3 multicore SoC
+         architecture.
+
 config ARCH_LAYERSCAPE
        bool "ARMv8 based Freescale Layerscape SoC family"
        select EDAC_SUPPORT
index 3543bc32455339cf22d7ca70f2aef5a3de159cba..4690364d584bf4e6a9bf43e8b8788fb8b1c5f0cf 100644 (file)
@@ -23,5 +23,6 @@ subdir-y += rockchip
 subdir-y += socionext
 subdir-y += sprd
 subdir-y += synaptics
+subdir-y += ti
 subdir-y += xilinx
 subdir-y += zte
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
new file mode 100644 (file)
index 0000000..63e619d
--- /dev/null
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Make file to build device tree binaries for boards based on
+# Texas Instruments Inc processors
+#
+# Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+#
+
+dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
new file mode 100644 (file)
index 0000000..2409344
--- /dev/null
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&cbass_main {
+       gic500: interrupt-controller@1800000 {
+               compatible = "arm,gic-v3";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0x01800000 0x10000>,     /* GICD */
+                     <0x01880000 0x90000>;     /* GICR */
+               /*
+                * vcpumntirq:
+                * virtual CPU interface maintenance interrupt
+                */
+               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+               gic_its: gic-its@18200000 {
+                       compatible = "arm,gic-v3-its";
+                       reg = <0x01820000 0x10000>;
+                       msi-controller;
+                       #msi-cells = <1>;
+               };
+       };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
new file mode 100644 (file)
index 0000000..cede1fa
--- /dev/null
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC Family
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+       model = "Texas Instruments K3 AM654 SoC";
+       compatible = "ti,am654";
+       interrupt-parent = <&gic500>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       chosen { };
+
+       firmware {
+               optee {
+                       compatible = "linaro,optee-tz";
+                       method = "smc";
+               };
+
+               psci: psci {
+                       compatible = "arm,psci-1.0";
+                       method = "smc";
+               };
+       };
+
+       a53_timer0: timer-cl0-cpu0 {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+       };
+
+       pmu: pmu {
+               compatible = "arm,armv8-pmuv3";
+               /* Recommendation from GIC500 TRM Table A.3 */
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       cbass_main: interconnect@100000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */
+                        <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */
+                        <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */
+                        <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */
+                        <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */
+                        /* MCUSS Range */
+                        <0x28380000 0x00 0x28380000 0x03880000>,
+                        <0x40200000 0x00 0x40200000 0x00900100>,
+                        <0x42040000 0x00 0x42040000 0x03ac2400>,
+                        <0x45100000 0x00 0x45100000 0x00c24000>,
+                        <0x46000000 0x00 0x46000000 0x00200000>,
+                        <0x47000000 0x00 0x47000000 0x00068400>;
+
+               cbass_mcu: interconnect@28380000 {
+                       compatible = "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/
+                                <0x40200000 0x40200000 0x00900100>, /* First peripheral window */
+                                <0x42040000 0x42040000 0x03ac2400>, /* WKUP */
+                                <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */
+                                <0x46000000 0x46000000 0x00200000>, /* CPSW */
+                                <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */
+
+                       cbass_wakeup: interconnect@42040000 {
+                               compatible = "simple-bus";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               /* WKUP  Basic peripherals */
+                               ranges = <0x42040000 0x42040000 0x03ac2400>;
+                       };
+               };
+       };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-am65-main.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
new file mode 100644 (file)
index 0000000..af6956f
--- /dev/null
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am654.dtsi"
+
+/ {
+       compatible =  "ti,am654-evm", "ti,am654";
+       model = "Texas Instruments AM654 Base Board";
+
+       chosen {
+               stdout-path = "serial2:115200n8";
+               bootargs = "earlycon=ns16550a,mmio32,0x02800000";
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               /* 4G RAM */
+               reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+                     <0x00000008 0x80000000 0x00000000 0x80000000>;
+       };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               secure_ddr: secure_ddr@9e800000 {
+                       reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
+                       alignment = <0x1000>;
+                       no-map;
+               };
+       };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi
new file mode 100644 (file)
index 0000000..2affa6f
--- /dev/null
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC family in Quad core configuration
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "k3-am65.dtsi"
+
+/ {
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cpu-map {
+                       cluster0: cluster0 {
+                               core0 {
+                                       cpu = <&cpu0>;
+                               };
+
+                               core1 {
+                                       cpu = <&cpu1>;
+                               };
+                       };
+
+                       cluster1: cluster1 {
+                               core0 {
+                                       cpu = <&cpu2>;
+                               };
+
+                               core1 {
+                                       cpu = <&cpu3>;
+                               };
+                       };
+               };
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x000>;
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               cpu1: cpu@1 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x001>;
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               cpu2: cpu@100 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x100>;
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&L2_1>;
+               };
+
+               cpu3: cpu@101 {
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x101>;
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&L2_1>;
+               };
+       };
+
+       L2_0: l2-cache0 {
+               compatible = "cache";
+               cache-level = <2>;
+               cache-size = <0x80000>;
+               cache-line-size = <64>;
+               cache-sets = <512>;
+               next-level-cache = <&msmc_l3>;
+       };
+
+       L2_1: l2-cache1 {
+               compatible = "cache";
+               cache-level = <2>;
+               cache-size = <0x80000>;
+               cache-line-size = <64>;
+               cache-sets = <512>;
+               next-level-cache = <&msmc_l3>;
+       };
+
+       msmc_l3: l3-cache0 {
+               compatible = "cache";
+               cache-level = <3>;
+       };
+};
index 92770d84a2885844b98bf7ec015c06c2b62c1553..be4570baad96c0c1a1bd5c1d9eb1d0d70e4da97d 100644 (file)
@@ -1,3 +1,17 @@
+# 64-bit ARM SoCs from TI
+if ARM64
+
+if ARCH_K3
+
+config ARCH_K3_AM6_SOC
+       bool "K3 AM6 SoC"
+       help
+         Enable support for TI's AM6 SoC Family support
+
+endif
+
+endif
+
 #
 # TI SOC drivers
 #