Merge tag 'mtd/for-4.20' of git://git.infradead.org/linux-mtd
authorLinus Torvalds <torvalds@linux-foundation.org>
Tue, 23 Oct 2018 00:09:22 +0000 (01:09 +0100)
committerLinus Torvalds <torvalds@linux-foundation.org>
Tue, 23 Oct 2018 00:09:22 +0000 (01:09 +0100)
Pull mtd updates from Boris Brezillon:
 "SPI NOR core changes:
   - Support non-uniform erase size
   - Support controllers with limited TX fifo size

 Driver changes:
   - m25p80: Re-issue a WREN command after each write access
   - cadence: Pass a proper dir value to dma_[un]map_single()
   - fsl-qspi: Check fsl_qspi_get_seqid() return val make sure 4B
     addressing opcodes are properly handled
   - intel-spi: Add a new PCI entry for Ice Lake

 Raw NAND core changes:
   - Two batchs of cleanups of the NAND API, including:
      * Deprecating a lot of interfaces (now replaced by ->exec_op()).
      * Moving code in separate drivers (JEDEC, ONFI), in private files
        (internals), in platform drivers, etc.
      * Functions/structures reordering.
      * Exclusive use of the nand_chip structure instead of the MTD one
        all across the subsystem.
   - Addition of the nand_wait_readrdy/rdy_op() helpers.

 Raw NAND controllers drivers changes:
   - Various coccinelle patches.
   - Marvell:
      * Use regmap_update_bits() for syscon access.
      * More documentation.
      * BCH failure path rework.
      * More layouts to be supported.
      * IRQ handler complete() condition fixed.
   - Fsl_ifc:
      * SRAM initialization fixed for newer controller versions.
   - Denali:
      * Fix licenses mismatch and use a SPDX tag.
      * Set SPARE_AREA_SKIP_BYTES register to 8 if unset.
   - Qualcomm:
      * Do not include dma-direct.h.
   - Docg4:
      * Removed.
   - Ams-delta:
      * Use of a GPIO lookup table
      * Internal machinery changes.

 Raw NAND chip drivers changes:
   - Toshiba:
      * Add support for Toshiba memory BENAND
      * Pass a single nand_chip object to the status helper.
   - ESMT:
      * New driver to retrieve the ECC requirements from the 5th ID
        byte.

  MTD changes:
   - physmap cleanups/fixe
   - gpio-addr-flash cleanups/fixes"

* tag 'mtd/for-4.20' of git://git.infradead.org/linux-mtd: (93 commits)
  jffs2: free jffs2_sb_info through jffs2_kill_sb()
  mtd: spi-nor: fsl-quadspi: fix read error for flash size larger than 16MB
  mtd: spi-nor: intel-spi: Add support for Intel Ice Lake SPI serial flash
  mtd: maps: gpio-addr-flash: Convert to gpiod
  mtd: maps: gpio-addr-flash: Replace array with an integer
  mtd: maps: gpio-addr-flash: Use order instead of size
  mtd: spi-nor: fsl-quadspi: Don't let -EINVAL on the bus
  mtd: devices: m25p80: Make sure WRITE_EN is issued before each write
  mtd: spi-nor: Support controllers with limited TX FIFO size
  mtd: spi-nor: cadence-quadspi: Use proper enum for dma_[un]map_single
  mtd: spi-nor: parse SFDP Sector Map Parameter Table
  mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories
  mtd: rawnand: marvell: fix the IRQ handler complete() condition
  mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES register to 8 if unset
  mtd: rawnand: r852: fix spelling mistake "card_registred" -> "card_registered"
  mtd: rawnand: toshiba: Pass a single nand_chip object to the status helper
  mtd: maps: gpio-addr-flash: Use devm_* functions
  mtd: maps: gpio-addr-flash: Fix ioremapped size
  mtd: maps: gpio-addr-flash: Replace custom printk
  mtd: physmap_of: Release resources on error
  ...

119 files changed:
Documentation/driver-api/mtdnand.rst
Documentation/mtd/nand/pxa3xx-nand.txt [deleted file]
arch/arm/mach-ep93xx/snappercl15.c
arch/arm/mach-ep93xx/ts72xx.c
arch/arm/mach-imx/mach-qong.c
arch/arm/mach-ixp4xx/ixdp425-setup.c
arch/arm/mach-omap1/board-fsample.c
arch/arm/mach-omap1/board-h2.c
arch/arm/mach-omap1/board-h3.c
arch/arm/mach-omap1/board-nand.c
arch/arm/mach-omap1/board-perseus2.c
arch/arm/mach-omap1/common.h
arch/arm/mach-orion5x/ts78xx-setup.c
arch/arm/mach-pxa/balloon3.c
arch/arm/mach-pxa/em-x270.c
arch/arm/mach-pxa/palmtreo.c
arch/arm/mach-pxa/palmtx.c
arch/mips/alchemy/devboards/db1200.c
arch/mips/alchemy/devboards/db1300.c
arch/mips/alchemy/devboards/db1550.c
arch/mips/netlogic/xlr/platform-flash.c
arch/mips/pnx833x/common/platform.c
arch/mips/rb532/devices.c
arch/sh/boards/mach-migor/setup.c
drivers/mtd/devices/m25p80.c
drivers/mtd/maps/gpio-addr-flash.c
drivers/mtd/maps/physmap_of_core.c
drivers/mtd/maps/physmap_of_gemini.c
drivers/mtd/nand/raw/Kconfig
drivers/mtd/nand/raw/Makefile
drivers/mtd/nand/raw/ams-delta.c
drivers/mtd/nand/raw/atmel/nand-controller.c
drivers/mtd/nand/raw/au1550nd.c
drivers/mtd/nand/raw/bcm47xxnflash/main.c
drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c
drivers/mtd/nand/raw/brcmnand/brcmnand.c
drivers/mtd/nand/raw/cafe_nand.c
drivers/mtd/nand/raw/cmx270_nand.c
drivers/mtd/nand/raw/cs553x_nand.c
drivers/mtd/nand/raw/davinci_nand.c
drivers/mtd/nand/raw/denali.c
drivers/mtd/nand/raw/denali.h
drivers/mtd/nand/raw/denali_dt.c
drivers/mtd/nand/raw/denali_pci.c
drivers/mtd/nand/raw/diskonchip.c
drivers/mtd/nand/raw/docg4.c [deleted file]
drivers/mtd/nand/raw/fsl_elbc_nand.c
drivers/mtd/nand/raw/fsl_ifc_nand.c
drivers/mtd/nand/raw/fsl_upm.c
drivers/mtd/nand/raw/fsmc_nand.c
drivers/mtd/nand/raw/gpio.c
drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
drivers/mtd/nand/raw/hisi504_nand.c
drivers/mtd/nand/raw/internals.h [new file with mode: 0644]
drivers/mtd/nand/raw/jz4740_nand.c
drivers/mtd/nand/raw/jz4780_nand.c
drivers/mtd/nand/raw/lpc32xx_mlc.c
drivers/mtd/nand/raw/lpc32xx_slc.c
drivers/mtd/nand/raw/marvell_nand.c
drivers/mtd/nand/raw/mpc5121_nfc.c
drivers/mtd/nand/raw/mtk_nand.c
drivers/mtd/nand/raw/mxc_nand.c
drivers/mtd/nand/raw/nand_amd.c
drivers/mtd/nand/raw/nand_base.c
drivers/mtd/nand/raw/nand_bbt.c
drivers/mtd/nand/raw/nand_bch.c
drivers/mtd/nand/raw/nand_ecc.c
drivers/mtd/nand/raw/nand_esmt.c [new file with mode: 0644]
drivers/mtd/nand/raw/nand_hynix.c
drivers/mtd/nand/raw/nand_ids.c
drivers/mtd/nand/raw/nand_jedec.c [new file with mode: 0644]
drivers/mtd/nand/raw/nand_legacy.c [new file with mode: 0644]
drivers/mtd/nand/raw/nand_macronix.c
drivers/mtd/nand/raw/nand_micron.c
drivers/mtd/nand/raw/nand_onfi.c [new file with mode: 0644]
drivers/mtd/nand/raw/nand_samsung.c
drivers/mtd/nand/raw/nand_timings.c
drivers/mtd/nand/raw/nand_toshiba.c
drivers/mtd/nand/raw/nandsim.c
drivers/mtd/nand/raw/ndfc.c
drivers/mtd/nand/raw/nuc900_nand.c
drivers/mtd/nand/raw/omap2.c
drivers/mtd/nand/raw/orion_nand.c
drivers/mtd/nand/raw/oxnas_nand.c
drivers/mtd/nand/raw/pasemi_nand.c
drivers/mtd/nand/raw/plat_nand.c
drivers/mtd/nand/raw/qcom_nandc.c
drivers/mtd/nand/raw/r852.c
drivers/mtd/nand/raw/r852.h
drivers/mtd/nand/raw/s3c2410.c
drivers/mtd/nand/raw/sh_flctl.c
drivers/mtd/nand/raw/sharpsl.c
drivers/mtd/nand/raw/sm_common.c
drivers/mtd/nand/raw/socrates_nand.c
drivers/mtd/nand/raw/sunxi_nand.c
drivers/mtd/nand/raw/tango_nand.c
drivers/mtd/nand/raw/tegra_nand.c
drivers/mtd/nand/raw/tmio_nand.c
drivers/mtd/nand/raw/txx9ndfmc.c
drivers/mtd/nand/raw/vf610_nfc.c
drivers/mtd/nand/raw/xway_nand.c
drivers/mtd/sm_ftl.c
drivers/mtd/spi-nor/cadence-quadspi.c
drivers/mtd/spi-nor/fsl-quadspi.c
drivers/mtd/spi-nor/intel-spi-pci.c
drivers/mtd/spi-nor/spi-nor.c
drivers/mtd/tests/mtd_nandecctest.c
drivers/staging/mt29f_spinand/mt29f_spinand.c
fs/jffs2/super.c
include/linux/fsl_ifc.h
include/linux/mtd/jedec.h [new file with mode: 0644]
include/linux/mtd/nand_bch.h
include/linux/mtd/nand_ecc.h
include/linux/mtd/onfi.h [new file with mode: 0644]
include/linux/mtd/platnand.h [new file with mode: 0644]
include/linux/mtd/rawnand.h
include/linux/mtd/spi-nor.h

index c55a6034c397d4e12fc80d064c3f730bc079cdc1..55447659b81fa41b9bcfac13402109ffc421e9ad 100644 (file)
@@ -180,10 +180,10 @@ by a chip select decoder.
     {
         struct nand_chip *this = mtd_to_nand(mtd);
         switch(cmd){
-            case NAND_CTL_SETCLE: this->IO_ADDR_W |= CLE_ADRR_BIT;  break;
-            case NAND_CTL_CLRCLE: this->IO_ADDR_W &= ~CLE_ADRR_BIT; break;
-            case NAND_CTL_SETALE: this->IO_ADDR_W |= ALE_ADRR_BIT;  break;
-            case NAND_CTL_CLRALE: this->IO_ADDR_W &= ~ALE_ADRR_BIT; break;
+            case NAND_CTL_SETCLE: this->legacy.IO_ADDR_W |= CLE_ADRR_BIT;  break;
+            case NAND_CTL_CLRCLE: this->legacy.IO_ADDR_W &= ~CLE_ADRR_BIT; break;
+            case NAND_CTL_SETALE: this->legacy.IO_ADDR_W |= ALE_ADRR_BIT;  break;
+            case NAND_CTL_CLRALE: this->legacy.IO_ADDR_W &= ~ALE_ADRR_BIT; break;
         }
     }
 
@@ -197,7 +197,7 @@ to read back the state of the pin. The function has no arguments and
 should return 0, if the device is busy (R/B pin is low) and 1, if the
 device is ready (R/B pin is high). If the hardware interface does not
 give access to the ready busy pin, then the function must not be defined
-and the function pointer this->dev_ready is set to NULL.
+and the function pointer this->legacy.dev_ready is set to NULL.
 
 Init function
 -------------
@@ -235,18 +235,18 @@ necessary information about the device.
         }
 
         /* Set address of NAND IO lines */
-        this->IO_ADDR_R = baseaddr;
-        this->IO_ADDR_W = baseaddr;
+        this->legacy.IO_ADDR_R = baseaddr;
+        this->legacy.IO_ADDR_W = baseaddr;
         /* Reference hardware control function */
         this->hwcontrol = board_hwcontrol;
         /* Set command delay time, see datasheet for correct value */
-        this->chip_delay = CHIP_DEPENDEND_COMMAND_DELAY;
+        this->legacy.chip_delay = CHIP_DEPENDEND_COMMAND_DELAY;
         /* Assign the device ready function, if available */
-        this->dev_ready = board_dev_ready;
+        this->legacy.dev_ready = board_dev_ready;
         this->eccmode = NAND_ECC_SOFT;
 
         /* Scan to find existence of the device */
-        if (nand_scan (board_mtd, 1)) {
+        if (nand_scan (this, 1)) {
             err = -ENXIO;
             goto out_ior;
         }
@@ -277,7 +277,7 @@ unregisters the partitions in the MTD layer.
     static void __exit board_cleanup (void)
     {
         /* Release resources, unregister device */
-        nand_release (board_mtd);
+        nand_release (mtd_to_nand(board_mtd));
 
         /* unmap physical address */
         iounmap(baseaddr);
@@ -336,17 +336,17 @@ connected to an address decoder.
         struct nand_chip *this = mtd_to_nand(mtd);
 
         /* Deselect all chips */
-        this->IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK;
-        this->IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK;
+        this->legacy.IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK;
+        this->legacy.IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK;
         switch (chip) {
         case 0:
-            this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0;
-            this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0;
+            this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0;
+            this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0;
             break;
         ....
         case n:
-            this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn;
-            this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn;
+            this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn;
+            this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn;
             break;
         }
     }
diff --git a/Documentation/mtd/nand/pxa3xx-nand.txt b/Documentation/mtd/nand/pxa3xx-nand.txt
deleted file mode 100644 (file)
index 1074cbc..0000000
+++ /dev/null
@@ -1,113 +0,0 @@
-
-About this document
-===================
-
-Some notes about Marvell's NAND controller available in PXA and Armada 370/XP
-SoC (aka NFCv1 and NFCv2), with an emphasis on the latter.
-
-NFCv2 controller background
-===========================
-
-The controller has a 2176 bytes FIFO buffer. Therefore, in order to support
-larger pages, I/O operations on 4 KiB and 8 KiB pages is done with a set of
-chunked transfers.
-
-For instance, if we choose a 2048 data chunk and set "BCH" ECC (see below)
-we'll have this layout in the pages:
-
-  ------------------------------------------------------------------------------
-  | 2048B data | 32B spare | 30B ECC || 2048B data | 32B spare | 30B ECC | ... |
-  ------------------------------------------------------------------------------
-
-The driver reads the data and spare portions independently and builds an internal
-buffer with this layout (in the 4 KiB page case):
-
-  ------------------------------------------
-  |     4096B data     |     64B spare     |
-  ------------------------------------------
-
-Also, for the READOOB command the driver disables the ECC and reads a 'spare + ECC'
-OOB, one per chunk read.
-
-  -------------------------------------------------------------------
-  |     4096B data     |  32B spare | 30B ECC | 32B spare | 30B ECC |
-  -------------------------------------------------------------------
-
-So, in order to achieve reading (for instance), we issue several READ0 commands
-(with some additional controller-specific magic) and read two chunks of 2080B
-(2048 data + 32 spare) each.
-The driver accommodates this data to expose the NAND core a contiguous buffer
-(4096 data + spare) or (4096 + spare + ECC + spare + ECC).
-
-ECC
-===
-
-The controller has built-in hardware ECC capabilities. In addition it is
-configurable between two modes: 1) Hamming, 2) BCH.
-
-Note that the actual BCH mode: BCH-4 or BCH-8 will depend on the way
-the controller is configured to transfer the data.
-
-In the BCH mode the ECC code will be calculated for each transferred chunk
-and expected to be located (when reading/programming) right after the spare
-bytes as the figure above shows.
-
-So, repeating the above scheme, a 2048B data chunk will be followed by 32B
-spare, and then the ECC controller will read/write the ECC code (30B in
-this case):
-
-  ------------------------------------
-  | 2048B data | 32B spare | 30B ECC |
-  ------------------------------------
-
-If the ECC mode is 'BCH' then the ECC is *always* 30 bytes long.
-If the ECC mode is 'Hamming' the ECC is 6 bytes long, for each 512B block.
-So in Hamming mode, a 2048B page will have a 24B ECC.
-
-Despite all of the above, the controller requires the driver to only read or
-write in multiples of 8-bytes, because the data buffer is 64-bits.
-
-OOB
-===
-
-Because of the above scheme, and because the "spare" OOB is really located in
-the middle of a page, spare OOB cannot be read or write independently of the
-data area. In other words, in order to read the OOB (aka READOOB), the entire
-page (aka READ0) has to be read.
-
-In the same sense, in order to write to the spare OOB the driver has to write
-an *entire* page.
-
-Factory bad blocks handling
-===========================
-
-Given the ECC BCH requires to layout the device's pages in a split
-data/OOB/data/OOB way, the controller has a view of the flash page that's
-different from the specified (aka the manufacturer's) view. In other words,
-
-Factory view:
-
-  -----------------------------------------------
-  |                    Data           |x  OOB   |
-  -----------------------------------------------
-
-Driver's view:
-
-  -----------------------------------------------
-  |      Data      | OOB |      Data   x  | OOB |
-  -----------------------------------------------
-
-It can be seen from the above, that the factory bad block marker must be
-searched within the 'data' region, and not in the usual OOB region.
-
-In addition, this means under regular usage the driver will write such
-position (since it belongs to the data region) and every used block is
-likely to be marked as bad.
-
-For this reason, marking the block as bad in the OOB is explicitly
-disabled by using the NAND_BBT_NO_OOB_BBM option in the driver. The rationale
-for this is that there's no point in marking a block as bad, because good
-blocks are also 'marked as bad' (in the OOB BBM sense) under normal usage.
-
-Instead, the driver relies on the bad block table alone, and should only perform
-the bad block scan on the very first time (when the device hasn't been used).
index 45940c1d778789f3b76a5e465c787ab05b22682f..cf0cb58b3454009d6d41fbf1c5d0431674dca5e9 100644 (file)
@@ -23,8 +23,7 @@
 #include <linux/i2c.h>
 #include <linux/fb.h>
 
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/rawnand.h>
+#include <linux/mtd/platnand.h>
 
 #include <mach/hardware.h>
 #include <linux/platform_data/video-ep93xx.h>
 #define SNAPPERCL15_NAND_CEN   (1 << 11) /* Chip enable (active low) */
 #define SNAPPERCL15_NAND_RDY   (1 << 14) /* Device ready */
 
-#define NAND_CTRL_ADDR(chip)   (chip->IO_ADDR_W + 0x40)
+#define NAND_CTRL_ADDR(chip)   (chip->legacy.IO_ADDR_W + 0x40)
 
-static void snappercl15_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+static void snappercl15_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
                                      unsigned int ctrl)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        static u16 nand_state = SNAPPERCL15_NAND_WPN;
        u16 set;
 
@@ -70,13 +68,12 @@ static void snappercl15_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
        }
 
        if (cmd != NAND_CMD_NONE)
-               __raw_writew((cmd & 0xff) | nand_state, chip->IO_ADDR_W);
+               __raw_writew((cmd & 0xff) | nand_state,
+                            chip->legacy.IO_ADDR_W);
 }
 
-static int snappercl15_nand_dev_ready(struct mtd_info *mtd)
+static int snappercl15_nand_dev_ready(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-
        return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY);
 }
 
index c089a2a4fe307150a3b4066b9bc7447aae8788bd..c6a533699b003bda6842daacc27a0fa320c63a9f 100644 (file)
@@ -16,8 +16,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/mmc_spi.h>
@@ -76,13 +75,11 @@ static void __init ts72xx_map_io(void)
 #define TS72XX_NAND_CONTROL_ADDR_LINE  22      /* 0xN0400000 */
 #define TS72XX_NAND_BUSY_ADDR_LINE     23      /* 0xN0800000 */
 
-static void ts72xx_nand_hwcontrol(struct mtd_info *mtd,
+static void ts72xx_nand_hwcontrol(struct nand_chip *chip,
                                  int cmd, unsigned int ctrl)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-
        if (ctrl & NAND_CTRL_CHANGE) {
-               void __iomem *addr = chip->IO_ADDR_R;
+               void __iomem *addr = chip->legacy.IO_ADDR_R;
                unsigned char bits;
 
                addr += (1 << TS72XX_NAND_CONTROL_ADDR_LINE);
@@ -96,13 +93,12 @@ static void ts72xx_nand_hwcontrol(struct mtd_info *mtd,
        }
 
        if (cmd != NAND_CMD_NONE)
-               __raw_writeb(cmd, chip->IO_ADDR_W);
+               __raw_writeb(cmd, chip->legacy.IO_ADDR_W);
 }
 
-static int ts72xx_nand_device_ready(struct mtd_info *mtd)
+static int ts72xx_nand_device_ready(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-       void __iomem *addr = chip->IO_ADDR_R;
+       void __iomem *addr = chip->legacy.IO_ADDR_R;
 
        addr += (1 << TS72XX_NAND_BUSY_ADDR_LINE);
 
index 42a700053103ebf57b9682a5e6dc9da05629d8a7..5c5df8ca38dd92eb179ebad5879506797d5a3b7f 100644 (file)
@@ -18,7 +18,7 @@
 #include <linux/memory.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mtd/rawnand.h>
+#include <linux/mtd/platnand.h>
 #include <linux/gpio.h>
 
 #include <asm/mach-types.h>
@@ -129,30 +129,29 @@ static void qong_init_nor_mtd(void)
 /*
  * Hardware specific access to control-lines
  */
-static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void qong_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
+                              unsigned int ctrl)
 {
-       struct nand_chip *nand_chip = mtd_to_nand(mtd);
-
        if (cmd == NAND_CMD_NONE)
                return;
 
        if (ctrl & NAND_CLE)
-               writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
+               writeb(cmd, nand_chip->legacy.IO_ADDR_W + (1 << 24));
        else
-               writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
+               writeb(cmd, nand_chip->legacy.IO_ADDR_W + (1 << 23));
 }
 
 /*
  * Read the Device Ready pin.
  */
-static int qong_nand_device_ready(struct mtd_info *mtd)
+static int qong_nand_device_ready(struct nand_chip *chip)
 {
        return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
 }
 
-static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
+static void qong_nand_select_chip(struct nand_chip *chip, int cs)
 {
-       if (chip >= 0)
+       if (cs >= 0)
                gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
        else
                gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
index 3ec829d52cdd2143a76113f9380cd54696b23395..57d7df79d8389b8373d1e0c24a3133f26ba70643 100644 (file)
@@ -20,6 +20,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
 #include <asm/types.h>
@@ -75,9 +76,8 @@ static struct mtd_partition ixdp425_partitions[] = {
 };
 
 static void
-ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+ixdp425_flash_nand_cmd_ctrl(struct nand_chip *this, int cmd, unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        int offset = (int)nand_get_controller_data(this);
 
        if (ctrl & NAND_CTRL_CHANGE) {
@@ -93,7 +93,7 @@ ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
        }
 
        if (cmd != NAND_CMD_NONE)
-               writeb(cmd, this->IO_ADDR_W + offset);
+               writeb(cmd, this->legacy.IO_ADDR_W + offset);
 }
 
 static struct platform_nand_data ixdp425_flash_nand_data = {
index 69bd601feb83d8ff04e1b8f6bbf24bc3fd86b217..4a0a66815ca0059e39183394a1c73b987e5b9650 100644 (file)
@@ -16,8 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/mtd/physmap.h>
 #include <linux/input.h>
 #include <linux/smc91x.h>
@@ -186,7 +185,7 @@ static struct platform_device nor_device = {
 
 #define FSAMPLE_NAND_RB_GPIO_PIN       62
 
-static int nand_dev_ready(struct mtd_info *mtd)
+static int nand_dev_ready(struct nand_chip *chip)
 {
        return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
 }
index 9aeb8ad8c3270cb5761f2a82408f2ba96e9c1a63..9d9a6ca15df0d49728bd625518bd6f3862db4d44 100644 (file)
@@ -24,8 +24,7 @@
 #include <linux/delay.h>
 #include <linux/i2c.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/mtd/physmap.h>
 #include <linux/input.h>
 #include <linux/mfd/tps65010.h>
@@ -182,7 +181,7 @@ static struct mtd_partition h2_nand_partitions[] = {
 
 #define H2_NAND_RB_GPIO_PIN    62
 
-static int h2_nand_dev_ready(struct mtd_info *mtd)
+static int h2_nand_dev_ready(struct nand_chip *chip)
 {
        return gpio_get_value(H2_NAND_RB_GPIO_PIN);
 }
index 2edcd6356f2d635011d55b1e77f04ef44aa1cd13..cd6e02c5c01a35a1b8235cbcaa8f70c038cd36da 100644 (file)
@@ -23,7 +23,7 @@
 #include <linux/workqueue.h>
 #include <linux/i2c.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
+#include <linux/mtd/platnand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/input.h>
@@ -185,7 +185,7 @@ static struct mtd_partition nand_partitions[] = {
 
 #define H3_NAND_RB_GPIO_PIN    10
 
-static int nand_dev_ready(struct mtd_info *mtd)
+static int nand_dev_ready(struct nand_chip *chip)
 {
        return gpio_get_value(H3_NAND_RB_GPIO_PIN);
 }
index 1bffbb4e050f2c1823cfaa18c7829deecad3c634..20923eb2d9b6bae15efebce2b9971429d568b822 100644 (file)
@@ -20,9 +20,8 @@
 
 #include "common.h"
 
-void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+void omap1_nand_cmd_ctl(struct nand_chip *this, int cmd, unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        unsigned long mask;
 
        if (cmd == NAND_CMD_NONE)
@@ -32,6 +31,6 @@ void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
        if (ctrl & NAND_ALE)
                mask |= 0x04;
 
-       writeb(cmd, this->IO_ADDR_W + mask);
+       writeb(cmd, this->legacy.IO_ADDR_W + mask);
 }
 
index b4951eb8289884549bb67f00e5a17bf8a05cab5e..06a584fef5b86ff05e72eae73459aa29cb65d81a 100644 (file)
@@ -16,8 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/mtd/physmap.h>
 #include <linux/input.h>
 #include <linux/smc91x.h>
@@ -144,7 +143,7 @@ static struct platform_device nor_device = {
 
 #define P2_NAND_RB_GPIO_PIN    62
 
-static int nand_dev_ready(struct mtd_info *mtd)
+static int nand_dev_ready(struct nand_chip *chip)
 {
        return gpio_get_value(P2_NAND_RB_GPIO_PIN);
 }
index c6537d2c28597ac1f8296322085d591198d508f4..504b959ba5cfc8378bd54caf9d11bcb8a86591e3 100644 (file)
@@ -26,7 +26,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP1_COMMON_H
 #define __ARCH_ARM_MACH_OMAP1_COMMON_H
 
-#include <linux/mtd/mtd.h>
 #include <linux/platform_data/i2c-omap.h>
 #include <linux/reboot.h>
 
@@ -82,7 +81,8 @@ void omap1_restart(enum reboot_mode, const char *);
 
 extern void __init omap_check_revision(void);
 
-extern void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
+struct nand_chip;
+extern void omap1_nand_cmd_ctl(struct nand_chip *this, int cmd,
                               unsigned int ctrl);
 
 extern void omap1_timer_init(void);
index 94778739e38f0cbf85535525c478a19b2c12fbad..fda9b75c3a333678518b235b0ff0ddfb888eedec 100644 (file)
@@ -16,8 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/timeriomem-rng.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -131,11 +130,9 @@ static void ts78xx_ts_rtc_unload(void)
  * NAND_CLE: bit 1 -> bit 1
  * NAND_ALE: bit 2 -> bit 0
  */
-static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
-                       unsigned int ctrl)
+static void ts78xx_ts_nand_cmd_ctrl(struct nand_chip *this, int cmd,
+                                   unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-
        if (ctrl & NAND_CTRL_CHANGE) {
                unsigned char bits;
 
@@ -147,19 +144,18 @@ static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
        }
 
        if (cmd != NAND_CMD_NONE)
-               writeb(cmd, this->IO_ADDR_W);
+               writeb(cmd, this->legacy.IO_ADDR_W);
 }
 
-static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
+static int ts78xx_ts_nand_dev_ready(struct nand_chip *chip)
 {
        return readb(TS_NAND_CTRL) & 0x20;
 }
 
-static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
-                       const uint8_t *buf, int len)
+static void ts78xx_ts_nand_write_buf(struct nand_chip *chip,
+                                    const uint8_t *buf, int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-       void __iomem *io_base = chip->IO_ADDR_W;
+       void __iomem *io_base = chip->legacy.IO_ADDR_W;
        unsigned long off = ((unsigned long)buf & 3);
        int sz;
 
@@ -182,11 +178,10 @@ static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
                writesb(io_base, buf, len);
 }
 
-static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
-                       uint8_t *buf, int len)
+static void ts78xx_ts_nand_read_buf(struct nand_chip *chip,
+                                   uint8_t *buf, int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-       void __iomem *io_base = chip->IO_ADDR_R;
+       void __iomem *io_base = chip->legacy.IO_ADDR_R;
        unsigned long off = ((unsigned long)buf & 3);
        int sz;
 
index af46d21825331ea5662a8aa042e814c93070f5e8..c52c081eb6d9dcbc8db7f49df5ce4f8b59f05b3b 100644 (file)
 #include <linux/ioport.h>
 #include <linux/ucb1400.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
 #include <linux/types.h>
 #include <linux/platform_data/pcf857x.h>
 #include <linux/platform_data/i2c-pxa.h>
-#include <linux/mtd/rawnand.h>
+#include <linux/mtd/platnand.h>
 #include <linux/mtd/physmap.h>
 #include <linux/regulator/max1586.h>
 
@@ -571,9 +570,9 @@ static inline void balloon3_i2c_init(void) {}
  * NAND
  ******************************************************************************/
 #if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
-static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void balloon3_nand_cmd_ctl(struct nand_chip *this, int cmd,
+                                 unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        uint8_t balloon3_ctl_set = 0, balloon3_ctl_clr = 0;
 
        if (ctrl & NAND_CTRL_CHANGE) {
@@ -597,10 +596,10 @@ static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ct
        }
 
        if (cmd != NAND_CMD_NONE)
-               writeb(cmd, this->IO_ADDR_W);
+               writeb(cmd, this->legacy.IO_ADDR_W);
 }
 
-static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip)
+static void balloon3_nand_select_chip(struct nand_chip *this, int chip)
 {
        if (chip < 0 || chip > 3)
                return;
@@ -616,7 +615,7 @@ static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip)
                BALLOON3_NAND_CONTROL_REG);
 }
 
-static int balloon3_nand_dev_ready(struct mtd_info *mtd)
+static int balloon3_nand_dev_ready(struct nand_chip *this)
 {
        return __raw_readl(BALLOON3_NAND_STAT_REG) & BALLOON3_NAND_STAT_RNB;
 }
index 29be04c6cc4858f3e93b73a8083643578cbc51bc..c30d20e1fb7a1ca60c7d58c8fa61feccbd76deac 100644 (file)
@@ -15,8 +15,7 @@
 
 #include <linux/dm9000.h>
 #include <linux/platform_data/rtc-v3020.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/mtd/physmap.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -285,11 +284,10 @@ static void nand_cs_off(void)
 }
 
 /* hardware specific access to control-lines */
-static void em_x270_nand_cmd_ctl(struct mtd_info *mtd, int dat,
+static void em_x270_nand_cmd_ctl(struct nand_chip *this, int dat,
                                 unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
+       unsigned long nandaddr = (unsigned long)this->legacy.IO_ADDR_W;
 
        dsb();
 
@@ -309,15 +307,15 @@ static void em_x270_nand_cmd_ctl(struct mtd_info *mtd, int dat,
        }
 
        dsb();
-       this->IO_ADDR_W = (void __iomem *)nandaddr;
+       this->legacy.IO_ADDR_W = (void __iomem *)nandaddr;
        if (dat != NAND_CMD_NONE)
-               writel(dat, this->IO_ADDR_W);
+               writel(dat, this->legacy.IO_ADDR_W);
 
        dsb();
 }
 
 /* read device ready pin */
-static int em_x270_nand_device_ready(struct mtd_info *mtd)
+static int em_x270_nand_device_ready(struct nand_chip *this)
 {
        dsb();
 
index 4cc05ecce6181755b2bb77b3e37589e0fcad3b35..b66b0b11d7172f4ad0e3db9e4a3fc80f0775f04d 100644 (file)
@@ -403,36 +403,6 @@ static void __init palmtreo_leds_init(void)
        platform_device_register(&palmtreo_leds);
 }
 
-/******************************************************************************
- * diskonchip docg4 flash
- ******************************************************************************/
-#if defined(CONFIG_MACH_TREO680)
-/* REVISIT: does the centro have this device also? */
-#if IS_ENABLED(CONFIG_MTD_NAND_DOCG4)
-static struct resource docg4_resources[] = {
-       {
-               .start  = 0x00000000,
-               .end    = 0x00001FFF,
-               .flags  = IORESOURCE_MEM,
-       },
-};
-
-static struct platform_device treo680_docg4_flash = {
-       .name   = "docg4",
-       .id     = -1,
-       .resource = docg4_resources,
-       .num_resources = ARRAY_SIZE(docg4_resources),
-};
-
-static void __init treo680_docg4_flash_init(void)
-{
-       platform_device_register(&treo680_docg4_flash);
-}
-#else
-static inline void treo680_docg4_flash_init(void) {}
-#endif
-#endif
-
 /******************************************************************************
  * Machine init
  ******************************************************************************/
@@ -517,7 +487,6 @@ static void __init treo680_init(void)
        treo680_gpio_init();
        palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, GPIO_NR_TREO680_SD_READONLY,
                        GPIO_NR_TREO680_SD_POWER, 0);
-       treo680_docg4_flash_init();
 }
 #endif
 
index 47e3e38e9becd229ad88b38ce90dcbeff1fa6035..1d06a8e91d8f9376b4a88a93b8dc4f58c9e4911b 100644 (file)
@@ -28,8 +28,7 @@
 #include <linux/wm97xx.h>
 #include <linux/power_supply.h>
 #include <linux/usb/gpio_vbus.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/physmap.h>
 
@@ -247,11 +246,10 @@ static inline void palmtx_keys_init(void) {}
  ******************************************************************************/
 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
        defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
-static void palmtx_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
-                                unsigned int ctrl)
+static void palmtx_nand_cmd_ctl(struct nand_chip *this, int cmd,
+                               unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       char __iomem *nandaddr = this->IO_ADDR_W;
+       char __iomem *nandaddr = this->legacy.IO_ADDR_W;
 
        if (cmd == NAND_CMD_NONE)
                return;
index da76637704253e3610f4f15b69a42e75af99d516..4bf02f96ab7ffd0eceb5b9d2ce28fff5ffe01068 100644 (file)
@@ -29,8 +29,7 @@
 #include <linux/leds.h>
 #include <linux/mmc/host.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/spi/spi.h>
@@ -197,11 +196,10 @@ static struct i2c_board_info db1200_i2c_devs[] __initdata = {
 
 /**********************************************************************/
 
-static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+static void au1200_nand_cmd_ctrl(struct nand_chip *this, int cmd,
                                 unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
+       unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
 
        ioaddr &= 0xffffff00;
 
@@ -213,14 +211,14 @@ static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
                /* assume we want to r/w real data  by default */
                ioaddr += MEM_STNAND_DATA;
        }
-       this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
+       this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
        if (cmd != NAND_CMD_NONE) {
-               __raw_writeb(cmd, this->IO_ADDR_W);
+               __raw_writeb(cmd, this->legacy.IO_ADDR_W);
                wmb();
        }
 }
 
-static int au1200_nand_device_ready(struct mtd_info *mtd)
+static int au1200_nand_device_ready(struct nand_chip *this)
 {
        return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
 }
index efb318e03e0a3d53163307d84c0d850c6a747869..ad7dd8e89598045986556ce685f21e1439a42a5d 100644 (file)
@@ -19,8 +19,7 @@
 #include <linux/mmc/host.h>
 #include <linux/module.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
 #include <linux/wm97xx.h>
@@ -149,11 +148,10 @@ static void __init db1300_gpio_config(void)
 
 /**********************************************************************/
 
-static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+static void au1300_nand_cmd_ctrl(struct nand_chip *this, int cmd,
                                 unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
+       unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
 
        ioaddr &= 0xffffff00;
 
@@ -165,14 +163,14 @@ static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
                /* assume we want to r/w real data  by default */
                ioaddr += MEM_STNAND_DATA;
        }
-       this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
+       this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
        if (cmd != NAND_CMD_NONE) {
-               __raw_writeb(cmd, this->IO_ADDR_W);
+               __raw_writeb(cmd, this->legacy.IO_ADDR_W);
                wmb();
        }
 }
 
-static int au1300_nand_device_ready(struct mtd_info *mtd)
+static int au1300_nand_device_ready(struct nand_chip *this)
 {
        return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
 }
index 7d3dfaa10231754e8d3eb683c8ab2439e1192a9b..7700ad0b93b4ce6b9f49fa2aeb496a572e6bc8c1 100644 (file)
@@ -13,8 +13,7 @@
 #include <linux/io.h>
 #include <linux/interrupt.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/spi/spi.h>
@@ -126,11 +125,10 @@ static struct i2c_board_info db1550_i2c_devs[] __initdata = {
 
 /**********************************************************************/
 
-static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+static void au1550_nand_cmd_ctrl(struct nand_chip *this, int cmd,
                                 unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
+       unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
 
        ioaddr &= 0xffffff00;
 
@@ -142,14 +140,14 @@ static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
                /* assume we want to r/w real data  by default */
                ioaddr += MEM_STNAND_DATA;
        }
-       this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
+       this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
        if (cmd != NAND_CMD_NONE) {
-               __raw_writeb(cmd, this->IO_ADDR_W);
+               __raw_writeb(cmd, this->legacy.IO_ADDR_W);
                wmb();
        }
 }
 
-static int au1550_nand_device_ready(struct mtd_info *mtd)
+static int au1550_nand_device_ready(struct nand_chip *this)
 {
        return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
 }
index 4d1b4c003376d1d0d196c623738e60f8d07826e4..cf9162284b0760df2b7b2433cf62987430c5df76 100644 (file)
@@ -19,8 +19,7 @@
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 
 #include <asm/netlogic/haldefs.h>
 #include <asm/netlogic/xlr/iomap.h>
@@ -92,8 +91,8 @@ struct xlr_nand_flash_priv {
 
 static struct xlr_nand_flash_priv nand_priv;
 
-static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd,
-               unsigned int ctrl)
+static void xlr_nand_ctrl(struct nand_chip *chip, int cmd,
+                         unsigned int ctrl)
 {
        if (ctrl & NAND_CLE)
                nlm_write_reg(nand_priv.flash_mmio,
index a7a4e9f5146d8264fa5452ed744f3331345e810e..dafbf027fad0185ea6af7df7b477313802a9102e 100644 (file)
@@ -30,8 +30,7 @@
 #include <linux/resource.h>
 #include <linux/serial.h>
 #include <linux/serial_pnx8xxx.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
+#include <linux/mtd/platnand.h>
 
 #include <irq.h>
 #include <irq-mapping.h>
@@ -178,10 +177,9 @@ static struct platform_device pnx833x_sata_device = {
 };
 
 static void
-pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+pnx833x_flash_nand_cmd_ctrl(struct nand_chip *this, int cmd, unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
+       unsigned long nandaddr = (unsigned long)this->legacy.IO_ADDR_W;
 
        if (cmd == NAND_CMD_NONE)
                return;
index 354d258396ff993f32878941d8c01621b887c8d7..2b23ad640f399f31118376a437d22a66621eaf3b 100644 (file)
@@ -20,9 +20,8 @@
 #include <linux/ctype.h>
 #include <linux/string.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/rawnand.h>
+#include <linux/mtd/platnand.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
@@ -141,14 +140,13 @@ static struct platform_device cf_slot0 = {
 };
 
 /* Resources and device for NAND */
-static int rb532_dev_ready(struct mtd_info *mtd)
+static int rb532_dev_ready(struct nand_chip *chip)
 {
        return gpio_get_value(GPIO_RDY);
 }
 
-static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void rb532_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        unsigned char orbits, nandbits;
 
        if (ctrl & NAND_CTRL_CHANGE) {
@@ -161,7 +159,7 @@ static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
                set_latch_u5(orbits, nandbits);
        }
        if (cmd != NAND_CMD_NONE)
-               writeb(cmd, chip->IO_ADDR_W);
+               writeb(cmd, chip->legacy.IO_ADDR_W);
 }
 
 static struct resource nand_slot0_res[] = {
index 254f2c66270362845524352e5ad73a1b6bdecf9b..f4ad33c6d2aaa9c6e0564b11db724cbc4bdc8f28 100644 (file)
@@ -14,7 +14,7 @@
 #include <linux/mmc/host.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mfd/tmio.h>
-#include <linux/mtd/rawnand.h>
+#include <linux/mtd/platnand.h>
 #include <linux/i2c.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
@@ -165,23 +165,21 @@ static struct mtd_partition migor_nand_flash_partitions[] = {
        },
 };
 
-static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
+static void migor_nand_flash_cmd_ctl(struct nand_chip *chip, int cmd,
                                     unsigned int ctrl)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-
        if (cmd == NAND_CMD_NONE)
                return;
 
        if (ctrl & NAND_CLE)
-               writeb(cmd, chip->IO_ADDR_W + 0x00400000);
+               writeb(cmd, chip->legacy.IO_ADDR_W + 0x00400000);
        else if (ctrl & NAND_ALE)
-               writeb(cmd, chip->IO_ADDR_W + 0x00800000);
+               writeb(cmd, chip->legacy.IO_ADDR_W + 0x00800000);
        else
-               writeb(cmd, chip->IO_ADDR_W);
+               writeb(cmd, chip->legacy.IO_ADDR_W);
 }
 
-static int migor_nand_flash_ready(struct mtd_info *mtd)
+static int migor_nand_flash_ready(struct nand_chip *chip)
 {
        return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
 }
index 270d3c9580c51195ccb6b05e3719e98fb1836031..c4a1d04b8c800d1b090e99dc9975025d4b61009c 100644 (file)
@@ -90,7 +90,6 @@ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
                                   SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
                                   SPI_MEM_OP_NO_DUMMY,
                                   SPI_MEM_OP_DATA_OUT(len, buf, 1));
-       size_t remaining = len;
        int ret;
 
        /* get transfer protocols. */
@@ -101,22 +100,16 @@ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
        if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
                op.addr.nbytes = 0;
 
-       while (remaining) {
-               op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
-               ret = spi_mem_adjust_op_size(flash->spimem, &op);
-               if (ret)
-                       return ret;
-
-               ret = spi_mem_exec_op(flash->spimem, &op);
-               if (ret)
-                       return ret;
+       ret = spi_mem_adjust_op_size(flash->spimem, &op);
+       if (ret)
+               return ret;
+       op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
 
-               op.addr.val += op.data.nbytes;
-               remaining -= op.data.nbytes;
-               op.data.buf.out += op.data.nbytes;
-       }
+       ret = spi_mem_exec_op(flash->spimem, &op);
+       if (ret)
+               return ret;
 
-       return len;
+       return op.data.nbytes;
 }
 
 /*
index 9d972369321755b5560c371626d9c8bf9a8d8271..a20e85aa770e37248b2c9e34e7cc2ac67bbc9778 100644 (file)
@@ -14,6 +14,7 @@
  */
 
 #include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 
-#define pr_devinit(fmt, args...) \
-       ({ static const char __fmt[] = fmt; printk(__fmt, ## args); })
+#define win_mask(x) ((BIT(x)) - 1)
 
 #define DRIVER_NAME "gpio-addr-flash"
-#define PFX DRIVER_NAME ": "
 
 /**
  * struct async_state - keep GPIO flash state
  *     @mtd:         MTD state for this mapping
  *     @map:         MTD map state for this flash
- *     @gpio_count:  number of GPIOs used to address
- *     @gpio_addrs:  array of GPIOs to twiddle
+ *     @gpios:       Struct containing the array of GPIO descriptors
  *     @gpio_values: cached GPIO values
- *     @win_size:    dedicated memory size (if no GPIOs)
+ *     @win_order:   dedicated memory size (if no GPIOs)
  */
 struct async_state {
        struct mtd_info *mtd;
        struct map_info map;
-       size_t gpio_count;
-       unsigned *gpio_addrs;
-       int *gpio_values;
-       unsigned long win_size;
+       struct gpio_descs *gpios;
+       unsigned int gpio_values;
+       unsigned int win_order;
 };
 #define gf_map_info_to_state(mi) ((struct async_state *)(mi)->map_priv_1)
 
@@ -57,21 +54,25 @@ struct async_state {
  *
  * Rather than call the GPIO framework every time, cache the last-programmed
  * value.  This speeds up sequential accesses (which are by far the most common
- * type).  We rely on the GPIO framework to treat non-zero value as high so
- * that we don't have to normalize the bits.
+ * type).
  */
 static void gf_set_gpios(struct async_state *state, unsigned long ofs)
 {
-       size_t i = 0;
-       int value;
-       ofs /= state->win_size;
-       do {
-               value = ofs & (1 << i);
-               if (state->gpio_values[i] != value) {
-                       gpio_set_value(state->gpio_addrs[i], value);
-                       state->gpio_values[i] = value;
-               }
-       } while (++i < state->gpio_count);
+       int i;
+
+       ofs >>= state->win_order;
+
+       if (ofs == state->gpio_values)
+               return;
+
+       for (i = 0; i < state->gpios->ndescs; i++) {
+               if ((ofs & BIT(i)) == (state->gpio_values & BIT(i)))
+                       continue;
+
+               gpiod_set_value(state->gpios->desc[i], !!(ofs & BIT(i)));
+       }
+
+       state->gpio_values = ofs;
 }
 
 /**
@@ -87,7 +88,7 @@ static map_word gf_read(struct map_info *map, unsigned long ofs)
 
        gf_set_gpios(state, ofs);
 
-       word = readw(map->virt + (ofs % state->win_size));
+       word = readw(map->virt + (ofs & win_mask(state->win_order)));
        test.x[0] = word;
        return test;
 }
@@ -109,14 +110,14 @@ static void gf_copy_from(struct map_info *map, void *to, unsigned long from, ssi
        int this_len;
 
        while (len) {
-               if ((from % state->win_size) + len > state->win_size)
-                       this_len = state->win_size - (from % state->win_size);
-               else
-                       this_len = len;
+               this_len = from & win_mask(state->win_order);
+               this_len = BIT(state->win_order) - this_len;
+               this_len = min_t(int, len, this_len);
 
                gf_set_gpios(state, from);
-               memcpy_fromio(to, map->virt + (from % state->win_size),
-                        this_len);
+               memcpy_fromio(to,
+                             map->virt + (from & win_mask(state->win_order)),
+                             this_len);
                len -= this_len;
                from += this_len;
                to += this_len;
@@ -136,7 +137,7 @@ static void gf_write(struct map_info *map, map_word d1, unsigned long ofs)
        gf_set_gpios(state, ofs);
 
        d = d1.x[0];
-       writew(d, map->virt + (ofs % state->win_size));
+       writew(d, map->virt + (ofs & win_mask(state->win_order)));
 }
 
 /**
@@ -156,13 +157,13 @@ static void gf_copy_to(struct map_info *map, unsigned long to,
        int this_len;
 
        while (len) {
-               if ((to % state->win_size) + len > state->win_size)
-                       this_len = state->win_size - (to % state->win_size);
-               else
-                       this_len = len;
+               this_len = to & win_mask(state->win_order);
+               this_len = BIT(state->win_order) - this_len;
+               this_len = min_t(int, len, this_len);
 
                gf_set_gpios(state, to);
-               memcpy_toio(map->virt + (to % state->win_size), from, len);
+               memcpy_toio(map->virt + (to & win_mask(state->win_order)),
+                           from, len);
 
                len -= this_len;
                to += this_len;
@@ -180,18 +181,22 @@ static const char * const part_probe_types[] = {
  * The platform resource layout expected looks something like:
  * struct mtd_partition partitions[] = { ... };
  * struct physmap_flash_data flash_data = { ... };
- * unsigned flash_gpios[] = { GPIO_XX, GPIO_XX, ... };
+ * static struct gpiod_lookup_table addr_flash_gpios = {
+ *             .dev_id = "gpio-addr-flash.0",
+ *             .table = {
+ *             GPIO_LOOKUP_IDX("gpio.0", 15, "addr", 0, GPIO_ACTIVE_HIGH),
+ *             GPIO_LOOKUP_IDX("gpio.0", 16, "addr", 1, GPIO_ACTIVE_HIGH),
+ *             );
+ * };
+ * gpiod_add_lookup_table(&addr_flash_gpios);
+ *
  * struct resource flash_resource[] = {
  *     {
  *             .name  = "cfi_probe",
  *             .start = 0x20000000,
  *             .end   = 0x201fffff,
  *             .flags = IORESOURCE_MEM,
- *     }, {
- *             .start = (unsigned long)flash_gpios,
- *             .end   = ARRAY_SIZE(flash_gpios),
- *             .flags = IORESOURCE_IRQ,
- *     }
+ *     },
  * };
  * struct platform_device flash_device = {
  *     .name          = "gpio-addr-flash",
@@ -203,33 +208,25 @@ static const char * const part_probe_types[] = {
  */
 static int gpio_flash_probe(struct platform_device *pdev)
 {
-       size_t i, arr_size;
        struct physmap_flash_data *pdata;
        struct resource *memory;
-       struct resource *gpios;
        struct async_state *state;
 
        pdata = dev_get_platdata(&pdev->dev);
        memory = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       gpios = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 
-       if (!memory || !gpios || !gpios->end)
+       if (!memory)
                return -EINVAL;
 
-       arr_size = sizeof(int) * gpios->end;
-       state = kzalloc(sizeof(*state) + arr_size, GFP_KERNEL);
+       state = devm_kzalloc(&pdev->dev, sizeof(*state), GFP_KERNEL);
        if (!state)
                return -ENOMEM;
 
-       /*
-        * We cast start/end to known types in the boards file, so cast
-        * away their pointer types here to the known types (gpios->xxx).
-        */
-       state->gpio_count     = gpios->end;
-       state->gpio_addrs     = (void *)(unsigned long)gpios->start;
-       state->gpio_values    = (void *)(state + 1);
-       state->win_size       = resource_size(memory);
-       memset(state->gpio_values, 0xff, arr_size);
+       state->gpios = devm_gpiod_get_array(&pdev->dev, "addr", GPIOD_OUT_LOW);
+       if (IS_ERR(state->gpios))
+               return PTR_ERR(state->gpios);
+
+       state->win_order      = get_bitmask_order(resource_size(memory)) - 1;
 
        state->map.name       = DRIVER_NAME;
        state->map.read       = gf_read;
@@ -237,38 +234,21 @@ static int gpio_flash_probe(struct platform_device *pdev)
        state->map.write      = gf_write;
        state->map.copy_to    = gf_copy_to;
        state->map.bankwidth  = pdata->width;
-       state->map.size       = state->win_size * (1 << state->gpio_count);
-       state->map.virt       = ioremap_nocache(memory->start, state->map.size);
-       if (!state->map.virt)
-               return -ENOMEM;
+       state->map.size       = BIT(state->win_order + state->gpios->ndescs);
+       state->map.virt       = devm_ioremap_resource(&pdev->dev, memory);
+       if (IS_ERR(state->map.virt))
+               return PTR_ERR(state->map.virt);
 
        state->map.phys       = NO_XIP;
        state->map.map_priv_1 = (unsigned long)state;
 
        platform_set_drvdata(pdev, state);
 
-       i = 0;
-       do {
-               if (gpio_request(state->gpio_addrs[i], DRIVER_NAME)) {
-                       pr_devinit(KERN_ERR PFX "failed to request gpio %d\n",
-                               state->gpio_addrs[i]);
-                       while (i--)
-                               gpio_free(state->gpio_addrs[i]);
-                       kfree(state);
-                       return -EBUSY;
-               }
-               gpio_direction_output(state->gpio_addrs[i], 0);
-       } while (++i < state->gpio_count);
-
-       pr_devinit(KERN_NOTICE PFX "probing %d-bit flash bus\n",
-               state->map.bankwidth * 8);
+       dev_notice(&pdev->dev, "probing %d-bit flash bus\n",
+                  state->map.bankwidth * 8);
        state->mtd = do_map_probe(memory->name, &state->map);
-       if (!state->mtd) {
-               for (i = 0; i < state->gpio_count; ++i)
-                       gpio_free(state->gpio_addrs[i]);
-               kfree(state);
+       if (!state->mtd)
                return -ENXIO;
-       }
        state->mtd->dev.parent = &pdev->dev;
 
        mtd_device_parse_register(state->mtd, part_probe_types, NULL,
@@ -280,13 +260,9 @@ static int gpio_flash_probe(struct platform_device *pdev)
 static int gpio_flash_remove(struct platform_device *pdev)
 {
        struct async_state *state = platform_get_drvdata(pdev);
-       size_t i = 0;
-       do {
-               gpio_free(state->gpio_addrs[i]);
-       } while (++i < state->gpio_count);
+
        mtd_device_unregister(state->mtd);
        map_destroy(state->mtd);
-       kfree(state);
        return 0;
 }
 
index 4129535b8e46f34e8891c3d86f0c6fb5160f6095..ece605d78c215670af7334fff835fb095e155bd0 100644 (file)
@@ -31,7 +31,6 @@
 struct of_flash_list {
        struct mtd_info *mtd;
        struct map_info map;
-       struct resource *res;
 };
 
 struct of_flash {
@@ -56,18 +55,10 @@ static int of_flash_remove(struct platform_device *dev)
                        mtd_concat_destroy(info->cmtd);
        }
 
-       for (i = 0; i < info->list_size; i++) {
+       for (i = 0; i < info->list_size; i++)
                if (info->list[i].mtd)
                        map_destroy(info->list[i].mtd);
 
-               if (info->list[i].map.virt)
-                       iounmap(info->list[i].map.virt);
-
-               if (info->list[i].res) {
-                       release_resource(info->list[i].res);
-                       kfree(info->list[i].res);
-               }
-       }
        return 0;
 }
 
@@ -215,10 +206,11 @@ static int of_flash_probe(struct platform_device *dev)
 
                err = -EBUSY;
                res_size = resource_size(&res);
-               info->list[i].res = request_mem_region(res.start, res_size,
-                                                      dev_name(&dev->dev));
-               if (!info->list[i].res)
+               info->list[i].map.virt = devm_ioremap_resource(&dev->dev, &res);
+               if (IS_ERR(info->list[i].map.virt)) {
+                       err = PTR_ERR(info->list[i].map.virt);
                        goto err_out;
+               }
 
                err = -ENXIO;
                width = of_get_property(dp, "bank-width", NULL);
@@ -246,15 +238,6 @@ static int of_flash_probe(struct platform_device *dev)
                if (err)
                        goto err_out;
 
-               err = -ENOMEM;
-               info->list[i].map.virt = ioremap(info->list[i].map.phys,
-                                                info->list[i].map.size);
-               if (!info->list[i].map.virt) {
-                       dev_err(&dev->dev, "Failed to ioremap() flash"
-                               " region\n");
-                       goto err_out;
-               }
-
                simple_map_init(&info->list[i].map);
 
                /*
index 830b1b7e702bc7433425bc37c21422d0fb3276a3..9df62ca721d5dd624a9bb738aa9d1fcb47cce244 100644 (file)
 
 #define FLASH_PARALLEL_HIGH_PIN_CNT    (1 << 20)       /* else low pin cnt */
 
-static const struct of_device_id syscon_match[] = {
-       { .compatible = "cortina,gemini-syscon" },
-       { },
-};
-
 int of_flash_probe_gemini(struct platform_device *pdev,
                          struct device_node *np,
                          struct map_info *map)
index 5fc9a1bde4ac2e6d6e8475ab92c81342395d03d7..c7efc31384d52726199a63869cc3dd1b547128e4 100644 (file)
@@ -227,26 +227,6 @@ config MTD_NAND_DISKONCHIP_BBTWRITE
          load time (assuming you build diskonchip as a module) with the module
          parameter "inftl_bbt_write=1".
 
-config MTD_NAND_DOCG4
-       tristate "Support for DiskOnChip G4"
-       depends on HAS_IOMEM
-       select BCH
-       select BITREVERSE
-       help
-         Support for diskonchip G4 nand flash, found in various smartphones and
-         PDAs, among them the Palm Treo680, HTC Prophet and Wizard, Toshiba
-         Portege G900, Asus P526, and O2 XDA Zinc.
-
-         With this driver you will be able to use UBI and create a ubifs on the
-         device, so you may wish to consider enabling UBI and UBIFS as well.
-
-         These devices ship with the Mys/Sandisk SAFTL formatting, for which
-         there is currently no mtd parser, so you may want to use command line
-         partitioning to segregate write-protected blocks. On the Treo680, the
-         first five erase blocks (256KiB each) are write-protected, followed
-         by the block containing the saftl partition table.  This is probably
-         typical.
-
 config MTD_NAND_SHARPSL
        tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)"
        depends on ARCH_PXA || COMPILE_TEST
index d5a5f9832b8879e4cbf16f5dd7f902edcf52c239..57159b349054ddf2065890326a5809633f8c4f16 100644 (file)
@@ -15,7 +15,6 @@ obj-$(CONFIG_MTD_NAND_S3C2410)                += s3c2410.o
 obj-$(CONFIG_MTD_NAND_TANGO)           += tango_nand.o
 obj-$(CONFIG_MTD_NAND_DAVINCI)         += davinci_nand.o
 obj-$(CONFIG_MTD_NAND_DISKONCHIP)      += diskonchip.o
-obj-$(CONFIG_MTD_NAND_DOCG4)           += docg4.o
 obj-$(CONFIG_MTD_NAND_FSMC)            += fsmc_nand.o
 obj-$(CONFIG_MTD_NAND_SHARPSL)         += sharpsl.o
 obj-$(CONFIG_MTD_NAND_NANDSIM)         += nandsim.o
@@ -58,8 +57,11 @@ obj-$(CONFIG_MTD_NAND_QCOM)          += qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK)             += mtk_ecc.o mtk_nand.o
 obj-$(CONFIG_MTD_NAND_TEGRA)           += tegra_nand.o
 
-nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
+nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
+nand-objs += nand_onfi.o
+nand-objs += nand_jedec.o
 nand-objs += nand_amd.o
+nand-objs += nand_esmt.o
 nand-objs += nand_hynix.o
 nand-objs += nand_macronix.o
 nand-objs += nand_micron.o
index 37a3cc21c7bccd396d92d6655e0004cd1aeddf6b..5ba180a291eb2986004b76af286e9582146e2d62 100644 (file)
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/delay.h>
+#include <linux/gpio/consumer.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/mtd/partitions.h>
-#include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
 
 #include <asm/io.h>
 #include <asm/sizes.h>
 
-#include <mach/board-ams-delta.h>
-
 #include <mach/hardware.h>
 
 /*
  * MTD structure for E3 (Delta)
  */
-static struct mtd_info *ams_delta_mtd = NULL;
+
+struct ams_delta_nand {
+       struct nand_chip        nand_chip;
+       struct gpio_desc        *gpiod_rdy;
+       struct gpio_desc        *gpiod_nce;
+       struct gpio_desc        *gpiod_nre;
+       struct gpio_desc        *gpiod_nwp;
+       struct gpio_desc        *gpiod_nwe;
+       struct gpio_desc        *gpiod_ale;
+       struct gpio_desc        *gpiod_cle;
+       void __iomem            *io_base;
+       bool                    data_in;
+};
 
 /*
  * Define partitions for flash devices
@@ -63,48 +73,64 @@ static const struct mtd_partition partition_info[] = {
          .size         =  3 * SZ_256K },
 };
 
-static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
+static void ams_delta_io_write(struct ams_delta_nand *priv, u_char byte)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       void __iomem *io_base = (void __iomem *)nand_get_controller_data(this);
-
-       writew(0, io_base + OMAP_MPUIO_IO_CNTL);
-       writew(byte, this->IO_ADDR_W);
-       gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
+       writew(byte, priv->nand_chip.legacy.IO_ADDR_W);
+       gpiod_set_value(priv->gpiod_nwe, 0);
        ndelay(40);
-       gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
+       gpiod_set_value(priv->gpiod_nwe, 1);
 }
 
-static u_char ams_delta_read_byte(struct mtd_info *mtd)
+static u_char ams_delta_io_read(struct ams_delta_nand *priv)
 {
        u_char res;
-       struct nand_chip *this = mtd_to_nand(mtd);
-       void __iomem *io_base = (void __iomem *)nand_get_controller_data(this);
 
-       gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 0);
+       gpiod_set_value(priv->gpiod_nre, 0);
        ndelay(40);
-       writew(~0, io_base + OMAP_MPUIO_IO_CNTL);
-       res = readw(this->IO_ADDR_R);
-       gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 1);
+       res = readw(priv->nand_chip.legacy.IO_ADDR_R);
+       gpiod_set_value(priv->gpiod_nre, 1);
 
        return res;
 }
 
-static void ams_delta_write_buf(struct mtd_info *mtd, const u_char *buf,
+static void ams_delta_dir_input(struct ams_delta_nand *priv, bool in)
+{
+       writew(in ? ~0 : 0, priv->io_base + OMAP_MPUIO_IO_CNTL);
+       priv->data_in = in;
+}
+
+static void ams_delta_write_buf(struct nand_chip *this, const u_char *buf,
                                int len)
 {
+       struct ams_delta_nand *priv = nand_get_controller_data(this);
        int i;
 
-       for (i=0; i<len; i++)
-               ams_delta_write_byte(mtd, buf[i]);
+       if (priv->data_in)
+               ams_delta_dir_input(priv, false);
+
+       for (i = 0; i < len; i++)
+               ams_delta_io_write(priv, buf[i]);
 }
 
-static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+static void ams_delta_read_buf(struct nand_chip *this, u_char *buf, int len)
 {
+       struct ams_delta_nand *priv = nand_get_controller_data(this);
        int i;
 
-       for (i=0; i<len; i++)
-               buf[i] = ams_delta_read_byte(mtd);
+       if (!priv->data_in)
+               ams_delta_dir_input(priv, true);
+
+       for (i = 0; i < len; i++)
+               buf[i] = ams_delta_io_read(priv);
+}
+
+static u_char ams_delta_read_byte(struct nand_chip *this)
+{
+       u_char res;
+
+       ams_delta_read_buf(this, &res, 1);
+
+       return res;
 }
 
 /*
@@ -115,67 +141,40 @@ static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  * NAND_CLE: bit 1 -> bit 7
  * NAND_ALE: bit 2 -> bit 6
  */
-static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd,
+static void ams_delta_hwcontrol(struct nand_chip *this, int cmd,
                                unsigned int ctrl)
 {
+       struct ams_delta_nand *priv = nand_get_controller_data(this);
 
        if (ctrl & NAND_CTRL_CHANGE) {
-               gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NCE,
-                               (ctrl & NAND_NCE) == 0);
-               gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_CLE,
-                               (ctrl & NAND_CLE) != 0);
-               gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_ALE,
-                               (ctrl & NAND_ALE) != 0);
+               gpiod_set_value(priv->gpiod_nce, !(ctrl & NAND_NCE));
+               gpiod_set_value(priv->gpiod_cle, !!(ctrl & NAND_CLE));
+               gpiod_set_value(priv->gpiod_ale, !!(ctrl & NAND_ALE));
        }
 
-       if (cmd != NAND_CMD_NONE)
-               ams_delta_write_byte(mtd, cmd);
+       if (cmd != NAND_CMD_NONE) {
+               u_char byte = cmd;
+
+               ams_delta_write_buf(this, &byte, 1);
+       }
 }
 
-static int ams_delta_nand_ready(struct mtd_info *mtd)
+static int ams_delta_nand_ready(struct nand_chip *this)
 {
-       return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB);
+       struct ams_delta_nand *priv = nand_get_controller_data(this);
+
+       return gpiod_get_value(priv->gpiod_rdy);
 }
 
-static const struct gpio _mandatory_gpio[] = {
-       {
-               .gpio   = AMS_DELTA_GPIO_PIN_NAND_NCE,
-               .flags  = GPIOF_OUT_INIT_HIGH,
-               .label  = "nand_nce",
-       },
-       {
-               .gpio   = AMS_DELTA_GPIO_PIN_NAND_NRE,
-               .flags  = GPIOF_OUT_INIT_HIGH,
-               .label  = "nand_nre",
-       },
-       {
-               .gpio   = AMS_DELTA_GPIO_PIN_NAND_NWP,
-               .flags  = GPIOF_OUT_INIT_HIGH,
-               .label  = "nand_nwp",
-       },
-       {
-               .gpio   = AMS_DELTA_GPIO_PIN_NAND_NWE,
-               .flags  = GPIOF_OUT_INIT_HIGH,
-               .label  = "nand_nwe",
-       },
-       {
-               .gpio   = AMS_DELTA_GPIO_PIN_NAND_ALE,
-               .flags  = GPIOF_OUT_INIT_LOW,
-               .label  = "nand_ale",
-       },
-       {
-               .gpio   = AMS_DELTA_GPIO_PIN_NAND_CLE,
-               .flags  = GPIOF_OUT_INIT_LOW,
-               .label  = "nand_cle",
-       },
-};
 
 /*
  * Main initialization routine
  */
 static int ams_delta_init(struct platform_device *pdev)
 {
+       struct ams_delta_nand *priv;
        struct nand_chip *this;
+       struct mtd_info *mtd;
        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        void __iomem *io_base;
        int err = 0;
@@ -184,15 +183,16 @@ static int ams_delta_init(struct platform_device *pdev)
                return -ENXIO;
 
        /* Allocate memory for MTD device structure and private data */
-       this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
-       if (!this) {
+       priv = devm_kzalloc(&pdev->dev, sizeof(struct ams_delta_nand),
+                           GFP_KERNEL);
+       if (!priv) {
                pr_warn("Unable to allocate E3 NAND MTD device structure.\n");
-               err = -ENOMEM;
-               goto out;
+               return -ENOMEM;
        }
+       this = &priv->nand_chip;
 
-       ams_delta_mtd = nand_to_mtd(this);
-       ams_delta_mtd->owner = THIS_MODULE;
+       mtd = nand_to_mtd(this);
+       mtd->dev.parent = &pdev->dev;
 
        /*
         * Don't try to request the memory region from here,
@@ -207,51 +207,93 @@ static int ams_delta_init(struct platform_device *pdev)
                goto out_free;
        }
 
-       nand_set_controller_data(this, (void *)io_base);
+       priv->io_base = io_base;
+       nand_set_controller_data(this, priv);
 
        /* Set address of NAND IO lines */
-       this->IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH;
-       this->IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT;
-       this->read_byte = ams_delta_read_byte;
-       this->write_buf = ams_delta_write_buf;
-       this->read_buf = ams_delta_read_buf;
-       this->cmd_ctrl = ams_delta_hwcontrol;
-       if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) {
-               this->dev_ready = ams_delta_nand_ready;
-       } else {
-               this->dev_ready = NULL;
-               pr_notice("Couldn't request gpio for Delta NAND ready.\n");
+       this->legacy.IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH;
+       this->legacy.IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT;
+       this->legacy.read_byte = ams_delta_read_byte;
+       this->legacy.write_buf = ams_delta_write_buf;
+       this->legacy.read_buf = ams_delta_read_buf;
+       this->legacy.cmd_ctrl = ams_delta_hwcontrol;
+
+       priv->gpiod_rdy = devm_gpiod_get_optional(&pdev->dev, "rdy", GPIOD_IN);
+       if (IS_ERR(priv->gpiod_rdy)) {
+               err = PTR_ERR(priv->gpiod_rdy);
+               dev_warn(&pdev->dev, "RDY GPIO request failed (%d)\n", err);
+               goto out_mtd;
        }
+
+       if (priv->gpiod_rdy)
+               this->legacy.dev_ready = ams_delta_nand_ready;
+
        /* 25 us command delay time */
-       this->chip_delay = 30;
+       this->legacy.chip_delay = 30;
        this->ecc.mode = NAND_ECC_SOFT;
        this->ecc.algo = NAND_ECC_HAMMING;
 
-       platform_set_drvdata(pdev, io_base);
+       platform_set_drvdata(pdev, priv);
 
        /* Set chip enabled, but  */
-       err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
-       if (err)
-               goto out_gpio;
+       priv->gpiod_nwp = devm_gpiod_get(&pdev->dev, "nwp", GPIOD_OUT_HIGH);
+       if (IS_ERR(priv->gpiod_nwp)) {
+               err = PTR_ERR(priv->gpiod_nwp);
+               dev_err(&pdev->dev, "NWP GPIO request failed (%d)\n", err);
+               goto out_mtd;
+       }
+
+       priv->gpiod_nce = devm_gpiod_get(&pdev->dev, "nce", GPIOD_OUT_HIGH);
+       if (IS_ERR(priv->gpiod_nce)) {
+               err = PTR_ERR(priv->gpiod_nce);
+               dev_err(&pdev->dev, "NCE GPIO request failed (%d)\n", err);
+               goto out_mtd;
+       }
+
+       priv->gpiod_nre = devm_gpiod_get(&pdev->dev, "nre", GPIOD_OUT_HIGH);
+       if (IS_ERR(priv->gpiod_nre)) {
+               err = PTR_ERR(priv->gpiod_nre);
+               dev_err(&pdev->dev, "NRE GPIO request failed (%d)\n", err);
+               goto out_mtd;
+       }
+
+       priv->gpiod_nwe = devm_gpiod_get(&pdev->dev, "nwe", GPIOD_OUT_HIGH);
+       if (IS_ERR(priv->gpiod_nwe)) {
+               err = PTR_ERR(priv->gpiod_nwe);
+               dev_err(&pdev->dev, "NWE GPIO request failed (%d)\n", err);
+               goto out_mtd;
+       }
+
+       priv->gpiod_ale = devm_gpiod_get(&pdev->dev, "ale", GPIOD_OUT_LOW);
+       if (IS_ERR(priv->gpiod_ale)) {
+               err = PTR_ERR(priv->gpiod_ale);
+               dev_err(&pdev->dev, "ALE GPIO request failed (%d)\n", err);
+               goto out_mtd;
+       }
+
+       priv->gpiod_cle = devm_gpiod_get(&pdev->dev, "cle", GPIOD_OUT_LOW);
+       if (IS_ERR(priv->gpiod_cle)) {
+               err = PTR_ERR(priv->gpiod_cle);
+               dev_err(&pdev->dev, "CLE GPIO request failed (%d)\n", err);
+               goto out_mtd;
+       }
+
+       /* Initialize data port direction to a known state */
+       ams_delta_dir_input(priv, true);
 
        /* Scan to find existence of the device */
-       err = nand_scan(ams_delta_mtd, 1);
+       err = nand_scan(this, 1);
        if (err)
                goto out_mtd;
 
        /* Register the partitions */
-       mtd_device_register(ams_delta_mtd, partition_info,
-                           ARRAY_SIZE(partition_info));
+       mtd_device_register(mtd, partition_info, ARRAY_SIZE(partition_info));
 
        goto out;
 
  out_mtd:
-       gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
-out_gpio:
-       gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
        iounmap(io_base);
 out_free:
-       kfree(this);
  out:
        return err;
 }
@@ -261,18 +303,15 @@ out_free:
  */
 static int ams_delta_cleanup(struct platform_device *pdev)
 {
-       void __iomem *io_base = platform_get_drvdata(pdev);
+       struct ams_delta_nand *priv = platform_get_drvdata(pdev);
+       struct mtd_info *mtd = nand_to_mtd(&priv->nand_chip);
+       void __iomem *io_base = priv->io_base;
 
        /* Release resources, unregister device */
-       nand_release(ams_delta_mtd);
+       nand_release(mtd_to_nand(mtd));
 
-       gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
-       gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
        iounmap(io_base);
 
-       /* Free the MTD device structure */
-       kfree(mtd_to_nand(ams_delta_mtd));
-
        return 0;
 }
 
index a068b214ebaa7970fac10d1b0ae4b2af0602e9ae..fb33f6be7c4ff7306f391931e1843f6712edbdb7 100644 (file)
@@ -410,25 +410,15 @@ err:
        return -EIO;
 }
 
-static u8 atmel_nand_read_byte(struct mtd_info *mtd)
+static u8 atmel_nand_read_byte(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct atmel_nand *nand = to_atmel_nand(chip);
 
        return ioread8(nand->activecs->io.virt);
 }
 
-static u16 atmel_nand_read_word(struct mtd_info *mtd)
+static void atmel_nand_write_byte(struct nand_chip *chip, u8 byte)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-       struct atmel_nand *nand = to_atmel_nand(chip);
-
-       return ioread16(nand->activecs->io.virt);
-}
-
-static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
-{
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct atmel_nand *nand = to_atmel_nand(chip);
 
        if (chip->options & NAND_BUSWIDTH_16)
@@ -437,9 +427,8 @@ static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
                iowrite8(byte, nand->activecs->io.virt);
 }
 
-static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+static void atmel_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct atmel_nand *nand = to_atmel_nand(chip);
        struct atmel_nand_controller *nc;
 
@@ -462,9 +451,8 @@ static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
                ioread8_rep(nand->activecs->io.virt, buf, len);
 }
 
-static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+static void atmel_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct atmel_nand *nand = to_atmel_nand(chip);
        struct atmel_nand_controller *nc;
 
@@ -487,34 +475,31 @@ static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
                iowrite8_rep(nand->activecs->io.virt, buf, len);
 }
 
-static int atmel_nand_dev_ready(struct mtd_info *mtd)
+static int atmel_nand_dev_ready(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct atmel_nand *nand = to_atmel_nand(chip);
 
        return gpiod_get_value(nand->activecs->rb.gpio);
 }
 
-static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
+static void atmel_nand_select_chip(struct nand_chip *chip, int cs)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct atmel_nand *nand = to_atmel_nand(chip);
 
        if (cs < 0 || cs >= nand->numcs) {
                nand->activecs = NULL;
-               chip->dev_ready = NULL;
+               chip->legacy.dev_ready = NULL;
                return;
        }
 
        nand->activecs = &nand->cs[cs];
 
        if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
-               chip->dev_ready = atmel_nand_dev_ready;
+               chip->legacy.dev_ready = atmel_nand_dev_ready;
 }
 
-static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
+static int atmel_hsmc_nand_dev_ready(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct atmel_nand *nand = to_atmel_nand(chip);
        struct atmel_hsmc_nand_controller *nc;
        u32 status;
@@ -526,15 +511,15 @@ static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
        return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 }
 
-static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
+static void atmel_hsmc_nand_select_chip(struct nand_chip *chip, int cs)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct atmel_nand *nand = to_atmel_nand(chip);
        struct atmel_hsmc_nand_controller *nc;
 
        nc = to_hsmc_nand_controller(chip->controller);
 
-       atmel_nand_select_chip(mtd, cs);
+       atmel_nand_select_chip(chip, cs);
 
        if (!nand->activecs) {
                regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
@@ -543,7 +528,7 @@ static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
        }
 
        if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
-               chip->dev_ready = atmel_hsmc_nand_dev_ready;
+               chip->legacy.dev_ready = atmel_hsmc_nand_dev_ready;
 
        regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
                           ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
@@ -607,10 +592,9 @@ static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
        return ret;
 }
 
-static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
+static void atmel_hsmc_nand_cmd_ctrl(struct nand_chip *chip, int dat,
                                     unsigned int ctrl)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct atmel_nand *nand = to_atmel_nand(chip);
        struct atmel_hsmc_nand_controller *nc;
 
@@ -634,10 +618,9 @@ static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
        }
 }
 
-static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+static void atmel_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
                                unsigned int ctrl)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct atmel_nand *nand = to_atmel_nand(chip);
        struct atmel_nand_controller *nc;
 
@@ -851,7 +834,7 @@ static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
        if (ret)
                return ret;
 
-       atmel_nand_write_buf(mtd, buf, mtd->writesize);
+       atmel_nand_write_buf(chip, buf, mtd->writesize);
 
        ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
        if (ret) {
@@ -861,20 +844,18 @@ static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 
        atmel_nand_pmecc_disable(chip, raw);
 
-       atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
+       atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize);
 
        return nand_prog_page_end_op(chip);
 }
 
-static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
-                                      struct nand_chip *chip, const u8 *buf,
+static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf,
                                       int oob_required, int page)
 {
        return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 }
 
-static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
-                                          struct nand_chip *chip,
+static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip,
                                           const u8 *buf, int oob_required,
                                           int page)
 {
@@ -893,8 +874,8 @@ static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
        if (ret)
                return ret;
 
-       atmel_nand_read_buf(mtd, buf, mtd->writesize);
-       atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
+       atmel_nand_read_buf(chip, buf, mtd->writesize);
+       atmel_nand_read_buf(chip, chip->oob_poi, mtd->oobsize);
 
        ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 
@@ -903,15 +884,13 @@ static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
        return ret;
 }
 
-static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
-                                     struct nand_chip *chip, u8 *buf,
+static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
                                      int oob_required, int page)
 {
        return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 }
 
-static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
-                                         struct nand_chip *chip, u8 *buf,
+static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf,
                                          int oob_required, int page)
 {
        return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
@@ -956,7 +935,7 @@ static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
        if (ret)
                return ret;
 
-       atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
+       atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize);
 
        nc->op.cmds[0] = NAND_CMD_PAGEPROG;
        nc->op.ncmds = 1;
@@ -966,15 +945,14 @@ static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
                dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
                        ret);
 
-       status = chip->waitfunc(mtd, chip);
+       status = chip->legacy.waitfunc(chip);
        if (status & NAND_STATUS_FAIL)
                return -EIO;
 
        return ret;
 }
 
-static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
-                                           struct nand_chip *chip,
+static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip,
                                            const u8 *buf, int oob_required,
                                            int page)
 {
@@ -982,8 +960,7 @@ static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
                                              false);
 }
 
-static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
-                                               struct nand_chip *chip,
+static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip,
                                                const u8 *buf,
                                                int oob_required, int page)
 {
@@ -1045,16 +1022,14 @@ static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
        return ret;
 }
 
-static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
-                                          struct nand_chip *chip, u8 *buf,
+static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
                                           int oob_required, int page)
 {
        return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
                                             false);
 }
 
-static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
-                                              struct nand_chip *chip,
+static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip,
                                               u8 *buf, int oob_required,
                                               int page)
 {
@@ -1473,10 +1448,9 @@ static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
        return 0;
 }
 
-static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
+static int atmel_nand_setup_data_interface(struct nand_chip *chip, int csline,
                                        const struct nand_data_interface *conf)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct atmel_nand *nand = to_atmel_nand(chip);
        struct atmel_nand_controller *nc;
 
@@ -1498,19 +1472,18 @@ static void atmel_nand_init(struct atmel_nand_controller *nc,
        mtd->dev.parent = nc->dev;
        nand->base.controller = &nc->base;
 
-       chip->cmd_ctrl = atmel_nand_cmd_ctrl;
-       chip->read_byte = atmel_nand_read_byte;
-       chip->read_word = atmel_nand_read_word;
-       chip->write_byte = atmel_nand_write_byte;
-       chip->read_buf = atmel_nand_read_buf;
-       chip->write_buf = atmel_nand_write_buf;
+       chip->legacy.cmd_ctrl = atmel_nand_cmd_ctrl;
+       chip->legacy.read_byte = atmel_nand_read_byte;
+       chip->legacy.write_byte = atmel_nand_write_byte;
+       chip->legacy.read_buf = atmel_nand_read_buf;
+       chip->legacy.write_buf = atmel_nand_write_buf;
        chip->select_chip = atmel_nand_select_chip;
 
        if (nc->mck && nc->caps->ops->setup_data_interface)
                chip->setup_data_interface = atmel_nand_setup_data_interface;
 
        /* Some NANDs require a longer delay than the default one (20us). */
-       chip->chip_delay = 40;
+       chip->legacy.chip_delay = 40;
 
        /*
         * Use a bounce buffer when the buffer passed by the MTD user is not
@@ -1551,7 +1524,7 @@ static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
        atmel_nand_init(nc, nand);
 
        /* Overload some methods for the HSMC controller. */
-       chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
+       chip->legacy.cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
        chip->select_chip = atmel_hsmc_nand_select_chip;
 }
 
@@ -1586,9 +1559,7 @@ static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
                return ERR_PTR(-EINVAL);
        }
 
-       nand = devm_kzalloc(nc->dev,
-                           sizeof(*nand) + (numcs * sizeof(*nand->cs)),
-                           GFP_KERNEL);
+       nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);
        if (!nand) {
                dev_err(nc->dev, "Failed to allocate NAND object\n");
                return ERR_PTR(-ENOMEM);
@@ -1694,7 +1665,7 @@ atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
 
        nc->caps->ops->nand_init(nc, nand);
 
-       ret = nand_scan(mtd, nand->numcs);
+       ret = nand_scan(chip, nand->numcs);
        if (ret) {
                dev_err(nc->dev, "NAND scan failed: %d\n", ret);
                return ret;
@@ -2063,6 +2034,10 @@ atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
        nand_np = dev->of_node;
        nfc_np = of_find_compatible_node(dev->of_node, NULL,
                                         "atmel,sama5d3-nfc");
+       if (!nfc_np) {
+               dev_err(dev, "Could not find device node for sama5d3-nfc\n");
+               return -ENODEV;
+       }
 
        nc->clk = of_clk_get(nfc_np, 0);
        if (IS_ERR(nc->clk)) {
index 35f5c84cd33162e4a290ce96795c4dc4a8d40d11..9731c1c487f6e723d54d8cad1af98e043c68291d 100644 (file)
@@ -24,134 +24,113 @@ struct au1550nd_ctx {
 
        int cs;
        void __iomem *base;
-       void (*write_byte)(struct mtd_info *, u_char);
+       void (*write_byte)(struct nand_chip *, u_char);
 };
 
 /**
  * au_read_byte -  read one byte from the chip
- * @mtd:       MTD device structure
+ * @this:      NAND chip object
  *
  * read function for 8bit buswidth
  */
-static u_char au_read_byte(struct mtd_info *mtd)
+static u_char au_read_byte(struct nand_chip *this)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       u_char ret = readb(this->IO_ADDR_R);
+       u_char ret = readb(this->legacy.IO_ADDR_R);
        wmb(); /* drain writebuffer */
        return ret;
 }
 
 /**
  * au_write_byte -  write one byte to the chip
- * @mtd:       MTD device structure
+ * @this:      NAND chip object
  * @byte:      pointer to data byte to write
  *
  * write function for 8it buswidth
  */
-static void au_write_byte(struct mtd_info *mtd, u_char byte)
+static void au_write_byte(struct nand_chip *this, u_char byte)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       writeb(byte, this->IO_ADDR_W);
+       writeb(byte, this->legacy.IO_ADDR_W);
        wmb(); /* drain writebuffer */
 }
 
 /**
  * au_read_byte16 -  read one byte endianness aware from the chip
- * @mtd:       MTD device structure
+ * @this:      NAND chip object
  *
  * read function for 16bit buswidth with endianness conversion
  */
-static u_char au_read_byte16(struct mtd_info *mtd)
+static u_char au_read_byte16(struct nand_chip *this)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
+       u_char ret = (u_char) cpu_to_le16(readw(this->legacy.IO_ADDR_R));
        wmb(); /* drain writebuffer */
        return ret;
 }
 
 /**
  * au_write_byte16 -  write one byte endianness aware to the chip
- * @mtd:       MTD device structure
+ * @this:      NAND chip object
  * @byte:      pointer to data byte to write
  *
  * write function for 16bit buswidth with endianness conversion
  */
-static void au_write_byte16(struct mtd_info *mtd, u_char byte)
+static void au_write_byte16(struct nand_chip *this, u_char byte)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
+       writew(le16_to_cpu((u16) byte), this->legacy.IO_ADDR_W);
        wmb(); /* drain writebuffer */
 }
 
-/**
- * au_read_word -  read one word from the chip
- * @mtd:       MTD device structure
- *
- * read function for 16bit buswidth without endianness conversion
- */
-static u16 au_read_word(struct mtd_info *mtd)
-{
-       struct nand_chip *this = mtd_to_nand(mtd);
-       u16 ret = readw(this->IO_ADDR_R);
-       wmb(); /* drain writebuffer */
-       return ret;
-}
-
 /**
  * au_write_buf -  write buffer to chip
- * @mtd:       MTD device structure
+ * @this:      NAND chip object
  * @buf:       data buffer
  * @len:       number of bytes to write
  *
  * write function for 8bit buswidth
  */
-static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+static void au_write_buf(struct nand_chip *this, const u_char *buf, int len)
 {
        int i;
-       struct nand_chip *this = mtd_to_nand(mtd);
 
        for (i = 0; i < len; i++) {
-               writeb(buf[i], this->IO_ADDR_W);
+               writeb(buf[i], this->legacy.IO_ADDR_W);
                wmb(); /* drain writebuffer */
        }
 }
 
 /**
  * au_read_buf -  read chip data into buffer
- * @mtd:       MTD device structure
+ * @this:      NAND chip object
  * @buf:       buffer to store date
  * @len:       number of bytes to read
  *
  * read function for 8bit buswidth
  */
-static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+static void au_read_buf(struct nand_chip *this, u_char *buf, int len)
 {
        int i;
-       struct nand_chip *this = mtd_to_nand(mtd);
 
        for (i = 0; i < len; i++) {
-               buf[i] = readb(this->IO_ADDR_R);
+               buf[i] = readb(this->legacy.IO_ADDR_R);
                wmb(); /* drain writebuffer */
        }
 }
 
 /**
  * au_write_buf16 -  write buffer to chip
- * @mtd:       MTD device structure
+ * @this:      NAND chip object
  * @buf:       data buffer
  * @len:       number of bytes to write
  *
  * write function for 16bit buswidth
  */
-static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
+static void au_write_buf16(struct nand_chip *this, const u_char *buf, int len)
 {
        int i;
-       struct nand_chip *this = mtd_to_nand(mtd);
        u16 *p = (u16 *) buf;
        len >>= 1;
 
        for (i = 0; i < len; i++) {
-               writew(p[i], this->IO_ADDR_W);
+               writew(p[i], this->legacy.IO_ADDR_W);
                wmb(); /* drain writebuffer */
        }
 
@@ -173,7 +152,7 @@ static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
        len >>= 1;
 
        for (i = 0; i < len; i++) {
-               p[i] = readw(this->IO_ADDR_R);
+               p[i] = readw(this->legacy.IO_ADDR_R);
                wmb(); /* drain writebuffer */
        }
 }
@@ -200,19 +179,19 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
        switch (cmd) {
 
        case NAND_CTL_SETCLE:
-               this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
+               this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
                break;
 
        case NAND_CTL_CLRCLE:
-               this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
+               this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
                break;
 
        case NAND_CTL_SETALE:
-               this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
+               this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
                break;
 
        case NAND_CTL_CLRALE:
-               this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
+               this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
                /* FIXME: Nobody knows why this is necessary,
                 * but it works only that way */
                udelay(1);
@@ -229,12 +208,12 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
                break;
        }
 
-       this->IO_ADDR_R = this->IO_ADDR_W;
+       this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W;
 
        wmb(); /* Drain the writebuffer */
 }
 
-int au1550_device_ready(struct mtd_info *mtd)
+int au1550_device_ready(struct nand_chip *this)
 {
        return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
 }
@@ -248,23 +227,24 @@ int au1550_device_ready(struct mtd_info *mtd)
  *     chip needs it to be asserted during chip not ready time but the NAND
  *     controller keeps it released.
  *
- * @mtd:       MTD device structure
+ * @this:      NAND chip object
  * @chip:      chipnumber to select, -1 for deselect
  */
-static void au1550_select_chip(struct mtd_info *mtd, int chip)
+static void au1550_select_chip(struct nand_chip *this, int chip)
 {
 }
 
 /**
  * au1550_command - Send command to NAND device
- * @mtd:       MTD device structure
+ * @this:      NAND chip object
  * @command:   the command to be sent
  * @column:    the column address for this command, -1 if none
  * @page_addr: the page address for this command, -1 if none
  */
-static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
+static void au1550_command(struct nand_chip *this, unsigned command,
+                          int column, int page_addr)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(this);
        struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
                                                chip);
        int ce_override = 0, i;
@@ -289,9 +269,9 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
                        column -= 256;
                        readcmd = NAND_CMD_READ1;
                }
-               ctx->write_byte(mtd, readcmd);
+               ctx->write_byte(this, readcmd);
        }
-       ctx->write_byte(mtd, command);
+       ctx->write_byte(this, command);
 
        /* Set ALE and clear CLE to start address cycle */
        au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
@@ -305,10 +285,10 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
                        if (this->options & NAND_BUSWIDTH_16 &&
                                        !nand_opcode_8bits(command))
                                column >>= 1;
-                       ctx->write_byte(mtd, column);
+                       ctx->write_byte(this, column);
                }
                if (page_addr != -1) {
-                       ctx->write_byte(mtd, (u8)(page_addr & 0xff));
+                       ctx->write_byte(this, (u8)(page_addr & 0xff));
 
                        if (command == NAND_CMD_READ0 ||
                            command == NAND_CMD_READ1 ||
@@ -326,10 +306,10 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
                                au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
                        }
 
-                       ctx->write_byte(mtd, (u8)(page_addr >> 8));
+                       ctx->write_byte(this, (u8)(page_addr >> 8));
 
                        if (this->options & NAND_ROW_ADDR_3)
-                               ctx->write_byte(mtd,
+                               ctx->write_byte(this,
                                                ((page_addr >> 16) & 0x0f));
                }
                /* Latch in address */
@@ -362,7 +342,8 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
                /* Apply a short delay always to ensure that we do wait tWB. */
                ndelay(100);
                /* Wait for a chip to become ready... */
-               for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
+               for (i = this->legacy.chip_delay;
+                    !this->legacy.dev_ready(this) && i > 0; --i)
                        udelay(1);
 
                /* Release -CE and re-enable interrupts. */
@@ -373,7 +354,7 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
        /* Apply this short delay always to ensure that we do wait tWB. */
        ndelay(100);
 
-       while(!this->dev_ready(mtd));
+       while(!this->legacy.dev_ready(this));
 }
 
 static int find_nand_cs(unsigned long nand_base)
@@ -448,25 +429,24 @@ static int au1550nd_probe(struct platform_device *pdev)
        }
        ctx->cs = cs;
 
-       this->dev_ready = au1550_device_ready;
+       this->legacy.dev_ready = au1550_device_ready;
        this->select_chip = au1550_select_chip;
-       this->cmdfunc = au1550_command;
+       this->legacy.cmdfunc = au1550_command;
 
        /* 30 us command delay time */
-       this->chip_delay = 30;
+       this->legacy.chip_delay = 30;
        this->ecc.mode = NAND_ECC_SOFT;
        this->ecc.algo = NAND_ECC_HAMMING;
 
        if (pd->devwidth)
                this->options |= NAND_BUSWIDTH_16;
 
-       this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
+       this->legacy.read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
        ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
-       this->read_word = au_read_word;
-       this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
-       this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
+       this->legacy.write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
+       this->legacy.read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
 
-       ret = nand_scan(mtd, 1);
+       ret = nand_scan(this, 1);
        if (ret) {
                dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
                goto out3;
@@ -492,7 +472,7 @@ static int au1550nd_remove(struct platform_device *pdev)
        struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
        struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
-       nand_release(nand_to_mtd(&ctx->chip));
+       nand_release(&ctx->chip);
        iounmap(ctx->base);
        release_mem_region(r->start, 0x1000);
        kfree(ctx);
index fb31429b70a9a2428d45daee8e9c3c45b3f2b542..d79694160845760f03fa59a40173e348756e3418 100644 (file)
@@ -65,7 +65,7 @@ static int bcm47xxnflash_remove(struct platform_device *pdev)
 {
        struct bcm47xxnflash *nflash = platform_get_drvdata(pdev);
 
-       nand_release(nand_to_mtd(&nflash->nand_chip));
+       nand_release(&nflash->nand_chip);
 
        return 0;
 }
index 60874de430eb7b743327f204d5d4cfcd6f770adf..9095a79ebc7db4f3d3273958cff7551ea99ba10f 100644 (file)
@@ -170,10 +170,9 @@ static void bcm47xxnflash_ops_bcm4706_write(struct mtd_info *mtd,
  * NAND chip ops
  **************************************************/
 
-static void bcm47xxnflash_ops_bcm4706_cmd_ctrl(struct mtd_info *mtd, int cmd,
-                                              unsigned int ctrl)
+static void bcm47xxnflash_ops_bcm4706_cmd_ctrl(struct nand_chip *nand_chip,
+                                              int cmd, unsigned int ctrl)
 {
-       struct nand_chip *nand_chip = mtd_to_nand(mtd);
        struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
        u32 code = 0;
 
@@ -191,15 +190,14 @@ static void bcm47xxnflash_ops_bcm4706_cmd_ctrl(struct mtd_info *mtd, int cmd,
 }
 
 /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
-static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
-                                                 int chip)
+static void bcm47xxnflash_ops_bcm4706_select_chip(struct nand_chip *chip,
+                                                 int cs)
 {
        return;
 }
 
-static int bcm47xxnflash_ops_bcm4706_dev_ready(struct mtd_info *mtd)
+static int bcm47xxnflash_ops_bcm4706_dev_ready(struct nand_chip *nand_chip)
 {
-       struct nand_chip *nand_chip = mtd_to_nand(mtd);
        struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
 
        return !!(bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_CTL) & NCTL_READY);
@@ -212,11 +210,11 @@ static int bcm47xxnflash_ops_bcm4706_dev_ready(struct mtd_info *mtd)
  * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert
  * standard commands would be much more complicated.
  */
-static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
+static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct nand_chip *nand_chip,
                                              unsigned command, int column,
                                              int page_addr)
 {
-       struct nand_chip *nand_chip = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(nand_chip);
        struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
        struct bcma_drv_cc *cc = b47n->cc;
        u32 ctlcode;
@@ -229,10 +227,10 @@ static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
 
        switch (command) {
        case NAND_CMD_RESET:
-               nand_chip->cmd_ctrl(mtd, command, NAND_CTRL_CLE);
+               nand_chip->legacy.cmd_ctrl(nand_chip, command, NAND_CTRL_CLE);
 
                ndelay(100);
-               nand_wait_ready(mtd);
+               nand_wait_ready(nand_chip);
                break;
        case NAND_CMD_READID:
                ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0;
@@ -310,9 +308,9 @@ static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
        b47n->curr_command = command;
 }
 
-static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
+static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct nand_chip *nand_chip)
 {
-       struct nand_chip *nand_chip = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(nand_chip);
        struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
        struct bcma_drv_cc *cc = b47n->cc;
        u32 tmp = 0;
@@ -338,31 +336,31 @@ static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
        return 0;
 }
 
-static void bcm47xxnflash_ops_bcm4706_read_buf(struct mtd_info *mtd,
+static void bcm47xxnflash_ops_bcm4706_read_buf(struct nand_chip *nand_chip,
                                               uint8_t *buf, int len)
 {
-       struct nand_chip *nand_chip = mtd_to_nand(mtd);
        struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
 
        switch (b47n->curr_command) {
        case NAND_CMD_READ0:
        case NAND_CMD_READOOB:
-               bcm47xxnflash_ops_bcm4706_read(mtd, buf, len);
+               bcm47xxnflash_ops_bcm4706_read(nand_to_mtd(nand_chip), buf,
+                                              len);
                return;
        }
 
        pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
 }
 
-static void bcm47xxnflash_ops_bcm4706_write_buf(struct mtd_info *mtd,
+static void bcm47xxnflash_ops_bcm4706_write_buf(struct nand_chip *nand_chip,
                                                const uint8_t *buf, int len)
 {
-       struct nand_chip *nand_chip = mtd_to_nand(mtd);
        struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
 
        switch (b47n->curr_command) {
        case NAND_CMD_SEQIN:
-               bcm47xxnflash_ops_bcm4706_write(mtd, buf, len);
+               bcm47xxnflash_ops_bcm4706_write(nand_to_mtd(nand_chip), buf,
+                                               len);
                return;
        }
 
@@ -386,16 +384,16 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
        u32 val;
 
        b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
-       nand_chip->cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl;
-       nand_chip->dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
-       b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
-       b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
-       b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
-       b47n->nand_chip.write_buf = bcm47xxnflash_ops_bcm4706_write_buf;
-       b47n->nand_chip.set_features = nand_get_set_features_notsupp;
-       b47n->nand_chip.get_features = nand_get_set_features_notsupp;
-
-       nand_chip->chip_delay = 50;
+       nand_chip->legacy.cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl;
+       nand_chip->legacy.dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
+       b47n->nand_chip.legacy.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
+       b47n->nand_chip.legacy.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
+       b47n->nand_chip.legacy.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
+       b47n->nand_chip.legacy.write_buf = bcm47xxnflash_ops_bcm4706_write_buf;
+       b47n->nand_chip.legacy.set_features = nand_get_set_features_notsupp;
+       b47n->nand_chip.legacy.get_features = nand_get_set_features_notsupp;
+
+       nand_chip->legacy.chip_delay = 50;
        b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
        b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
 
@@ -423,7 +421,7 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
                        (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
 
        /* Scan NAND */
-       err = nand_scan(nand_to_mtd(&b47n->nand_chip), 1);
+       err = nand_scan(&b47n->nand_chip, 1);
        if (err) {
                pr_err("Could not scan NAND flash: %d\n", err);
                goto exit;
index 4b90d5b380c2503fc88426890f719bd018d6d2f7..482c6f093f996cb5f2f04c0ab2389d5cc49a5c61 100644 (file)
@@ -1231,15 +1231,14 @@ static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
  * NAND MTD API: read/program/erase
  ***********************************************************************/
 
-static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
-       unsigned int ctrl)
+static void brcmnand_cmd_ctrl(struct nand_chip *chip, int dat,
+                             unsigned int ctrl)
 {
        /* intentionally left blank */
 }
 
-static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
+static int brcmnand_waitfunc(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct brcmnand_host *host = nand_get_controller_data(chip);
        struct brcmnand_controller *ctrl = host->ctrl;
        unsigned long timeo = msecs_to_jiffies(100);
@@ -1274,7 +1273,6 @@ static int brcmnand_low_level_op(struct brcmnand_host *host,
                                 enum brcmnand_llop_type type, u32 data,
                                 bool last_op)
 {
-       struct mtd_info *mtd = nand_to_mtd(&host->chip);
        struct nand_chip *chip = &host->chip;
        struct brcmnand_controller *ctrl = host->ctrl;
        u32 tmp;
@@ -1307,13 +1305,13 @@ static int brcmnand_low_level_op(struct brcmnand_host *host,
        (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
 
        brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
-       return brcmnand_waitfunc(mtd, chip);
+       return brcmnand_waitfunc(chip);
 }
 
-static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
+static void brcmnand_cmdfunc(struct nand_chip *chip, unsigned command,
                             int column, int page_addr)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct brcmnand_host *host = nand_get_controller_data(chip);
        struct brcmnand_controller *ctrl = host->ctrl;
        u64 addr = (u64)page_addr << chip->page_shift;
@@ -1383,7 +1381,7 @@ static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
        (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
 
        brcmnand_send_cmd(host, native_cmd);
-       brcmnand_waitfunc(mtd, chip);
+       brcmnand_waitfunc(chip);
 
        if (native_cmd == CMD_PARAMETER_READ ||
                        native_cmd == CMD_PARAMETER_CHANGE_COL) {
@@ -1417,9 +1415,8 @@ static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
                brcmnand_wp(mtd, 1);
 }
 
-static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
+static uint8_t brcmnand_read_byte(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct brcmnand_host *host = nand_get_controller_data(chip);
        struct brcmnand_controller *ctrl = host->ctrl;
        uint8_t ret = 0;
@@ -1474,19 +1471,18 @@ static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
        return ret;
 }
 
-static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+static void brcmnand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
 {
        int i;
 
        for (i = 0; i < len; i++, buf++)
-               *buf = brcmnand_read_byte(mtd);
+               *buf = brcmnand_read_byte(chip);
 }
 
-static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
-                                  int len)
+static void brcmnand_write_buf(struct nand_chip *chip, const uint8_t *buf,
+                              int len)
 {
        int i;
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct brcmnand_host *host = nand_get_controller_data(chip);
 
        switch (host->last_cmd) {
@@ -1617,7 +1613,7 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
                (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
                /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
                brcmnand_send_cmd(host, CMD_PAGE_READ);
-               brcmnand_waitfunc(mtd, chip);
+               brcmnand_waitfunc(chip);
 
                if (likely(buf)) {
                        brcmnand_soc_data_bus_prepare(ctrl->soc, false);
@@ -1689,7 +1685,7 @@ static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
        sas = mtd->oobsize / chip->ecc.steps;
 
        /* read without ecc for verification */
-       ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
+       ret = chip->ecc.read_page_raw(chip, buf, true, page);
        if (ret)
                return ret;
 
@@ -1786,9 +1782,10 @@ try_dmaread:
        return 0;
 }
 
-static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
-                             uint8_t *buf, int oob_required, int page)
+static int brcmnand_read_page(struct nand_chip *chip, uint8_t *buf,
+                             int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct brcmnand_host *host = nand_get_controller_data(chip);
        u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
 
@@ -1798,10 +1795,11 @@ static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
                        mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
 }
 
-static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-                                 uint8_t *buf, int oob_required, int page)
+static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf,
+                                 int oob_required, int page)
 {
        struct brcmnand_host *host = nand_get_controller_data(chip);
+       struct mtd_info *mtd = nand_to_mtd(chip);
        u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
        int ret;
 
@@ -1814,17 +1812,18 @@ static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
        return ret;
 }
 
-static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
-                            int page)
+static int brcmnand_read_oob(struct nand_chip *chip, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
+
        return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
                        mtd->writesize >> FC_SHIFT,
                        NULL, (u8 *)chip->oob_poi);
 }
 
-static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
-                                int page)
+static int brcmnand_read_oob_raw(struct nand_chip *chip, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct brcmnand_host *host = nand_get_controller_data(chip);
 
        brcmnand_set_ecc_enabled(host, 0);
@@ -1892,7 +1891,7 @@ static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
 
                /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
                brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
-               status = brcmnand_waitfunc(mtd, chip);
+               status = brcmnand_waitfunc(chip);
 
                if (status & NAND_STATUS_FAIL) {
                        dev_info(ctrl->dev, "program failed at %llx\n",
@@ -1906,9 +1905,10 @@ out:
        return ret;
 }
 
-static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-                              const uint8_t *buf, int oob_required, int page)
+static int brcmnand_write_page(struct nand_chip *chip, const uint8_t *buf,
+                              int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct brcmnand_host *host = nand_get_controller_data(chip);
        void *oob = oob_required ? chip->oob_poi : NULL;
 
@@ -1918,10 +1918,10 @@ static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
        return nand_prog_page_end_op(chip);
 }
 
-static int brcmnand_write_page_raw(struct mtd_info *mtd,
-                                  struct nand_chip *chip, const uint8_t *buf,
+static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
                                   int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct brcmnand_host *host = nand_get_controller_data(chip);
        void *oob = oob_required ? chip->oob_poi : NULL;
 
@@ -1933,16 +1933,16 @@ static int brcmnand_write_page_raw(struct mtd_info *mtd,
        return nand_prog_page_end_op(chip);
 }
 
-static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
-                                 int page)
+static int brcmnand_write_oob(struct nand_chip *chip, int page)
 {
-       return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
-                                 NULL, chip->oob_poi);
+       return brcmnand_write(nand_to_mtd(chip), chip,
+                             (u64)page << chip->page_shift, NULL,
+                             chip->oob_poi);
 }
 
-static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
-                                 int page)
+static int brcmnand_write_oob_raw(struct nand_chip *chip, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct brcmnand_host *host = nand_get_controller_data(chip);
        int ret;
 
@@ -2270,15 +2270,12 @@ static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
        mtd->owner = THIS_MODULE;
        mtd->dev.parent = &pdev->dev;
 
-       chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
-       chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
-
-       chip->cmd_ctrl = brcmnand_cmd_ctrl;
-       chip->cmdfunc = brcmnand_cmdfunc;
-       chip->waitfunc = brcmnand_waitfunc;
-       chip->read_byte = brcmnand_read_byte;
-       chip->read_buf = brcmnand_read_buf;
-       chip->write_buf = brcmnand_write_buf;
+       chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl;
+       chip->legacy.cmdfunc = brcmnand_cmdfunc;
+       chip->legacy.waitfunc = brcmnand_waitfunc;
+       chip->legacy.read_byte = brcmnand_read_byte;
+       chip->legacy.read_buf = brcmnand_read_buf;
+       chip->legacy.write_buf = brcmnand_write_buf;
 
        chip->ecc.mode = NAND_ECC_HW;
        chip->ecc.read_page = brcmnand_read_page;
@@ -2301,7 +2298,7 @@ static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
        nand_writereg(ctrl, cfg_offs,
                      nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
 
-       ret = nand_scan(mtd, 1);
+       ret = nand_scan(chip, 1);
        if (ret)
                return ret;
 
@@ -2616,7 +2613,7 @@ int brcmnand_remove(struct platform_device *pdev)
        struct brcmnand_host *host;
 
        list_for_each_entry(host, &ctrl->host_list, node)
-               nand_release(nand_to_mtd(&host->chip));
+               nand_release(&host->chip);
 
        clk_disable_unprepare(ctrl->clk);
 
index 1dbe43adcfe7d550aabb31885a0f366e21cc6b1a..c1a745940d12936123433878b5c63b4a81c39002 100644 (file)
@@ -100,9 +100,8 @@ static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
 #define cafe_readl(cafe, addr)                 readl((cafe)->mmio + CAFE_##addr)
 #define cafe_writel(cafe, datum, addr)         writel(datum, (cafe)->mmio + CAFE_##addr)
 
-static int cafe_device_ready(struct mtd_info *mtd)
+static int cafe_device_ready(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct cafe_priv *cafe = nand_get_controller_data(chip);
        int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
        uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
@@ -117,9 +116,8 @@ static int cafe_device_ready(struct mtd_info *mtd)
 }
 
 
-static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+static void cafe_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct cafe_priv *cafe = nand_get_controller_data(chip);
 
        if (cafe->usedma)
@@ -133,9 +131,8 @@ static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
                len, cafe->datalen);
 }
 
-static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+static void cafe_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct cafe_priv *cafe = nand_get_controller_data(chip);
 
        if (cafe->usedma)
@@ -148,22 +145,21 @@ static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
        cafe->datalen += len;
 }
 
-static uint8_t cafe_read_byte(struct mtd_info *mtd)
+static uint8_t cafe_read_byte(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct cafe_priv *cafe = nand_get_controller_data(chip);
        uint8_t d;
 
-       cafe_read_buf(mtd, &d, 1);
+       cafe_read_buf(chip, &d, 1);
        cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
 
        return d;
 }
 
-static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
+static void cafe_nand_cmdfunc(struct nand_chip *chip, unsigned command,
                              int column, int page_addr)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct cafe_priv *cafe = nand_get_controller_data(chip);
        int adrbytes = 0;
        uint32_t ctl1;
@@ -313,13 +309,12 @@ static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
                cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
                return;
        }
-       nand_wait_ready(mtd);
+       nand_wait_ready(chip);
        cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
 }
 
-static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
+static void cafe_select_chip(struct nand_chip *chip, int chipnr)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct cafe_priv *cafe = nand_get_controller_data(chip);
 
        cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
@@ -346,17 +341,19 @@ static irqreturn_t cafe_nand_interrupt(int irq, void *id)
        return IRQ_HANDLED;
 }
 
-static int cafe_nand_write_oob(struct mtd_info *mtd,
-                              struct nand_chip *chip, int page)
+static int cafe_nand_write_oob(struct nand_chip *chip, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
+
        return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
                                 mtd->oobsize);
 }
 
 /* Don't use -- use nand_read_oob_std for now */
-static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
-                             int page)
+static int cafe_nand_read_oob(struct nand_chip *chip, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
+
        return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
 }
 /**
@@ -369,9 +366,10 @@ static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  * The hw generator calculates the error syndrome automatically. Therefore
  * we need a special oob layout and handling.
  */
-static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
-                              uint8_t *buf, int oob_required, int page)
+static int cafe_nand_read_page(struct nand_chip *chip, uint8_t *buf,
+                              int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct cafe_priv *cafe = nand_get_controller_data(chip);
        unsigned int max_bitflips = 0;
 
@@ -380,7 +378,7 @@ static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
                     cafe_readl(cafe, NAND_ECC_SYN01));
 
        nand_read_page_op(chip, page, 0, buf, mtd->writesize);
-       chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+       chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
 
        if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
                unsigned short syn[8], pat[4];
@@ -531,15 +529,15 @@ static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
 };
 
 
-static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
-                                         struct nand_chip *chip,
-                                         const uint8_t *buf, int oob_required,
-                                         int page)
+static int cafe_nand_write_page_lowlevel(struct nand_chip *chip,
+                                        const uint8_t *buf, int oob_required,
+                                        int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct cafe_priv *cafe = nand_get_controller_data(chip);
 
        nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
-       chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+       chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
 
        /* Set up ECC autogeneration */
        cafe->ctl2 |= (1<<30);
@@ -547,7 +545,7 @@ static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
        return nand_prog_page_end_op(chip);
 }
 
-static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
+static int cafe_nand_block_bad(struct nand_chip *chip, loff_t ofs)
 {
        return 0;
 }
@@ -705,23 +703,23 @@ static int cafe_nand_probe(struct pci_dev *pdev,
                goto out_ior;
        }
 
-       cafe->nand.cmdfunc = cafe_nand_cmdfunc;
-       cafe->nand.dev_ready = cafe_device_ready;
-       cafe->nand.read_byte = cafe_read_byte;
-       cafe->nand.read_buf = cafe_read_buf;
-       cafe->nand.write_buf = cafe_write_buf;
+       cafe->nand.legacy.cmdfunc = cafe_nand_cmdfunc;
+       cafe->nand.legacy.dev_ready = cafe_device_ready;
+       cafe->nand.legacy.read_byte = cafe_read_byte;
+       cafe->nand.legacy.read_buf = cafe_read_buf;
+       cafe->nand.legacy.write_buf = cafe_write_buf;
        cafe->nand.select_chip = cafe_select_chip;
-       cafe->nand.set_features = nand_get_set_features_notsupp;
-       cafe->nand.get_features = nand_get_set_features_notsupp;
+       cafe->nand.legacy.set_features = nand_get_set_features_notsupp;
+       cafe->nand.legacy.get_features = nand_get_set_features_notsupp;
 
-       cafe->nand.chip_delay = 0;
+       cafe->nand.legacy.chip_delay = 0;
 
        /* Enable the following for a flash based bad block table */
        cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
 
        if (skipbbt) {
                cafe->nand.options |= NAND_SKIP_BBTSCAN;
-               cafe->nand.block_bad = cafe_nand_block_bad;
+               cafe->nand.legacy.block_bad = cafe_nand_block_bad;
        }
 
        if (numtimings && numtimings != 3) {
@@ -783,7 +781,7 @@ static int cafe_nand_probe(struct pci_dev *pdev,
 
        /* Scan to find existence of the device */
        cafe->nand.dummy_controller.ops = &cafe_nand_controller_ops;
-       err = nand_scan(mtd, 2);
+       err = nand_scan(&cafe->nand, 2);
        if (err)
                goto out_irq;
 
@@ -819,7 +817,7 @@ static void cafe_nand_remove(struct pci_dev *pdev)
        /* Disable NAND IRQ in global IRQ mask register */
        cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
        free_irq(pdev->irq, mtd);
-       nand_release(mtd);
+       nand_release(chip);
        free_rs(cafe->rs);
        pci_iounmap(pdev, cafe->mmio);
        dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
index b66e254b680281b4b951866ad9492473f8544f3d..143e4acacaae2acbb9f4e1347f12e994e2b9f0c1 100644 (file)
@@ -49,29 +49,26 @@ static const struct mtd_partition partition_info[] = {
 };
 #define NUM_PARTITIONS (ARRAY_SIZE(partition_info))
 
-static u_char cmx270_read_byte(struct mtd_info *mtd)
+static u_char cmx270_read_byte(struct nand_chip *this)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-
-       return (readl(this->IO_ADDR_R) >> 16);
+       return (readl(this->legacy.IO_ADDR_R) >> 16);
 }
 
-static void cmx270_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+static void cmx270_write_buf(struct nand_chip *this, const u_char *buf,
+                            int len)
 {
        int i;
-       struct nand_chip *this = mtd_to_nand(mtd);
 
        for (i=0; i<len; i++)
-               writel((*buf++ << 16), this->IO_ADDR_W);
+               writel((*buf++ << 16), this->legacy.IO_ADDR_W);
 }
 
-static void cmx270_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+static void cmx270_read_buf(struct nand_chip *this, u_char *buf, int len)
 {
        int i;
-       struct nand_chip *this = mtd_to_nand(mtd);
 
        for (i=0; i<len; i++)
-               *buf++ = readl(this->IO_ADDR_R) >> 16;
+               *buf++ = readl(this->legacy.IO_ADDR_R) >> 16;
 }
 
 static inline void nand_cs_on(void)
@@ -89,11 +86,10 @@ static void nand_cs_off(void)
 /*
  *     hardware specific access to control-lines
  */
-static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
+static void cmx270_hwcontrol(struct nand_chip *this, int dat,
                             unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       unsigned int nandaddr = (unsigned int)this->IO_ADDR_W;
+       unsigned int nandaddr = (unsigned int)this->legacy.IO_ADDR_W;
 
        dsb();
 
@@ -113,9 +109,9 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
        }
 
        dsb();
-       this->IO_ADDR_W = (void __iomem*)nandaddr;
+       this->legacy.IO_ADDR_W = (void __iomem*)nandaddr;
        if (dat != NAND_CMD_NONE)
-               writel((dat << 16), this->IO_ADDR_W);
+               writel((dat << 16), this->legacy.IO_ADDR_W);
 
        dsb();
 }
@@ -123,7 +119,7 @@ static void cmx270_hwcontrol(struct mtd_info *mtd, int dat,
 /*
  *     read device ready pin
  */
-static int cmx270_device_ready(struct mtd_info *mtd)
+static int cmx270_device_ready(struct nand_chip *this)
 {
        dsb();
 
@@ -177,23 +173,23 @@ static int __init cmx270_init(void)
        cmx270_nand_mtd->owner = THIS_MODULE;
 
        /* insert callbacks */
-       this->IO_ADDR_R = cmx270_nand_io;
-       this->IO_ADDR_W = cmx270_nand_io;
-       this->cmd_ctrl = cmx270_hwcontrol;
-       this->dev_ready = cmx270_device_ready;
+       this->legacy.IO_ADDR_R = cmx270_nand_io;
+       this->legacy.IO_ADDR_W = cmx270_nand_io;
+       this->legacy.cmd_ctrl = cmx270_hwcontrol;
+       this->legacy.dev_ready = cmx270_device_ready;
 
        /* 15 us command delay time */
-       this->chip_delay = 20;
+       this->legacy.chip_delay = 20;
        this->ecc.mode = NAND_ECC_SOFT;
        this->ecc.algo = NAND_ECC_HAMMING;
 
        /* read/write functions */
-       this->read_byte = cmx270_read_byte;
-       this->read_buf = cmx270_read_buf;
-       this->write_buf = cmx270_write_buf;
+       this->legacy.read_byte = cmx270_read_byte;
+       this->legacy.read_buf = cmx270_read_buf;
+       this->legacy.write_buf = cmx270_write_buf;
 
        /* Scan to find existence of the device */
-       ret = nand_scan(cmx270_nand_mtd, 1);
+       ret = nand_scan(this, 1);
        if (ret) {
                pr_notice("No NAND device\n");
                goto err_scan;
@@ -228,7 +224,7 @@ module_init(cmx270_init);
 static void __exit cmx270_cleanup(void)
 {
        /* Release resources, unregister device */
-       nand_release(cmx270_nand_mtd);
+       nand_release(mtd_to_nand(cmx270_nand_mtd));
 
        gpio_free(GPIO_NAND_RB);
        gpio_free(GPIO_NAND_CS);
index beafad62e7d5007f4a2313cf1dd469b0fabf88f1..c6f578aff5d90415a0c1f62f640c75c6b9c8f1d6 100644 (file)
 #define CS_NAND_ECC_CLRECC     (1<<1)
 #define CS_NAND_ECC_ENECC      (1<<0)
 
-static void cs553x_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+static void cs553x_read_buf(struct nand_chip *this, u_char *buf, int len)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-
        while (unlikely(len > 0x800)) {
-               memcpy_fromio(buf, this->IO_ADDR_R, 0x800);
+               memcpy_fromio(buf, this->legacy.IO_ADDR_R, 0x800);
                buf += 0x800;
                len -= 0x800;
        }
-       memcpy_fromio(buf, this->IO_ADDR_R, len);
+       memcpy_fromio(buf, this->legacy.IO_ADDR_R, len);
 }
 
-static void cs553x_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+static void cs553x_write_buf(struct nand_chip *this, const u_char *buf, int len)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-
        while (unlikely(len > 0x800)) {
-               memcpy_toio(this->IO_ADDR_R, buf, 0x800);
+               memcpy_toio(this->legacy.IO_ADDR_R, buf, 0x800);
                buf += 0x800;
                len -= 0x800;
        }
-       memcpy_toio(this->IO_ADDR_R, buf, len);
+       memcpy_toio(this->legacy.IO_ADDR_R, buf, len);
 }
 
-static unsigned char cs553x_read_byte(struct mtd_info *mtd)
+static unsigned char cs553x_read_byte(struct nand_chip *this)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       return readb(this->IO_ADDR_R);
+       return readb(this->legacy.IO_ADDR_R);
 }
 
-static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)
+static void cs553x_write_byte(struct nand_chip *this, u_char byte)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        int i = 100000;
 
-       while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
+       while (i && readb(this->legacy.IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
                udelay(1);
                i--;
        }
-       writeb(byte, this->IO_ADDR_W + 0x801);
+       writeb(byte, this->legacy.IO_ADDR_W + 0x801);
 }
 
-static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd,
+static void cs553x_hwcontrol(struct nand_chip *this, int cmd,
                             unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       void __iomem *mmio_base = this->IO_ADDR_R;
+       void __iomem *mmio_base = this->legacy.IO_ADDR_R;
        if (ctrl & NAND_CTRL_CHANGE) {
                unsigned char ctl = (ctrl & ~NAND_CTRL_CHANGE ) ^ 0x01;
                writeb(ctl, mmio_base + MM_NAND_CTL);
        }
        if (cmd != NAND_CMD_NONE)
-               cs553x_write_byte(mtd, cmd);
+               cs553x_write_byte(this, cmd);
 }
 
-static int cs553x_device_ready(struct mtd_info *mtd)
+static int cs553x_device_ready(struct nand_chip *this)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       void __iomem *mmio_base = this->IO_ADDR_R;
+       void __iomem *mmio_base = this->legacy.IO_ADDR_R;
        unsigned char foo = readb(mmio_base + MM_NAND_STS);
 
        return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY);
 }
 
-static void cs_enable_hwecc(struct mtd_info *mtd, int mode)
+static void cs_enable_hwecc(struct nand_chip *this, int mode)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
-       void __iomem *mmio_base = this->IO_ADDR_R;
+       void __iomem *mmio_base = this->legacy.IO_ADDR_R;
 
        writeb(0x07, mmio_base + MM_NAND_ECC_CTL);
 }
 
-static int cs_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
+static int cs_calculate_ecc(struct nand_chip *this, const u_char *dat,
+                           u_char *ecc_code)
 {
        uint32_t ecc;
-       struct nand_chip *this = mtd_to_nand(mtd);
-       void __iomem *mmio_base = this->IO_ADDR_R;
+       void __iomem *mmio_base = this->legacy.IO_ADDR_R;
 
        ecc = readl(mmio_base + MM_NAND_STS);
 
@@ -208,20 +199,20 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
        new_mtd->owner = THIS_MODULE;
 
        /* map physical address */
-       this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);
-       if (!this->IO_ADDR_R) {
+       this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = ioremap(adr, 4096);
+       if (!this->legacy.IO_ADDR_R) {
                pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);
                err = -EIO;
                goto out_mtd;
        }
 
-       this->cmd_ctrl = cs553x_hwcontrol;
-       this->dev_ready = cs553x_device_ready;
-       this->read_byte = cs553x_read_byte;
-       this->read_buf = cs553x_read_buf;
-       this->write_buf = cs553x_write_buf;
+       this->legacy.cmd_ctrl = cs553x_hwcontrol;
+       this->legacy.dev_ready = cs553x_device_ready;
+       this->legacy.read_byte = cs553x_read_byte;
+       this->legacy.read_buf = cs553x_read_buf;
+       this->legacy.write_buf = cs553x_write_buf;
 
-       this->chip_delay = 0;
+       this->legacy.chip_delay = 0;
 
        this->ecc.mode = NAND_ECC_HW;
        this->ecc.size = 256;
@@ -241,7 +232,7 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
        }
 
        /* Scan to find existence of the device */
-       err = nand_scan(new_mtd, 1);
+       err = nand_scan(this, 1);
        if (err)
                goto out_free;
 
@@ -251,7 +242,7 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
 out_free:
        kfree(new_mtd->name);
 out_ior:
-       iounmap(this->IO_ADDR_R);
+       iounmap(this->legacy.IO_ADDR_R);
 out_mtd:
        kfree(this);
 out:
@@ -333,10 +324,10 @@ static void __exit cs553x_cleanup(void)
                        continue;
 
                this = mtd_to_nand(mtd);
-               mmio_base = this->IO_ADDR_R;
+               mmio_base = this->legacy.IO_ADDR_R;
 
                /* Release resources, unregister device */
-               nand_release(mtd);
+               nand_release(this);
                kfree(mtd->name);
                cs553x_mtd[i] = NULL;
 
index 40145e206a6b7a1d6c82de067c1e55069dd9a9d5..80f228d23cd26da3c118e595edd4e5406ef0610f 100644 (file)
@@ -97,12 +97,11 @@ static inline void davinci_nand_writel(struct davinci_nand_info *info,
  * Access to hardware control lines:  ALE, CLE, secondary chipselect.
  */
 
-static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
+static void nand_davinci_hwcontrol(struct nand_chip *nand, int cmd,
                                   unsigned int ctrl)
 {
-       struct davinci_nand_info        *info = to_davinci_nand(mtd);
+       struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(nand));
        void __iomem                    *addr = info->current_cs;
-       struct nand_chip                *nand = mtd_to_nand(mtd);
 
        /* Did the control lines change? */
        if (ctrl & NAND_CTRL_CHANGE) {
@@ -111,16 +110,16 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
                else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
                        addr += info->mask_ale;
 
-               nand->IO_ADDR_W = addr;
+               nand->legacy.IO_ADDR_W = addr;
        }
 
        if (cmd != NAND_CMD_NONE)
-               iowrite8(cmd, nand->IO_ADDR_W);
+               iowrite8(cmd, nand->legacy.IO_ADDR_W);
 }
 
-static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
+static void nand_davinci_select_chip(struct nand_chip *nand, int chip)
 {
-       struct davinci_nand_info        *info = to_davinci_nand(mtd);
+       struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(nand));
 
        info->current_cs = info->vaddr;
 
@@ -128,8 +127,8 @@ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
        if (chip > 0)
                info->current_cs += info->mask_chipsel;
 
-       info->chip.IO_ADDR_W = info->current_cs;
-       info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
+       info->chip.legacy.IO_ADDR_W = info->current_cs;
+       info->chip.legacy.IO_ADDR_R = info->chip.legacy.IO_ADDR_W;
 }
 
 /*----------------------------------------------------------------------*/
@@ -146,16 +145,16 @@ static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
                        + 4 * info->core_chipsel);
 }
 
-static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
+static void nand_davinci_hwctl_1bit(struct nand_chip *chip, int mode)
 {
        struct davinci_nand_info *info;
        uint32_t nandcfr;
        unsigned long flags;
 
-       info = to_davinci_nand(mtd);
+       info = to_davinci_nand(nand_to_mtd(chip));
 
        /* Reset ECC hardware */
-       nand_davinci_readecc_1bit(mtd);
+       nand_davinci_readecc_1bit(nand_to_mtd(chip));
 
        spin_lock_irqsave(&davinci_nand_lock, flags);
 
@@ -170,10 +169,10 @@ static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
 /*
  * Read hardware ECC value and pack into three bytes
  */
-static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
-                                     const u_char *dat, u_char *ecc_code)
+static int nand_davinci_calculate_1bit(struct nand_chip *chip,
+                                      const u_char *dat, u_char *ecc_code)
 {
-       unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
+       unsigned int ecc_val = nand_davinci_readecc_1bit(nand_to_mtd(chip));
        unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
 
        /* invert so that erased block ecc is correct */
@@ -185,10 +184,9 @@ static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
        return 0;
 }
 
-static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
+static int nand_davinci_correct_1bit(struct nand_chip *chip, u_char *dat,
                                     u_char *read_ecc, u_char *calc_ecc)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
                                          (read_ecc[2] << 16);
        uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
@@ -231,9 +229,9 @@ static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
  * OOB without recomputing ECC.
  */
 
-static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
+static void nand_davinci_hwctl_4bit(struct nand_chip *chip, int mode)
 {
-       struct davinci_nand_info *info = to_davinci_nand(mtd);
+       struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
        unsigned long flags;
        u32 val;
 
@@ -266,10 +264,10 @@ nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
 }
 
 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
-static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
-               const u_char *dat, u_char *ecc_code)
+static int nand_davinci_calculate_4bit(struct nand_chip *chip,
+                                      const u_char *dat, u_char *ecc_code)
 {
-       struct davinci_nand_info *info = to_davinci_nand(mtd);
+       struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
        u32 raw_ecc[4], *p;
        unsigned i;
 
@@ -303,11 +301,11 @@ static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
 /* Correct up to 4 bits in data we just read, using state left in the
  * hardware plus the ecc_code computed when it was first written.
  */
-static int nand_davinci_correct_4bit(struct mtd_info *mtd,
-               u_char *data, u_char *ecc_code, u_char *null)
+static int nand_davinci_correct_4bit(struct nand_chip *chip, u_char *data,
+                                    u_char *ecc_code, u_char *null)
 {
        int i;
-       struct davinci_nand_info *info = to_davinci_nand(mtd);
+       struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
        unsigned short ecc10[8];
        unsigned short *ecc16;
        u32 syndrome[4];
@@ -436,38 +434,35 @@ correct:
  * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
  * and have that transparently morphed into multiple NAND operations.
  */
-static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+static void nand_davinci_read_buf(struct nand_chip *chip, uint8_t *buf,
+                                 int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-
        if ((0x03 & ((uintptr_t)buf)) == 0 && (0x03 & len) == 0)
-               ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
+               ioread32_rep(chip->legacy.IO_ADDR_R, buf, len >> 2);
        else if ((0x01 & ((uintptr_t)buf)) == 0 && (0x01 & len) == 0)
-               ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
+               ioread16_rep(chip->legacy.IO_ADDR_R, buf, len >> 1);
        else
-               ioread8_rep(chip->IO_ADDR_R, buf, len);
+               ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
 }
 
-static void nand_davinci_write_buf(struct mtd_info *mtd,
-               const uint8_t *buf, int len)
+static void nand_davinci_write_buf(struct nand_chip *chip, const uint8_t *buf,
+                                  int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-
        if ((0x03 & ((uintptr_t)buf)) == 0 && (0x03 & len) == 0)
-               iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
+               iowrite32_rep(chip->legacy.IO_ADDR_R, buf, len >> 2);
        else if ((0x01 & ((uintptr_t)buf)) == 0 && (0x01 & len) == 0)
-               iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
+               iowrite16_rep(chip->legacy.IO_ADDR_R, buf, len >> 1);
        else
-               iowrite8_rep(chip->IO_ADDR_R, buf, len);
+               iowrite8_rep(chip->legacy.IO_ADDR_R, buf, len);
 }
 
 /*
  * Check hardware register for wait status. Returns 1 if device is ready,
  * 0 if it is still busy.
  */
-static int nand_davinci_dev_ready(struct mtd_info *mtd)
+static int nand_davinci_dev_ready(struct nand_chip *chip)
 {
-       struct davinci_nand_info *info = to_davinci_nand(mtd);
+       struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
 
        return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
 }
@@ -764,9 +759,9 @@ static int nand_davinci_probe(struct platform_device *pdev)
        mtd->dev.parent         = &pdev->dev;
        nand_set_flash_node(&info->chip, pdev->dev.of_node);
 
-       info->chip.IO_ADDR_R    = vaddr;
-       info->chip.IO_ADDR_W    = vaddr;
-       info->chip.chip_delay   = 0;
+       info->chip.legacy.IO_ADDR_R     = vaddr;
+       info->chip.legacy.IO_ADDR_W     = vaddr;
+       info->chip.legacy.chip_delay    = 0;
        info->chip.select_chip  = nand_davinci_select_chip;
 
        /* options such as NAND_BBT_USE_FLASH */
@@ -786,12 +781,12 @@ static int nand_davinci_probe(struct platform_device *pdev)
        info->mask_cle          = pdata->mask_cle ? : MASK_CLE;
 
        /* Set address of hardware control function */
-       info->chip.cmd_ctrl     = nand_davinci_hwcontrol;
-       info->chip.dev_ready    = nand_davinci_dev_ready;
+       info->chip.legacy.cmd_ctrl      = nand_davinci_hwcontrol;
+       info->chip.legacy.dev_ready     = nand_davinci_dev_ready;
 
        /* Speed up buffer I/O */
-       info->chip.read_buf     = nand_davinci_read_buf;
-       info->chip.write_buf    = nand_davinci_write_buf;
+       info->chip.legacy.read_buf     = nand_davinci_read_buf;
+       info->chip.legacy.write_buf    = nand_davinci_write_buf;
 
        /* Use board-specific ECC config */
        info->chip.ecc.mode     = pdata->ecc_mode;
@@ -807,7 +802,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
 
        /* Scan to find existence of the device(s) */
        info->chip.dummy_controller.ops = &davinci_nand_controller_ops;
-       ret = nand_scan(mtd, pdata->mask_chipsel ? 2 : 1);
+       ret = nand_scan(&info->chip, pdata->mask_chipsel ? 2 : 1);
        if (ret < 0) {
                dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
                return ret;
@@ -841,7 +836,7 @@ static int nand_davinci_remove(struct platform_device *pdev)
                ecc4_busy = false;
        spin_unlock_irq(&davinci_nand_lock);
 
-       nand_release(nand_to_mtd(&info->chip));
+       nand_release(&info->chip);
 
        return 0;
 }
index b864b93dd289ed6eda8b2591006a6ab57922c1b7..830ea247277b1cac529e4814834eb20c05212e7f 100644 (file)
@@ -1,15 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * NAND Flash Controller Device Driver
  * Copyright © 2009-2010, Intel Corporation and its suppliers.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
+ * Copyright (c) 2017 Socionext Inc.
+ *   Reworked by Masahiro Yamada <yamada.masahiro@socionext.com>
  */
 
 #include <linux/bitfield.h>
@@ -25,9 +20,8 @@
 
 #include "denali.h"
 
-MODULE_LICENSE("GPL");
-
 #define DENALI_NAND_NAME    "denali-nand"
+#define DENALI_DEFAULT_OOB_SKIP_BYTES  8
 
 /* for Indexed Addressing */
 #define DENALI_INDEXED_CTRL    0x00
@@ -222,8 +216,9 @@ static uint32_t denali_check_irq(struct denali_nand_info *denali)
        return irq_status;
 }
 
-static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+static void denali_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct denali_nand_info *denali = mtd_to_denali(mtd);
        u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
        int i;
@@ -232,9 +227,10 @@ static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
                buf[i] = denali->host_read(denali, addr);
 }
 
-static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+static void denali_write_buf(struct nand_chip *chip, const uint8_t *buf,
+                            int len)
 {
-       struct denali_nand_info *denali = mtd_to_denali(mtd);
+       struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
        u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
        int i;
 
@@ -242,9 +238,9 @@ static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
                denali->host_write(denali, addr, buf[i]);
 }
 
-static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
+static void denali_read_buf16(struct nand_chip *chip, uint8_t *buf, int len)
 {
-       struct denali_nand_info *denali = mtd_to_denali(mtd);
+       struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
        u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
        uint16_t *buf16 = (uint16_t *)buf;
        int i;
@@ -253,10 +249,10 @@ static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
                buf16[i] = denali->host_read(denali, addr);
 }
 
-static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
+static void denali_write_buf16(struct nand_chip *chip, const uint8_t *buf,
                               int len)
 {
-       struct denali_nand_info *denali = mtd_to_denali(mtd);
+       struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
        u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
        const uint16_t *buf16 = (const uint16_t *)buf;
        int i;
@@ -265,32 +261,23 @@ static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
                denali->host_write(denali, addr, buf16[i]);
 }
 
-static uint8_t denali_read_byte(struct mtd_info *mtd)
+static uint8_t denali_read_byte(struct nand_chip *chip)
 {
        uint8_t byte;
 
-       denali_read_buf(mtd, &byte, 1);
+       denali_read_buf(chip, &byte, 1);
 
        return byte;
 }
 
-static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
-{
-       denali_write_buf(mtd, &byte, 1);
-}
-
-static uint16_t denali_read_word(struct mtd_info *mtd)
+static void denali_write_byte(struct nand_chip *chip, uint8_t byte)
 {
-       uint16_t word;
-
-       denali_read_buf16(mtd, (uint8_t *)&word, 2);
-
-       return word;
+       denali_write_buf(chip, &byte, 1);
 }
 
-static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
+static void denali_cmd_ctrl(struct nand_chip *chip, int dat, unsigned int ctrl)
 {
-       struct denali_nand_info *denali = mtd_to_denali(mtd);
+       struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
        uint32_t type;
 
        if (ctrl & NAND_CLE)
@@ -301,7 +288,8 @@ static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
                return;
 
        /*
-        * Some commands are followed by chip->dev_ready or chip->waitfunc.
+        * Some commands are followed by chip->legacy.dev_ready or
+        * chip->legacy.waitfunc.
         * irq_status must be cleared here to catch the R/B# interrupt later.
         */
        if (ctrl & NAND_CTRL_CHANGE)
@@ -310,9 +298,9 @@ static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
        denali->host_write(denali, DENALI_BANK(denali) | type, dat);
 }
 
-static int denali_dev_ready(struct mtd_info *mtd)
+static int denali_dev_ready(struct nand_chip *chip)
 {
-       struct denali_nand_info *denali = mtd_to_denali(mtd);
+       struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
 
        return !!(denali_check_irq(denali) & INTR__INT_ACT);
 }
@@ -698,9 +686,10 @@ static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
                                           false);
 }
 
-static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-                               uint8_t *buf, int oob_required, int page)
+static int denali_read_page_raw(struct nand_chip *chip, uint8_t *buf,
+                               int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct denali_nand_info *denali = mtd_to_denali(mtd);
        int writesize = mtd->writesize;
        int oobsize = mtd->oobsize;
@@ -773,17 +762,18 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
        return 0;
 }
 
-static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
-                          int page)
+static int denali_read_oob(struct nand_chip *chip, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
+
        denali_oob_xfer(mtd, chip, page, 0);
 
        return 0;
 }
 
-static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
-                           int page)
+static int denali_write_oob(struct nand_chip *chip, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct denali_nand_info *denali = mtd_to_denali(mtd);
 
        denali_reset_irq(denali);
@@ -793,9 +783,10 @@ static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
        return nand_prog_page_end_op(chip);
 }
 
-static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
-                           uint8_t *buf, int oob_required, int page)
+static int denali_read_page(struct nand_chip *chip, uint8_t *buf,
+                           int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct denali_nand_info *denali = mtd_to_denali(mtd);
        unsigned long uncor_ecc_flags = 0;
        int stat = 0;
@@ -814,7 +805,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
                return stat;
 
        if (uncor_ecc_flags) {
-               ret = denali_read_oob(mtd, chip, page);
+               ret = denali_read_oob(chip, page);
                if (ret)
                        return ret;
 
@@ -825,9 +816,10 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
        return stat;
 }
 
-static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-                                const uint8_t *buf, int oob_required, int page)
+static int denali_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
+                                int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct denali_nand_info *denali = mtd_to_denali(mtd);
        int writesize = mtd->writesize;
        int oobsize = mtd->oobsize;
@@ -903,25 +895,26 @@ static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
        return denali_data_xfer(denali, tmp_buf, size, page, 1, 1);
 }
 
-static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-                            const uint8_t *buf, int oob_required, int page)
+static int denali_write_page(struct nand_chip *chip, const uint8_t *buf,
+                            int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct denali_nand_info *denali = mtd_to_denali(mtd);
 
        return denali_data_xfer(denali, (void *)buf, mtd->writesize,
                                page, 0, 1);
 }
 
-static void denali_select_chip(struct mtd_info *mtd, int chip)
+static void denali_select_chip(struct nand_chip *chip, int cs)
 {
-       struct denali_nand_info *denali = mtd_to_denali(mtd);
+       struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
 
-       denali->active_bank = chip;
+       denali->active_bank = cs;
 }
 
-static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
+static int denali_waitfunc(struct nand_chip *chip)
 {
-       struct denali_nand_info *denali = mtd_to_denali(mtd);
+       struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
        uint32_t irq_status;
 
        /* R/B# pin transitioned from low to high? */
@@ -930,9 +923,9 @@ static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
        return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
 }
 
-static int denali_erase(struct mtd_info *mtd, int page)
+static int denali_erase(struct nand_chip *chip, int page)
 {
-       struct denali_nand_info *denali = mtd_to_denali(mtd);
+       struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
        uint32_t irq_status;
 
        denali_reset_irq(denali);
@@ -947,10 +940,10 @@ static int denali_erase(struct mtd_info *mtd, int page)
        return irq_status & INTR__ERASE_COMP ? 0 : -EIO;
 }
 
-static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
+static int denali_setup_data_interface(struct nand_chip *chip, int chipnr,
                                       const struct nand_data_interface *conf)
 {
-       struct denali_nand_info *denali = mtd_to_denali(mtd);
+       struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
        const struct nand_sdr_timings *timings;
        unsigned long t_x, mult_x;
        int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
@@ -1105,12 +1098,17 @@ static void denali_hw_init(struct denali_nand_info *denali)
                denali->revision = swab16(ioread32(denali->reg + REVISION));
 
        /*
-        * tell driver how many bit controller will skip before
-        * writing ECC code in OOB, this register may be already
-        * set by firmware. So we read this value out.
-        * if this value is 0, just let it be.
+        * Set how many bytes should be skipped before writing data in OOB.
+        * If a non-zero value has already been set (by firmware or something),
+        * just use it.  Otherwise, set the driver default.
         */
        denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES);
+       if (!denali->oob_skip_bytes) {
+               denali->oob_skip_bytes = DENALI_DEFAULT_OOB_SKIP_BYTES;
+               iowrite32(denali->oob_skip_bytes,
+                         denali->reg + SPARE_AREA_SKIP_BYTES);
+       }
+
        denali_detect_max_banks(denali);
        iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
        iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
@@ -1277,11 +1275,11 @@ static int denali_attach_chip(struct nand_chip *chip)
        mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
 
        if (chip->options & NAND_BUSWIDTH_16) {
-               chip->read_buf = denali_read_buf16;
-               chip->write_buf = denali_write_buf16;
+               chip->legacy.read_buf = denali_read_buf16;
+               chip->legacy.write_buf = denali_write_buf16;
        } else {
-               chip->read_buf = denali_read_buf;
-               chip->write_buf = denali_write_buf;
+               chip->legacy.read_buf = denali_read_buf;
+               chip->legacy.write_buf = denali_write_buf;
        }
        chip->ecc.read_page = denali_read_page;
        chip->ecc.read_page_raw = denali_read_page_raw;
@@ -1289,7 +1287,7 @@ static int denali_attach_chip(struct nand_chip *chip)
        chip->ecc.write_page_raw = denali_write_page_raw;
        chip->ecc.read_oob = denali_read_oob;
        chip->ecc.write_oob = denali_write_oob;
-       chip->erase = denali_erase;
+       chip->legacy.erase = denali_erase;
 
        ret = denali_multidev_fixup(denali);
        if (ret)
@@ -1358,12 +1356,11 @@ int denali_init(struct denali_nand_info *denali)
                mtd->name = "denali-nand";
 
        chip->select_chip = denali_select_chip;
-       chip->read_byte = denali_read_byte;
-       chip->write_byte = denali_write_byte;
-       chip->read_word = denali_read_word;
-       chip->cmd_ctrl = denali_cmd_ctrl;
-       chip->dev_ready = denali_dev_ready;
-       chip->waitfunc = denali_waitfunc;
+       chip->legacy.read_byte = denali_read_byte;
+       chip->legacy.write_byte = denali_write_byte;
+       chip->legacy.cmd_ctrl = denali_cmd_ctrl;
+       chip->legacy.dev_ready = denali_dev_ready;
+       chip->legacy.waitfunc = denali_waitfunc;
 
        if (features & FEATURES__INDEX_ADDR) {
                denali->host_read = denali_indexed_read;
@@ -1378,7 +1375,7 @@ int denali_init(struct denali_nand_info *denali)
                chip->setup_data_interface = denali_setup_data_interface;
 
        chip->dummy_controller.ops = &denali_controller_ops;
-       ret = nand_scan(mtd, denali->max_banks);
+       ret = nand_scan(chip, denali->max_banks);
        if (ret)
                goto disable_irq;
 
@@ -1401,9 +1398,11 @@ EXPORT_SYMBOL(denali_init);
 
 void denali_remove(struct denali_nand_info *denali)
 {
-       struct mtd_info *mtd = nand_to_mtd(&denali->nand);
-
-       nand_release(mtd);
+       nand_release(&denali->nand);
        denali_disable_irq(denali);
 }
 EXPORT_SYMBOL(denali_remove);
+
+MODULE_DESCRIPTION("Driver core for Denali NAND controller");
+MODULE_AUTHOR("Intel Corporation and its suppliers");
+MODULE_LICENSE("GPL v2");
index 1f8feaf924ebc66bc1d62f9fea43a6a915547a1e..57a5498f58bbb493dc8379c0341e45ea33e6a2ac 100644 (file)
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * NAND Flash Controller Device Driver
  * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
  */
 
 #ifndef __DENALI_H__
index 0faaad032e5fbfbcbd7fb7c2e8b92d2c67863a4f..7c6a8a426606afdf37ff59e63108c262437a4017 100644 (file)
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * NAND Flash Controller Device Driver for DT
  *
  * Copyright © 2011, Picochip.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
  */
 
 #include <linux/clk.h>
@@ -202,6 +194,6 @@ static struct platform_driver denali_dt_driver = {
 };
 module_platform_driver(denali_dt_driver);
 
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Jamie Iles");
 MODULE_DESCRIPTION("DT driver for Denali NAND controller");
index 7c8efc4c7bdfe1cd0bf5b07493b7e8da46efccee..48e9ac54ad531a884fe5d24519fbadfbb0ff2547 100644 (file)
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * NAND Flash Controller Device Driver
  * Copyright © 2009-2010, Intel Corporation and its suppliers.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
  */
 
 #include <linux/errno.h>
index 3c46188dd6d2ba68a9b78bdd140dcdf1070fa800..3a4c373affab3048866b40cda681c2a1335c3029 100644 (file)
@@ -83,9 +83,9 @@ static u_char empty_write_ecc[6] = { 0x4b, 0x00, 0xe2, 0x0e, 0x93, 0xf7 };
 #define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil)
 #define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k)
 
-static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd,
+static void doc200x_hwcontrol(struct nand_chip *this, int cmd,
                              unsigned int bitmask);
-static void doc200x_select_chip(struct mtd_info *mtd, int chip);
+static void doc200x_select_chip(struct nand_chip *this, int chip);
 
 static int debug = 0;
 module_param(debug, int, 0);
@@ -290,9 +290,8 @@ static inline int DoC_WaitReady(struct doc_priv *doc)
        return ret;
 }
 
-static void doc2000_write_byte(struct mtd_info *mtd, u_char datum)
+static void doc2000_write_byte(struct nand_chip *this, u_char datum)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
 
@@ -302,9 +301,8 @@ static void doc2000_write_byte(struct mtd_info *mtd, u_char datum)
        WriteDOC(datum, docptr, 2k_CDSN_IO);
 }
 
-static u_char doc2000_read_byte(struct mtd_info *mtd)
+static u_char doc2000_read_byte(struct nand_chip *this)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        u_char ret;
@@ -317,9 +315,9 @@ static u_char doc2000_read_byte(struct mtd_info *mtd)
        return ret;
 }
 
-static void doc2000_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
+static void doc2000_writebuf(struct nand_chip *this, const u_char *buf,
+                            int len)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        int i;
@@ -334,9 +332,8 @@ static void doc2000_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
                printk("\n");
 }
 
-static void doc2000_readbuf(struct mtd_info *mtd, u_char *buf, int len)
+static void doc2000_readbuf(struct nand_chip *this, u_char *buf, int len)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        int i;
@@ -344,14 +341,12 @@ static void doc2000_readbuf(struct mtd_info *mtd, u_char *buf, int len)
        if (debug)
                printk("readbuf of %d bytes: ", len);
 
-       for (i = 0; i < len; i++) {
+       for (i = 0; i < len; i++)
                buf[i] = ReadDOC(docptr, 2k_CDSN_IO + i);
-       }
 }
 
-static void doc2000_readbuf_dword(struct mtd_info *mtd, u_char *buf, int len)
+static void doc2000_readbuf_dword(struct nand_chip *this, u_char *buf, int len)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        int i;
@@ -376,19 +371,19 @@ static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr)
        struct doc_priv *doc = nand_get_controller_data(this);
        uint16_t ret;
 
-       doc200x_select_chip(mtd, nr);
-       doc200x_hwcontrol(mtd, NAND_CMD_READID,
+       doc200x_select_chip(this, nr);
+       doc200x_hwcontrol(this, NAND_CMD_READID,
                          NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-       doc200x_hwcontrol(mtd, 0, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
-       doc200x_hwcontrol(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+       doc200x_hwcontrol(this, 0, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+       doc200x_hwcontrol(this, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
        /* We can't use dev_ready here, but at least we wait for the
         * command to complete
         */
        udelay(50);
 
-       ret = this->read_byte(mtd) << 8;
-       ret |= this->read_byte(mtd);
+       ret = this->legacy.read_byte(this) << 8;
+       ret |= this->legacy.read_byte(this);
 
        if (doc->ChipID == DOC_ChipID_Doc2k && try_dword && !nr) {
                /* First chip probe. See if we get same results by 32-bit access */
@@ -398,10 +393,10 @@ static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr)
                } ident;
                void __iomem *docptr = doc->virtadr;
 
-               doc200x_hwcontrol(mtd, NAND_CMD_READID,
+               doc200x_hwcontrol(this, NAND_CMD_READID,
                                  NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-               doc200x_hwcontrol(mtd, 0, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
-               doc200x_hwcontrol(mtd, NAND_CMD_NONE,
+               doc200x_hwcontrol(this, 0, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+               doc200x_hwcontrol(this, NAND_CMD_NONE,
                                  NAND_NCE | NAND_CTRL_CHANGE);
 
                udelay(50);
@@ -409,7 +404,7 @@ static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr)
                ident.dword = readl(docptr + DoC_2k_CDSN_IO);
                if (((ident.byte[0] << 8) | ident.byte[1]) == ret) {
                        pr_info("DiskOnChip 2000 responds to DWORD access\n");
-                       this->read_buf = &doc2000_readbuf_dword;
+                       this->legacy.read_buf = &doc2000_readbuf_dword;
                }
        }
 
@@ -438,7 +433,7 @@ static void __init doc2000_count_chips(struct mtd_info *mtd)
        pr_debug("Detected %d chips per floor.\n", i);
 }
 
-static int doc200x_wait(struct mtd_info *mtd, struct nand_chip *this)
+static int doc200x_wait(struct nand_chip *this)
 {
        struct doc_priv *doc = nand_get_controller_data(this);
 
@@ -447,14 +442,13 @@ static int doc200x_wait(struct mtd_info *mtd, struct nand_chip *this)
        DoC_WaitReady(doc);
        nand_status_op(this, NULL);
        DoC_WaitReady(doc);
-       status = (int)this->read_byte(mtd);
+       status = (int)this->legacy.read_byte(this);
 
        return status;
 }
 
-static void doc2001_write_byte(struct mtd_info *mtd, u_char datum)
+static void doc2001_write_byte(struct nand_chip *this, u_char datum)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
 
@@ -463,9 +457,8 @@ static void doc2001_write_byte(struct mtd_info *mtd, u_char datum)
        WriteDOC(datum, docptr, WritePipeTerm);
 }
 
-static u_char doc2001_read_byte(struct mtd_info *mtd)
+static u_char doc2001_read_byte(struct nand_chip *this)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
 
@@ -477,9 +470,8 @@ static u_char doc2001_read_byte(struct mtd_info *mtd)
        return ReadDOC(docptr, LastDataRead);
 }
 
-static void doc2001_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
+static void doc2001_writebuf(struct nand_chip *this, const u_char *buf, int len)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        int i;
@@ -490,9 +482,8 @@ static void doc2001_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
        WriteDOC(0x00, docptr, WritePipeTerm);
 }
 
-static void doc2001_readbuf(struct mtd_info *mtd, u_char *buf, int len)
+static void doc2001_readbuf(struct nand_chip *this, u_char *buf, int len)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        int i;
@@ -507,9 +498,8 @@ static void doc2001_readbuf(struct mtd_info *mtd, u_char *buf, int len)
        buf[i] = ReadDOC(docptr, LastDataRead);
 }
 
-static u_char doc2001plus_read_byte(struct mtd_info *mtd)
+static u_char doc2001plus_read_byte(struct nand_chip *this)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        u_char ret;
@@ -522,9 +512,8 @@ static u_char doc2001plus_read_byte(struct mtd_info *mtd)
        return ret;
 }
 
-static void doc2001plus_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
+static void doc2001plus_writebuf(struct nand_chip *this, const u_char *buf, int len)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        int i;
@@ -540,9 +529,8 @@ static void doc2001plus_writebuf(struct mtd_info *mtd, const u_char *buf, int le
                printk("\n");
 }
 
-static void doc2001plus_readbuf(struct mtd_info *mtd, u_char *buf, int len)
+static void doc2001plus_readbuf(struct nand_chip *this, u_char *buf, int len)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        int i;
@@ -571,9 +559,8 @@ static void doc2001plus_readbuf(struct mtd_info *mtd, u_char *buf, int len)
                printk("\n");
 }
 
-static void doc2001plus_select_chip(struct mtd_info *mtd, int chip)
+static void doc2001plus_select_chip(struct nand_chip *this, int chip)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        int floor = 0;
@@ -598,9 +585,8 @@ static void doc2001plus_select_chip(struct mtd_info *mtd, int chip)
        doc->curfloor = floor;
 }
 
-static void doc200x_select_chip(struct mtd_info *mtd, int chip)
+static void doc200x_select_chip(struct nand_chip *this, int chip)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        int floor = 0;
@@ -615,12 +601,12 @@ static void doc200x_select_chip(struct mtd_info *mtd, int chip)
        chip -= (floor * doc->chips_per_floor);
 
        /* 11.4.4 -- deassert CE before changing chip */
-       doc200x_hwcontrol(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
+       doc200x_hwcontrol(this, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 
        WriteDOC(floor, docptr, FloorSelect);
        WriteDOC(chip, docptr, CDSNDeviceSelect);
 
-       doc200x_hwcontrol(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+       doc200x_hwcontrol(this, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
        doc->curchip = chip;
        doc->curfloor = floor;
@@ -628,10 +614,9 @@ static void doc200x_select_chip(struct mtd_info *mtd, int chip)
 
 #define CDSN_CTRL_MSK (CDSN_CTRL_CE | CDSN_CTRL_CLE | CDSN_CTRL_ALE)
 
-static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd,
+static void doc200x_hwcontrol(struct nand_chip *this, int cmd,
                              unsigned int ctrl)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
 
@@ -646,15 +631,16 @@ static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd,
        }
        if (cmd != NAND_CMD_NONE) {
                if (DoC_is_2000(doc))
-                       doc2000_write_byte(mtd, cmd);
+                       doc2000_write_byte(this, cmd);
                else
-                       doc2001_write_byte(mtd, cmd);
+                       doc2001_write_byte(this, cmd);
        }
 }
 
-static void doc2001plus_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
+static void doc2001plus_command(struct nand_chip *this, unsigned command,
+                               int column, int page_addr)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(this);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
 
@@ -729,13 +715,13 @@ static void doc2001plus_command(struct mtd_info *mtd, unsigned command, int colu
                return;
 
        case NAND_CMD_RESET:
-               if (this->dev_ready)
+               if (this->legacy.dev_ready)
                        break;
-               udelay(this->chip_delay);
+               udelay(this->legacy.chip_delay);
                WriteDOC(NAND_CMD_STATUS, docptr, Mplus_FlashCmd);
                WriteDOC(0, docptr, Mplus_WritePipeTerm);
                WriteDOC(0, docptr, Mplus_WritePipeTerm);
-               while (!(this->read_byte(mtd) & 0x40)) ;
+               while (!(this->legacy.read_byte(this) & 0x40)) ;
                return;
 
                /* This applies to read commands */
@@ -744,8 +730,8 @@ static void doc2001plus_command(struct mtd_info *mtd, unsigned command, int colu
                 * If we don't have access to the busy pin, we apply the given
                 * command delay
                 */
-               if (!this->dev_ready) {
-                       udelay(this->chip_delay);
+               if (!this->legacy.dev_ready) {
+                       udelay(this->legacy.chip_delay);
                        return;
                }
        }
@@ -754,12 +740,11 @@ static void doc2001plus_command(struct mtd_info *mtd, unsigned command, int colu
         * any case on any machine. */
        ndelay(100);
        /* wait until command is processed */
-       while (!this->dev_ready(mtd)) ;
+       while (!this->legacy.dev_ready(this)) ;
 }
 
-static int doc200x_dev_ready(struct mtd_info *mtd)
+static int doc200x_dev_ready(struct nand_chip *this)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
 
@@ -790,16 +775,15 @@ static int doc200x_dev_ready(struct mtd_info *mtd)
        }
 }
 
-static int doc200x_block_bad(struct mtd_info *mtd, loff_t ofs)
+static int doc200x_block_bad(struct nand_chip *this, loff_t ofs)
 {
        /* This is our last resort if we couldn't find or create a BBT.  Just
           pretend all blocks are good. */
        return 0;
 }
 
-static void doc200x_enable_hwecc(struct mtd_info *mtd, int mode)
+static void doc200x_enable_hwecc(struct nand_chip *this, int mode)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
 
@@ -816,9 +800,8 @@ static void doc200x_enable_hwecc(struct mtd_info *mtd, int mode)
        }
 }
 
-static void doc2001plus_enable_hwecc(struct mtd_info *mtd, int mode)
+static void doc2001plus_enable_hwecc(struct nand_chip *this, int mode)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
 
@@ -836,9 +819,9 @@ static void doc2001plus_enable_hwecc(struct mtd_info *mtd, int mode)
 }
 
 /* This code is only called on write */
-static int doc200x_calculate_ecc(struct mtd_info *mtd, const u_char *dat, unsigned char *ecc_code)
+static int doc200x_calculate_ecc(struct nand_chip *this, const u_char *dat,
+                                unsigned char *ecc_code)
 {
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        int i;
@@ -895,11 +878,10 @@ static int doc200x_calculate_ecc(struct mtd_info *mtd, const u_char *dat, unsign
        return 0;
 }
 
-static int doc200x_correct_data(struct mtd_info *mtd, u_char *dat,
+static int doc200x_correct_data(struct nand_chip *this, u_char *dat,
                                u_char *read_ecc, u_char *isnull)
 {
        int i, ret = 0;
-       struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
        void __iomem *docptr = doc->virtadr;
        uint8_t calc_ecc[6];
@@ -1357,9 +1339,9 @@ static inline int __init doc2000_init(struct mtd_info *mtd)
        struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
 
-       this->read_byte = doc2000_read_byte;
-       this->write_buf = doc2000_writebuf;
-       this->read_buf = doc2000_readbuf;
+       this->legacy.read_byte = doc2000_read_byte;
+       this->legacy.write_buf = doc2000_writebuf;
+       this->legacy.read_buf = doc2000_readbuf;
        doc->late_init = nftl_scan_bbt;
 
        doc->CDSNControl = CDSN_CTRL_FLASH_IO | CDSN_CTRL_ECC_IO;
@@ -1373,9 +1355,9 @@ static inline int __init doc2001_init(struct mtd_info *mtd)
        struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
 
-       this->read_byte = doc2001_read_byte;
-       this->write_buf = doc2001_writebuf;
-       this->read_buf = doc2001_readbuf;
+       this->legacy.read_byte = doc2001_read_byte;
+       this->legacy.write_buf = doc2001_writebuf;
+       this->legacy.read_buf = doc2001_readbuf;
 
        ReadDOC(doc->virtadr, ChipID);
        ReadDOC(doc->virtadr, ChipID);
@@ -1403,13 +1385,13 @@ static inline int __init doc2001plus_init(struct mtd_info *mtd)
        struct nand_chip *this = mtd_to_nand(mtd);
        struct doc_priv *doc = nand_get_controller_data(this);
 
-       this->read_byte = doc2001plus_read_byte;
-       this->write_buf = doc2001plus_writebuf;
-       this->read_buf = doc2001plus_readbuf;
+       this->legacy.read_byte = doc2001plus_read_byte;
+       this->legacy.write_buf = doc2001plus_writebuf;
+       this->legacy.read_buf = doc2001plus_readbuf;
        doc->late_init = inftl_scan_bbt;
-       this->cmd_ctrl = NULL;
+       this->legacy.cmd_ctrl = NULL;
        this->select_chip = doc2001plus_select_chip;
-       this->cmdfunc = doc2001plus_command;
+       this->legacy.cmdfunc = doc2001plus_command;
        this->ecc.hwctl = doc2001plus_enable_hwecc;
 
        doc->chips_per_floor = 1;
@@ -1587,10 +1569,10 @@ static int __init doc_probe(unsigned long physadr)
 
        nand_set_controller_data(nand, doc);
        nand->select_chip       = doc200x_select_chip;
-       nand->cmd_ctrl          = doc200x_hwcontrol;
-       nand->dev_ready         = doc200x_dev_ready;
-       nand->waitfunc          = doc200x_wait;
-       nand->block_bad         = doc200x_block_bad;
+       nand->legacy.cmd_ctrl           = doc200x_hwcontrol;
+       nand->legacy.dev_ready  = doc200x_dev_ready;
+       nand->legacy.waitfunc   = doc200x_wait;
+       nand->legacy.block_bad  = doc200x_block_bad;
        nand->ecc.hwctl         = doc200x_enable_hwecc;
        nand->ecc.calculate     = doc200x_calculate_ecc;
        nand->ecc.correct       = doc200x_correct_data;
@@ -1620,14 +1602,14 @@ static int __init doc_probe(unsigned long physadr)
        else
                numchips = doc2001_init(mtd);
 
-       if ((ret = nand_scan(mtd, numchips)) || (ret = doc->late_init(mtd))) {
+       if ((ret = nand_scan(nand, numchips)) || (ret = doc->late_init(mtd))) {
                /* DBB note: i believe nand_release is necessary here, as
                   buffers may have been allocated in nand_base.  Check with
                   Thomas. FIX ME! */
                /* nand_release will call mtd_device_unregister, but we
                   haven't yet added it.  This is handled without incident by
                   mtd_device_unregister, as far as I can tell. */
-               nand_release(mtd);
+               nand_release(nand);
                goto fail;
        }
 
@@ -1662,7 +1644,7 @@ static void release_nanddoc(void)
                doc = nand_get_controller_data(nand);
 
                nextmtd = doc->nextdoc;
-               nand_release(mtd);
+               nand_release(nand);
                iounmap(doc->virtadr);
                release_mem_region(doc->physadr, DOC_IOREMAP_LEN);
                free_rs(doc->rs_decoder);
diff --git a/drivers/mtd/nand/raw/docg4.c b/drivers/mtd/nand/raw/docg4.c
deleted file mode 100644 (file)
index 427fcbc..0000000
+++ /dev/null
@@ -1,1442 +0,0 @@
-/*
- *  Copyright © 2012 Mike Dunn <mikedunn@newsguy.com>
- *
- * mtd nand driver for M-Systems DiskOnChip G4
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * Tested on the Palm Treo 680.  The G4 is also present on Toshiba Portege, Asus
- * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others.
- * Should work on these as well.  Let me know!
- *
- * TODO:
- *
- *  Mechanism for management of password-protected areas
- *
- *  Hamming ecc when reading oob only
- *
- *  According to the M-Sys documentation, this device is also available in a
- *  "dual-die" configuration having a 256MB capacity, but no mechanism for
- *  detecting this variant is documented.  Currently this driver assumes 128MB
- *  capacity.
- *
- *  Support for multiple cascaded devices ("floors").  Not sure which gadgets
- *  contain multiple G4s in a cascaded configuration, if any.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/bitops.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/bch.h>
-#include <linux/bitrev.h>
-#include <linux/jiffies.h>
-
-/*
- * In "reliable mode" consecutive 2k pages are used in parallel (in some
- * fashion) to store the same data.  The data can be read back from the
- * even-numbered pages in the normal manner; odd-numbered pages will appear to
- * contain junk.  Systems that boot from the docg4 typically write the secondary
- * program loader (SPL) code in this mode.  The SPL is loaded by the initial
- * program loader (IPL, stored in the docg4's 2k NOR-like region that is mapped
- * to the reset vector address).  This module parameter enables you to use this
- * driver to write the SPL.  When in this mode, no more than 2k of data can be
- * written at a time, because the addresses do not increment in the normal
- * manner, and the starting offset must be within an even-numbered 2k region;
- * i.e., invalid starting offsets are 0x800, 0xa00, 0xc00, 0xe00, 0x1800,
- * 0x1a00, ...  Reliable mode is a special case and should not be used unless
- * you know what you're doing.
- */
-static bool reliable_mode;
-module_param(reliable_mode, bool, 0);
-MODULE_PARM_DESC(reliable_mode, "pages are programmed in reliable mode");
-
-/*
- * You'll want to ignore badblocks if you're reading a partition that contains
- * data written by the TrueFFS library (i.e., by PalmOS, Windows, etc), since
- * it does not use mtd nand's method for marking bad blocks (using oob area).
- * This will also skip the check of the "page written" flag.
- */
-static bool ignore_badblocks;
-module_param(ignore_badblocks, bool, 0);
-MODULE_PARM_DESC(ignore_badblocks, "no badblock checking performed");
-
-struct docg4_priv {
-       struct mtd_info *mtd;
-       struct device *dev;
-       void __iomem *virtadr;
-       int status;
-       struct {
-               unsigned int command;
-               int column;
-               int page;
-       } last_command;
-       uint8_t oob_buf[16];
-       uint8_t ecc_buf[7];
-       int oob_page;
-       struct bch_control *bch;
-};
-
-/*
- * Defines prefixed with DOCG4 are unique to the diskonchip G4.  All others are
- * shared with other diskonchip devices (P3, G3 at least).
- *
- * Functions with names prefixed with docg4_ are mtd / nand interface functions
- * (though they may also be called internally).  All others are internal.
- */
-
-#define DOC_IOSPACE_DATA               0x0800
-
-/* register offsets */
-#define DOC_CHIPID                     0x1000
-#define DOC_DEVICESELECT               0x100a
-#define DOC_ASICMODE                   0x100c
-#define DOC_DATAEND                    0x101e
-#define DOC_NOP                                0x103e
-
-#define DOC_FLASHSEQUENCE              0x1032
-#define DOC_FLASHCOMMAND               0x1034
-#define DOC_FLASHADDRESS               0x1036
-#define DOC_FLASHCONTROL               0x1038
-#define DOC_ECCCONF0                   0x1040
-#define DOC_ECCCONF1                   0x1042
-#define DOC_HAMMINGPARITY              0x1046
-#define DOC_BCH_SYNDROM(idx)           (0x1048 + idx)
-
-#define DOC_ASICMODECONFIRM            0x1072
-#define DOC_CHIPID_INV                 0x1074
-#define DOC_POWERMODE                  0x107c
-
-#define DOCG4_MYSTERY_REG              0x1050
-
-/* apparently used only to write oob bytes 6 and 7 */
-#define DOCG4_OOB_6_7                  0x1052
-
-/* DOC_FLASHSEQUENCE register commands */
-#define DOC_SEQ_RESET                  0x00
-#define DOCG4_SEQ_PAGE_READ            0x03
-#define DOCG4_SEQ_FLUSH                        0x29
-#define DOCG4_SEQ_PAGEWRITE            0x16
-#define DOCG4_SEQ_PAGEPROG             0x1e
-#define DOCG4_SEQ_BLOCKERASE           0x24
-#define DOCG4_SEQ_SETMODE              0x45
-
-/* DOC_FLASHCOMMAND register commands */
-#define DOCG4_CMD_PAGE_READ             0x00
-#define DOC_CMD_ERASECYCLE2            0xd0
-#define DOCG4_CMD_FLUSH                 0x70
-#define DOCG4_CMD_READ2                 0x30
-#define DOC_CMD_PROG_BLOCK_ADDR                0x60
-#define DOCG4_CMD_PAGEWRITE            0x80
-#define DOC_CMD_PROG_CYCLE2            0x10
-#define DOCG4_CMD_FAST_MODE            0xa3 /* functionality guessed */
-#define DOC_CMD_RELIABLE_MODE          0x22
-#define DOC_CMD_RESET                  0xff
-
-/* DOC_POWERMODE register bits */
-#define DOC_POWERDOWN_READY            0x80
-
-/* DOC_FLASHCONTROL register bits */
-#define DOC_CTRL_CE                    0x10
-#define DOC_CTRL_UNKNOWN               0x40
-#define DOC_CTRL_FLASHREADY            0x01
-
-/* DOC_ECCCONF0 register bits */
-#define DOC_ECCCONF0_READ_MODE         0x8000
-#define DOC_ECCCONF0_UNKNOWN           0x2000
-#define DOC_ECCCONF0_ECC_ENABLE                0x1000
-#define DOC_ECCCONF0_DATA_BYTES_MASK   0x07ff
-
-/* DOC_ECCCONF1 register bits */
-#define DOC_ECCCONF1_BCH_SYNDROM_ERR   0x80
-#define DOC_ECCCONF1_ECC_ENABLE         0x07
-#define DOC_ECCCONF1_PAGE_IS_WRITTEN   0x20
-
-/* DOC_ASICMODE register bits */
-#define DOC_ASICMODE_RESET             0x00
-#define DOC_ASICMODE_NORMAL            0x01
-#define DOC_ASICMODE_POWERDOWN         0x02
-#define DOC_ASICMODE_MDWREN            0x04
-#define DOC_ASICMODE_BDETCT_RESET      0x08
-#define DOC_ASICMODE_RSTIN_RESET       0x10
-#define DOC_ASICMODE_RAM_WE            0x20
-
-/* good status values read after read/write/erase operations */
-#define DOCG4_PROGSTATUS_GOOD          0x51
-#define DOCG4_PROGSTATUS_GOOD_2        0xe0
-
-/*
- * On read operations (page and oob-only), the first byte read from I/O reg is a
- * status.  On error, it reads 0x73; otherwise, it reads either 0x71 (first read
- * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
- */
-#define DOCG4_READ_ERROR           0x02 /* bit 1 indicates read error */
-
-/* anatomy of the device */
-#define DOCG4_CHIP_SIZE        0x8000000
-#define DOCG4_PAGE_SIZE        0x200
-#define DOCG4_PAGES_PER_BLOCK  0x200
-#define DOCG4_BLOCK_SIZE       (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
-#define DOCG4_NUMBLOCKS        (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
-#define DOCG4_OOB_SIZE         0x10
-#define DOCG4_CHIP_SHIFT       27    /* log_2(DOCG4_CHIP_SIZE) */
-#define DOCG4_PAGE_SHIFT       9     /* log_2(DOCG4_PAGE_SIZE) */
-#define DOCG4_ERASE_SHIFT      18    /* log_2(DOCG4_BLOCK_SIZE) */
-
-/* all but the last byte is included in ecc calculation */
-#define DOCG4_BCH_SIZE         (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
-
-#define DOCG4_USERDATA_LEN     520 /* 512 byte page plus 8 oob avail to user */
-
-/* expected values from the ID registers */
-#define DOCG4_IDREG1_VALUE     0x0400
-#define DOCG4_IDREG2_VALUE     0xfbff
-
-/* primitive polynomial used to build the Galois field used by hw ecc gen */
-#define DOCG4_PRIMITIVE_POLY   0x4443
-
-#define DOCG4_M                14  /* Galois field is of order 2^14 */
-#define DOCG4_T                4   /* BCH alg corrects up to 4 bit errors */
-
-#define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
-#define DOCG4_REDUNDANT_BBT_PAGE 24 /* page where redundant factory bbt lives */
-
-/*
- * Bytes 0, 1 are used as badblock marker.
- * Bytes 2 - 6 are available to the user.
- * Byte 7 is hamming ecc for first 7 oob bytes only.
- * Bytes 8 - 14 are hw-generated ecc covering entire page + oob bytes 0 - 14.
- * Byte 15 (the last) is used by the driver as a "page written" flag.
- */
-static int docg4_ooblayout_ecc(struct mtd_info *mtd, int section,
-                              struct mtd_oob_region *oobregion)
-{
-       if (section)
-               return -ERANGE;
-
-       oobregion->offset = 7;
-       oobregion->length = 9;
-
-       return 0;
-}
-
-static int docg4_ooblayout_free(struct mtd_info *mtd, int section,
-                               struct mtd_oob_region *oobregion)
-{
-       if (section)
-               return -ERANGE;
-
-       oobregion->offset = 2;
-       oobregion->length = 5;
-
-       return 0;
-}
-
-static const struct mtd_ooblayout_ops docg4_ooblayout_ops = {
-       .ecc = docg4_ooblayout_ecc,
-       .free = docg4_ooblayout_free,
-};
-
-/*
- * The device has a nop register which M-Sys claims is for the purpose of
- * inserting precise delays.  But beware; at least some operations fail if the
- * nop writes are replaced with a generic delay!
- */
-static inline void write_nop(void __iomem *docptr)
-{
-       writew(0, docptr + DOC_NOP);
-}
-
-static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
-       int i;
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       uint16_t *p = (uint16_t *) buf;
-       len >>= 1;
-
-       for (i = 0; i < len; i++)
-               p[i] = readw(nand->IO_ADDR_R);
-}
-
-static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
-       int i;
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       uint16_t *p = (uint16_t *) buf;
-       len >>= 1;
-
-       for (i = 0; i < len; i++)
-               writew(p[i], nand->IO_ADDR_W);
-}
-
-static int poll_status(struct docg4_priv *doc)
-{
-       /*
-        * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
-        * register.  Operations known to take a long time (e.g., block erase)
-        * should sleep for a while before calling this.
-        */
-
-       uint16_t flash_status;
-       unsigned long timeo;
-       void __iomem *docptr = doc->virtadr;
-
-       dev_dbg(doc->dev, "%s...\n", __func__);
-
-       /* hardware quirk requires reading twice initially */
-       flash_status = readw(docptr + DOC_FLASHCONTROL);
-
-       timeo = jiffies + msecs_to_jiffies(200); /* generous timeout */
-       do {
-               cpu_relax();
-               flash_status = readb(docptr + DOC_FLASHCONTROL);
-       } while (!(flash_status & DOC_CTRL_FLASHREADY) &&
-                time_before(jiffies, timeo));
-
-       if (unlikely(!(flash_status & DOC_CTRL_FLASHREADY))) {
-               dev_err(doc->dev, "%s: timed out!\n", __func__);
-               return NAND_STATUS_FAIL;
-       }
-
-       return 0;
-}
-
-
-static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand)
-{
-
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       int status = NAND_STATUS_WP;       /* inverse logic?? */
-       dev_dbg(doc->dev, "%s...\n", __func__);
-
-       /* report any previously unreported error */
-       if (doc->status) {
-               status |= doc->status;
-               doc->status = 0;
-               return status;
-       }
-
-       status |= poll_status(doc);
-       return status;
-}
-
-static void docg4_select_chip(struct mtd_info *mtd, int chip)
-{
-       /*
-        * Select among multiple cascaded chips ("floors").  Multiple floors are
-        * not yet supported, so the only valid non-negative value is 0.
-        */
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-
-       dev_dbg(doc->dev, "%s: chip %d\n", __func__, chip);
-
-       if (chip < 0)
-               return;         /* deselected */
-
-       if (chip > 0)
-               dev_warn(doc->dev, "multiple floors currently unsupported\n");
-
-       writew(0, docptr + DOC_DEVICESELECT);
-}
-
-static void reset(struct mtd_info *mtd)
-{
-       /* full device reset */
-
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-
-       writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN,
-              docptr + DOC_ASICMODE);
-       writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN),
-              docptr + DOC_ASICMODECONFIRM);
-       write_nop(docptr);
-
-       writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN,
-              docptr + DOC_ASICMODE);
-       writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN),
-              docptr + DOC_ASICMODECONFIRM);
-
-       writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1);
-
-       poll_status(doc);
-}
-
-static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf)
-{
-       /* read the 7 hw-generated ecc bytes */
-
-       int i;
-       for (i = 0; i < 7; i++) { /* hw quirk; read twice */
-               ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
-               ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
-       }
-}
-
-static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page)
-{
-       /*
-        * Called after a page read when hardware reports bitflips.
-        * Up to four bitflips can be corrected.
-        */
-
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-       int i, numerrs, errpos[4];
-       const uint8_t blank_read_hwecc[8] = {
-               0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 };
-
-       read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */
-
-       /* check if read error is due to a blank page */
-       if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7))
-               return 0;       /* yes */
-
-       /* skip additional check of "written flag" if ignore_badblocks */
-       if (ignore_badblocks == false) {
-
-               /*
-                * If the hw ecc bytes are not those of a blank page, there's
-                * still a chance that the page is blank, but was read with
-                * errors.  Check the "written flag" in last oob byte, which
-                * is set to zero when a page is written.  If more than half
-                * the bits are set, assume a blank page.  Unfortunately, the
-                * bit flips(s) are not reported in stats.
-                */
-
-               if (nand->oob_poi[15]) {
-                       int bit, numsetbits = 0;
-                       unsigned long written_flag = nand->oob_poi[15];
-                       for_each_set_bit(bit, &written_flag, 8)
-                               numsetbits++;
-                       if (numsetbits > 4) { /* assume blank */
-                               dev_warn(doc->dev,
-                                        "error(s) in blank page "
-                                        "at offset %08x\n",
-                                        page * DOCG4_PAGE_SIZE);
-                               return 0;
-                       }
-               }
-       }
-
-       /*
-        * The hardware ecc unit produces oob_ecc ^ calc_ecc.  The kernel's bch
-        * algorithm is used to decode this.  However the hw operates on page
-        * data in a bit order that is the reverse of that of the bch alg,
-        * requiring that the bits be reversed on the result.  Thanks to Ivan
-        * Djelic for his analysis!
-        */
-       for (i = 0; i < 7; i++)
-               doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]);
-
-       numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL,
-                            doc->ecc_buf, NULL, errpos);
-
-       if (numerrs == -EBADMSG) {
-               dev_warn(doc->dev, "uncorrectable errors at offset %08x\n",
-                        page * DOCG4_PAGE_SIZE);
-               return -EBADMSG;
-       }
-
-       BUG_ON(numerrs < 0);    /* -EINVAL, or anything other than -EBADMSG */
-
-       /* undo last step in BCH alg (modulo mirroring not needed) */
-       for (i = 0; i < numerrs; i++)
-               errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7));
-
-       /* fix the errors */
-       for (i = 0; i < numerrs; i++) {
-
-               /* ignore if error within oob ecc bytes */
-               if (errpos[i] > DOCG4_USERDATA_LEN * 8)
-                       continue;
-
-               /* if error within oob area preceeding ecc bytes... */
-               if (errpos[i] > DOCG4_PAGE_SIZE * 8)
-                       change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8,
-                                  (unsigned long *)nand->oob_poi);
-
-               else    /* error in page data */
-                       change_bit(errpos[i], (unsigned long *)buf);
-       }
-
-       dev_notice(doc->dev, "%d error(s) corrected at offset %08x\n",
-                  numerrs, page * DOCG4_PAGE_SIZE);
-
-       return numerrs;
-}
-
-static uint8_t docg4_read_byte(struct mtd_info *mtd)
-{
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-
-       dev_dbg(doc->dev, "%s\n", __func__);
-
-       if (doc->last_command.command == NAND_CMD_STATUS) {
-               int status;
-
-               /*
-                * Previous nand command was status request, so nand
-                * infrastructure code expects to read the status here.  If an
-                * error occurred in a previous operation, report it.
-                */
-               doc->last_command.command = 0;
-
-               if (doc->status) {
-                       status = doc->status;
-                       doc->status = 0;
-               }
-
-               /* why is NAND_STATUS_WP inverse logic?? */
-               else
-                       status = NAND_STATUS_WP | NAND_STATUS_READY;
-
-               return status;
-       }
-
-       dev_warn(doc->dev, "unexpected call to read_byte()\n");
-
-       return 0;
-}
-
-static void write_addr(struct docg4_priv *doc, uint32_t docg4_addr)
-{
-       /* write the four address bytes packed in docg4_addr to the device */
-
-       void __iomem *docptr = doc->virtadr;
-       writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-       docg4_addr >>= 8;
-       writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-       docg4_addr >>= 8;
-       writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-       docg4_addr >>= 8;
-       writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-}
-
-static int read_progstatus(struct docg4_priv *doc)
-{
-       /*
-        * This apparently checks the status of programming.  Done after an
-        * erasure, and after page data is written.  On error, the status is
-        * saved, to be later retrieved by the nand infrastructure code.
-        */
-       void __iomem *docptr = doc->virtadr;
-
-       /* status is read from the I/O reg */
-       uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA);
-       uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA);
-       uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG);
-
-       dev_dbg(doc->dev, "docg4: %s: %02x %02x %02x\n",
-             __func__, status1, status2, status3);
-
-       if (status1 != DOCG4_PROGSTATUS_GOOD
-           || status2 != DOCG4_PROGSTATUS_GOOD_2
-           || status3 != DOCG4_PROGSTATUS_GOOD_2) {
-               doc->status = NAND_STATUS_FAIL;
-               dev_warn(doc->dev, "read_progstatus failed: "
-                        "%02x, %02x, %02x\n", status1, status2, status3);
-               return -EIO;
-       }
-       return 0;
-}
-
-static int pageprog(struct mtd_info *mtd)
-{
-       /*
-        * Final step in writing a page.  Writes the contents of its
-        * internal buffer out to the flash array, or some such.
-        */
-
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-       int retval = 0;
-
-       dev_dbg(doc->dev, "docg4: %s\n", __func__);
-
-       writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE);
-       writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND);
-       write_nop(docptr);
-       write_nop(docptr);
-
-       /* Just busy-wait; usleep_range() slows things down noticeably. */
-       poll_status(doc);
-
-       writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
-       writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
-       writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-
-       retval = read_progstatus(doc);
-       writew(0, docptr + DOC_DATAEND);
-       write_nop(docptr);
-       poll_status(doc);
-       write_nop(docptr);
-
-       return retval;
-}
-
-static void sequence_reset(struct mtd_info *mtd)
-{
-       /* common starting sequence for all operations */
-
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-
-       writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL);
-       writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
-       writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
-       write_nop(docptr);
-       write_nop(docptr);
-       poll_status(doc);
-       write_nop(docptr);
-}
-
-static void read_page_prologue(struct mtd_info *mtd, uint32_t docg4_addr)
-{
-       /* first step in reading a page */
-
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-
-       dev_dbg(doc->dev,
-             "docg4: %s: g4 page %08x\n", __func__, docg4_addr);
-
-       sequence_reset(mtd);
-
-       writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
-       writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
-       write_nop(docptr);
-
-       write_addr(doc, docg4_addr);
-
-       write_nop(docptr);
-       writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
-       write_nop(docptr);
-       write_nop(docptr);
-
-       poll_status(doc);
-}
-
-static void write_page_prologue(struct mtd_info *mtd, uint32_t docg4_addr)
-{
-       /* first step in writing a page */
-
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-
-       dev_dbg(doc->dev,
-             "docg4: %s: g4 addr: %x\n", __func__, docg4_addr);
-       sequence_reset(mtd);
-
-       if (unlikely(reliable_mode)) {
-               writew(DOCG4_SEQ_SETMODE, docptr + DOC_FLASHSEQUENCE);
-               writew(DOCG4_CMD_FAST_MODE, docptr + DOC_FLASHCOMMAND);
-               writew(DOC_CMD_RELIABLE_MODE, docptr + DOC_FLASHCOMMAND);
-               write_nop(docptr);
-       }
-
-       writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE);
-       writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND);
-       write_nop(docptr);
-       write_addr(doc, docg4_addr);
-       write_nop(docptr);
-       write_nop(docptr);
-       poll_status(doc);
-}
-
-static uint32_t mtd_to_docg4_address(int page, int column)
-{
-       /*
-        * Convert mtd address to format used by the device, 32 bit packed.
-        *
-        * Some notes on G4 addressing... The M-Sys documentation on this device
-        * claims that pages are 2K in length, and indeed, the format of the
-        * address used by the device reflects that.  But within each page are
-        * four 512 byte "sub-pages", each with its own oob data that is
-        * read/written immediately after the 512 bytes of page data.  This oob
-        * data contains the ecc bytes for the preceeding 512 bytes.
-        *
-        * Rather than tell the mtd nand infrastructure that page size is 2k,
-        * with four sub-pages each, we engage in a little subterfuge and tell
-        * the infrastructure code that pages are 512 bytes in size.  This is
-        * done because during the course of reverse-engineering the device, I
-        * never observed an instance where an entire 2K "page" was read or
-        * written as a unit.  Each "sub-page" is always addressed individually,
-        * its data read/written, and ecc handled before the next "sub-page" is
-        * addressed.
-        *
-        * This requires us to convert addresses passed by the mtd nand
-        * infrastructure code to those used by the device.
-        *
-        * The address that is written to the device consists of four bytes: the
-        * first two are the 2k page number, and the second is the index into
-        * the page.  The index is in terms of 16-bit half-words and includes
-        * the preceeding oob data, so e.g., the index into the second
-        * "sub-page" is 0x108, and the full device address of the start of mtd
-        * page 0x201 is 0x00800108.
-        */
-       int g4_page = page / 4;                       /* device's 2K page */
-       int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */
-       return (g4_page << 16) | g4_index;            /* pack */
-}
-
-static void docg4_command(struct mtd_info *mtd, unsigned command, int column,
-                         int page_addr)
-{
-       /* handle standard nand commands */
-
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       uint32_t g4_addr = mtd_to_docg4_address(page_addr, column);
-
-       dev_dbg(doc->dev, "%s %x, page_addr=%x, column=%x\n",
-             __func__, command, page_addr, column);
-
-       /*
-        * Save the command and its arguments.  This enables emulation of
-        * standard flash devices, and also some optimizations.
-        */
-       doc->last_command.command = command;
-       doc->last_command.column = column;
-       doc->last_command.page = page_addr;
-
-       switch (command) {
-
-       case NAND_CMD_RESET:
-               reset(mtd);
-               break;
-
-       case NAND_CMD_READ0:
-               read_page_prologue(mtd, g4_addr);
-               break;
-
-       case NAND_CMD_STATUS:
-               /* next call to read_byte() will expect a status */
-               break;
-
-       case NAND_CMD_SEQIN:
-               if (unlikely(reliable_mode)) {
-                       uint16_t g4_page = g4_addr >> 16;
-
-                       /* writes to odd-numbered 2k pages are invalid */
-                       if (g4_page & 0x01)
-                               dev_warn(doc->dev,
-                                        "invalid reliable mode address\n");
-               }
-
-               write_page_prologue(mtd, g4_addr);
-
-               /* hack for deferred write of oob bytes */
-               if (doc->oob_page == page_addr)
-                       memcpy(nand->oob_poi, doc->oob_buf, 16);
-               break;
-
-       case NAND_CMD_PAGEPROG:
-               pageprog(mtd);
-               break;
-
-       /* we don't expect these, based on review of nand_base.c */
-       case NAND_CMD_READOOB:
-       case NAND_CMD_READID:
-       case NAND_CMD_ERASE1:
-       case NAND_CMD_ERASE2:
-               dev_warn(doc->dev, "docg4_command: "
-                        "unexpected nand command 0x%x\n", command);
-               break;
-
-       }
-}
-
-static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
-                    uint8_t *buf, int page, bool use_ecc)
-{
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-       uint16_t status, edc_err, *buf16;
-       int bits_corrected = 0;
-
-       dev_dbg(doc->dev, "%s: page %08x\n", __func__, page);
-
-       nand_read_page_op(nand, page, 0, NULL, 0);
-
-       writew(DOC_ECCCONF0_READ_MODE |
-              DOC_ECCCONF0_ECC_ENABLE |
-              DOC_ECCCONF0_UNKNOWN |
-              DOCG4_BCH_SIZE,
-              docptr + DOC_ECCCONF0);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-
-       /* the 1st byte from the I/O reg is a status; the rest is page data */
-       status = readw(docptr + DOC_IOSPACE_DATA);
-       if (status & DOCG4_READ_ERROR) {
-               dev_err(doc->dev,
-                       "docg4_read_page: bad status: 0x%02x\n", status);
-               writew(0, docptr + DOC_DATAEND);
-               return -EIO;
-       }
-
-       dev_dbg(doc->dev, "%s: status = 0x%x\n", __func__, status);
-
-       docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */
-
-       /* this device always reads oob after page data */
-       /* first 14 oob bytes read from I/O reg */
-       docg4_read_buf(mtd, nand->oob_poi, 14);
-
-       /* last 2 read from another reg */
-       buf16 = (uint16_t *)(nand->oob_poi + 14);
-       *buf16 = readw(docptr + DOCG4_MYSTERY_REG);
-
-       write_nop(docptr);
-
-       if (likely(use_ecc == true)) {
-
-               /* read the register that tells us if bitflip(s) detected  */
-               edc_err = readw(docptr + DOC_ECCCONF1);
-               edc_err = readw(docptr + DOC_ECCCONF1);
-               dev_dbg(doc->dev, "%s: edc_err = 0x%02x\n", __func__, edc_err);
-
-               /* If bitflips are reported, attempt to correct with ecc */
-               if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) {
-                       bits_corrected = correct_data(mtd, buf, page);
-                       if (bits_corrected == -EBADMSG)
-                               mtd->ecc_stats.failed++;
-                       else
-                               mtd->ecc_stats.corrected += bits_corrected;
-               }
-       }
-
-       writew(0, docptr + DOC_DATAEND);
-       if (bits_corrected == -EBADMSG)   /* uncorrectable errors */
-               return 0;
-       return bits_corrected;
-}
-
-
-static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
-                              uint8_t *buf, int oob_required, int page)
-{
-       return read_page(mtd, nand, buf, page, false);
-}
-
-static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
-                          uint8_t *buf, int oob_required, int page)
-{
-       return read_page(mtd, nand, buf, page, true);
-}
-
-static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
-                         int page)
-{
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-       uint16_t status;
-
-       dev_dbg(doc->dev, "%s: page %x\n", __func__, page);
-
-       nand_read_page_op(nand, page, nand->ecc.size, NULL, 0);
-
-       writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-
-       /* the 1st byte from the I/O reg is a status; the rest is oob data */
-       status = readw(docptr + DOC_IOSPACE_DATA);
-       if (status & DOCG4_READ_ERROR) {
-               dev_warn(doc->dev,
-                        "docg4_read_oob failed: status = 0x%02x\n", status);
-               return -EIO;
-       }
-
-       dev_dbg(doc->dev, "%s: status = 0x%x\n", __func__, status);
-
-       docg4_read_buf(mtd, nand->oob_poi, 16);
-
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-       writew(0, docptr + DOC_DATAEND);
-       write_nop(docptr);
-
-       return 0;
-}
-
-static int docg4_erase_block(struct mtd_info *mtd, int page)
-{
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-       uint16_t g4_page;
-       int status;
-
-       dev_dbg(doc->dev, "%s: page %04x\n", __func__, page);
-
-       sequence_reset(mtd);
-
-       writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE);
-       writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND);
-       write_nop(docptr);
-
-       /* only 2 bytes of address are written to specify erase block */
-       g4_page = (uint16_t)(page / 4);  /* to g4's 2k page addressing */
-       writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
-       g4_page >>= 8;
-       writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
-       write_nop(docptr);
-
-       /* start the erasure */
-       writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND);
-       write_nop(docptr);
-       write_nop(docptr);
-
-       usleep_range(500, 1000); /* erasure is long; take a snooze */
-       poll_status(doc);
-       writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
-       writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
-       writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-       write_nop(docptr);
-
-       read_progstatus(doc);
-
-       writew(0, docptr + DOC_DATAEND);
-       write_nop(docptr);
-       poll_status(doc);
-       write_nop(docptr);
-
-       status = nand->waitfunc(mtd, nand);
-       if (status < 0)
-               return status;
-
-       return status & NAND_STATUS_FAIL ? -EIO : 0;
-}
-
-static int write_page(struct mtd_info *mtd, struct nand_chip *nand,
-                     const uint8_t *buf, int page, bool use_ecc)
-{
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-       uint8_t ecc_buf[8];
-
-       dev_dbg(doc->dev, "%s...\n", __func__);
-
-       nand_prog_page_begin_op(nand, page, 0, NULL, 0);
-
-       writew(DOC_ECCCONF0_ECC_ENABLE |
-              DOC_ECCCONF0_UNKNOWN |
-              DOCG4_BCH_SIZE,
-              docptr + DOC_ECCCONF0);
-       write_nop(docptr);
-
-       /* write the page data */
-       docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE);
-
-       /* oob bytes 0 through 5 are written to I/O reg */
-       docg4_write_buf16(mtd, nand->oob_poi, 6);
-
-       /* oob byte 6 written to a separate reg */
-       writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7);
-
-       write_nop(docptr);
-       write_nop(docptr);
-
-       /* write hw-generated ecc bytes to oob */
-       if (likely(use_ecc == true)) {
-               /* oob byte 7 is hamming code */
-               uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY);
-               hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */
-               writew(hamming, docptr + DOCG4_OOB_6_7);
-               write_nop(docptr);
-
-               /* read the 7 bch bytes from ecc regs */
-               read_hw_ecc(docptr, ecc_buf);
-               ecc_buf[7] = 0;         /* clear the "page written" flag */
-       }
-
-       /* write user-supplied bytes to oob */
-       else {
-               writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7);
-               write_nop(docptr);
-               memcpy(ecc_buf, &nand->oob_poi[8], 8);
-       }
-
-       docg4_write_buf16(mtd, ecc_buf, 8);
-       write_nop(docptr);
-       write_nop(docptr);
-       writew(0, docptr + DOC_DATAEND);
-       write_nop(docptr);
-
-       return nand_prog_page_end_op(nand);
-}
-
-static int docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
-                               const uint8_t *buf, int oob_required, int page)
-{
-       return write_page(mtd, nand, buf, page, false);
-}
-
-static int docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
-                            const uint8_t *buf, int oob_required, int page)
-{
-       return write_page(mtd, nand, buf, page, true);
-}
-
-static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
-                          int page)
-{
-       /*
-        * Writing oob-only is not really supported, because MLC nand must write
-        * oob bytes at the same time as page data.  Nonetheless, we save the
-        * oob buffer contents here, and then write it along with the page data
-        * if the same page is subsequently written.  This allows user space
-        * utilities that write the oob data prior to the page data to work
-        * (e.g., nandwrite).  The disdvantage is that, if the intention was to
-        * write oob only, the operation is quietly ignored.  Also, oob can get
-        * corrupted if two concurrent processes are running nandwrite.
-        */
-
-       /* note that bytes 7..14 are hw generated hamming/ecc and overwritten */
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       doc->oob_page = page;
-       memcpy(doc->oob_buf, nand->oob_poi, 16);
-       return 0;
-}
-
-static int __init read_factory_bbt(struct mtd_info *mtd)
-{
-       /*
-        * The device contains a read-only factory bad block table.  Read it and
-        * update the memory-based bbt accordingly.
-        */
-
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0);
-       uint8_t *buf;
-       int i, block;
-       __u32 eccfailed_stats = mtd->ecc_stats.failed;
-
-       buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
-       if (buf == NULL)
-               return -ENOMEM;
-
-       read_page_prologue(mtd, g4_addr);
-       docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE);
-
-       /*
-        * If no memory-based bbt was created, exit.  This will happen if module
-        * parameter ignore_badblocks is set.  Then why even call this function?
-        * For an unknown reason, block erase always fails if it's the first
-        * operation after device power-up.  The above read ensures it never is.
-        * Ugly, I know.
-        */
-       if (nand->bbt == NULL)  /* no memory-based bbt */
-               goto exit;
-
-       if (mtd->ecc_stats.failed > eccfailed_stats) {
-               /*
-                * Whoops, an ecc failure ocurred reading the factory bbt.
-                * It is stored redundantly, so we get another chance.
-                */
-               eccfailed_stats = mtd->ecc_stats.failed;
-               docg4_read_page(mtd, nand, buf, 0, DOCG4_REDUNDANT_BBT_PAGE);
-               if (mtd->ecc_stats.failed > eccfailed_stats) {
-                       dev_warn(doc->dev,
-                                "The factory bbt could not be read!\n");
-                       goto exit;
-               }
-       }
-
-       /*
-        * Parse factory bbt and update memory-based bbt.  Factory bbt format is
-        * simple: one bit per block, block numbers increase left to right (msb
-        * to lsb).  Bit clear means bad block.
-        */
-       for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) {
-               int bitnum;
-               unsigned long bits = ~buf[i];
-               for_each_set_bit(bitnum, &bits, 8) {
-                       int badblock = block + 7 - bitnum;
-                       nand->bbt[badblock / 4] |=
-                               0x03 << ((badblock % 4) * 2);
-                       mtd->ecc_stats.badblocks++;
-                       dev_notice(doc->dev, "factory-marked bad block: %d\n",
-                                  badblock);
-               }
-       }
- exit:
-       kfree(buf);
-       return 0;
-}
-
-static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs)
-{
-       /*
-        * Mark a block as bad.  Bad blocks are marked in the oob area of the
-        * first page of the block.  The default scan_bbt() in the nand
-        * infrastructure code works fine for building the memory-based bbt
-        * during initialization, as does the nand infrastructure function that
-        * checks if a block is bad by reading the bbt.  This function replaces
-        * the nand default because writes to oob-only are not supported.
-        */
-
-       int ret, i;
-       uint8_t *buf;
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       struct nand_bbt_descr *bbtd = nand->badblock_pattern;
-       int page = (int)(ofs >> nand->page_shift);
-       uint32_t g4_addr = mtd_to_docg4_address(page, 0);
-
-       dev_dbg(doc->dev, "%s: %08llx\n", __func__, ofs);
-
-       if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1)))
-               dev_warn(doc->dev, "%s: ofs %llx not start of block!\n",
-                        __func__, ofs);
-
-       /* allocate blank buffer for page data */
-       buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
-       if (buf == NULL)
-               return -ENOMEM;
-
-       /* write bit-wise negation of pattern to oob buffer */
-       memset(nand->oob_poi, 0xff, mtd->oobsize);
-       for (i = 0; i < bbtd->len; i++)
-               nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i];
-
-       /* write first page of block */
-       write_page_prologue(mtd, g4_addr);
-       docg4_write_page(mtd, nand, buf, 1, page);
-       ret = pageprog(mtd);
-
-       kfree(buf);
-
-       return ret;
-}
-
-static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs)
-{
-       /* only called when module_param ignore_badblocks is set */
-       return 0;
-}
-
-static int docg4_suspend(struct platform_device *pdev, pm_message_t state)
-{
-       /*
-        * Put the device into "deep power-down" mode.  Note that CE# must be
-        * deasserted for this to take effect.  The xscale, e.g., can be
-        * configured to float this signal when the processor enters power-down,
-        * and a suitable pull-up ensures its deassertion.
-        */
-
-       int i;
-       uint8_t pwr_down;
-       struct docg4_priv *doc = platform_get_drvdata(pdev);
-       void __iomem *docptr = doc->virtadr;
-
-       dev_dbg(doc->dev, "%s...\n", __func__);
-
-       /* poll the register that tells us we're ready to go to sleep */
-       for (i = 0; i < 10; i++) {
-               pwr_down = readb(docptr + DOC_POWERMODE);
-               if (pwr_down & DOC_POWERDOWN_READY)
-                       break;
-               usleep_range(1000, 4000);
-       }
-
-       if (pwr_down & DOC_POWERDOWN_READY) {
-               dev_err(doc->dev, "suspend failed; "
-                       "timeout polling DOC_POWERDOWN_READY\n");
-               return -EIO;
-       }
-
-       writew(DOC_ASICMODE_POWERDOWN | DOC_ASICMODE_MDWREN,
-              docptr + DOC_ASICMODE);
-       writew(~(DOC_ASICMODE_POWERDOWN | DOC_ASICMODE_MDWREN),
-              docptr + DOC_ASICMODECONFIRM);
-
-       write_nop(docptr);
-
-       return 0;
-}
-
-static int docg4_resume(struct platform_device *pdev)
-{
-
-       /*
-        * Exit power-down.  Twelve consecutive reads of the address below
-        * accomplishes this, assuming CE# has been asserted.
-        */
-
-       struct docg4_priv *doc = platform_get_drvdata(pdev);
-       void __iomem *docptr = doc->virtadr;
-       int i;
-
-       dev_dbg(doc->dev, "%s...\n", __func__);
-
-       for (i = 0; i < 12; i++)
-               readb(docptr + 0x1fff);
-
-       return 0;
-}
-
-static void init_mtd_structs(struct mtd_info *mtd)
-{
-       /* initialize mtd and nand data structures */
-
-       /*
-        * Note that some of the following initializations are not usually
-        * required within a nand driver because they are performed by the nand
-        * infrastructure code as part of nand_scan().  In this case they need
-        * to be initialized here because we skip call to nand_scan_ident() (the
-        * first half of nand_scan()).  The call to nand_scan_ident() could be
-        * skipped because for this device the chip id is not read in the manner
-        * of a standard nand device.
-        */
-
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-
-       mtd->size = DOCG4_CHIP_SIZE;
-       mtd->name = "Msys_Diskonchip_G4";
-       mtd->writesize = DOCG4_PAGE_SIZE;
-       mtd->erasesize = DOCG4_BLOCK_SIZE;
-       mtd->oobsize = DOCG4_OOB_SIZE;
-       mtd_set_ooblayout(mtd, &docg4_ooblayout_ops);
-       nand->chipsize = DOCG4_CHIP_SIZE;
-       nand->chip_shift = DOCG4_CHIP_SHIFT;
-       nand->bbt_erase_shift = nand->phys_erase_shift = DOCG4_ERASE_SHIFT;
-       nand->chip_delay = 20;
-       nand->page_shift = DOCG4_PAGE_SHIFT;
-       nand->pagemask = 0x3ffff;
-       nand->badblockpos = NAND_LARGE_BADBLOCK_POS;
-       nand->badblockbits = 8;
-       nand->ecc.mode = NAND_ECC_HW_SYNDROME;
-       nand->ecc.size = DOCG4_PAGE_SIZE;
-       nand->ecc.prepad = 8;
-       nand->ecc.bytes = 8;
-       nand->ecc.strength = DOCG4_T;
-       nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
-       nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA;
-       nand->controller = &nand->dummy_controller;
-       nand_controller_init(nand->controller);
-
-       /* methods */
-       nand->cmdfunc = docg4_command;
-       nand->waitfunc = docg4_wait;
-       nand->select_chip = docg4_select_chip;
-       nand->read_byte = docg4_read_byte;
-       nand->block_markbad = docg4_block_markbad;
-       nand->read_buf = docg4_read_buf;
-       nand->write_buf = docg4_write_buf16;
-       nand->erase = docg4_erase_block;
-       nand->set_features = nand_get_set_features_notsupp;
-       nand->get_features = nand_get_set_features_notsupp;
-       nand->ecc.read_page = docg4_read_page;
-       nand->ecc.write_page = docg4_write_page;
-       nand->ecc.read_page_raw = docg4_read_page_raw;
-       nand->ecc.write_page_raw = docg4_write_page_raw;
-       nand->ecc.read_oob = docg4_read_oob;
-       nand->ecc.write_oob = docg4_write_oob;
-
-       /*
-        * The way the nand infrastructure code is written, a memory-based bbt
-        * is not created if NAND_SKIP_BBTSCAN is set.  With no memory bbt,
-        * nand->block_bad() is used.  So when ignoring bad blocks, we skip the
-        * scan and define a dummy block_bad() which always returns 0.
-        */
-       if (ignore_badblocks) {
-               nand->options |= NAND_SKIP_BBTSCAN;
-               nand->block_bad = docg4_block_neverbad;
-       }
-
-}
-
-static int read_id_reg(struct mtd_info *mtd)
-{
-       struct nand_chip *nand = mtd_to_nand(mtd);
-       struct docg4_priv *doc = nand_get_controller_data(nand);
-       void __iomem *docptr = doc->virtadr;
-       uint16_t id1, id2;
-
-       /* check for presence of g4 chip by reading id registers */
-       id1 = readw(docptr + DOC_CHIPID);
-       id1 = readw(docptr + DOCG4_MYSTERY_REG);
-       id2 = readw(docptr + DOC_CHIPID_INV);
-       id2 = readw(docptr + DOCG4_MYSTERY_REG);
-
-       if (id1 == DOCG4_IDREG1_VALUE && id2 == DOCG4_IDREG2_VALUE) {
-               dev_info(doc->dev,
-                        "NAND device: 128MiB Diskonchip G4 detected\n");
-               return 0;
-       }
-
-       return -ENODEV;
-}
-
-static char const *part_probes[] = { "cmdlinepart", "saftlpart", NULL };
-
-static int docg4_attach_chip(struct nand_chip *chip)
-{
-       struct mtd_info *mtd = nand_to_mtd(chip);
-       struct docg4_priv *doc = (struct docg4_priv *)(chip + 1);
-       int ret;
-
-       init_mtd_structs(mtd);
-
-       /* Initialize kernel BCH algorithm */
-       doc->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY);
-       if (!doc->bch)
-               return -EINVAL;
-
-       reset(mtd);
-
-       ret = read_id_reg(mtd);
-       if (ret)
-               free_bch(doc->bch);
-
-       return ret;
-}
-
-static void docg4_detach_chip(struct nand_chip *chip)
-{
-       struct docg4_priv *doc = (struct docg4_priv *)(chip + 1);
-
-       free_bch(doc->bch);
-}
-
-static const struct nand_controller_ops docg4_controller_ops = {
-       .attach_chip = docg4_attach_chip,
-       .detach_chip = docg4_detach_chip,
-};
-
-static int __init probe_docg4(struct platform_device *pdev)
-{
-       struct mtd_info *mtd;
-       struct nand_chip *nand;
-       void __iomem *virtadr;
-       struct docg4_priv *doc;
-       int len, retval;
-       struct resource *r;
-       struct device *dev = &pdev->dev;
-
-       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       if (r == NULL) {
-               dev_err(dev, "no io memory resource defined!\n");
-               return -ENODEV;
-       }
-
-       virtadr = ioremap(r->start, resource_size(r));
-       if (!virtadr) {
-               dev_err(dev, "Diskonchip ioremap failed: %pR\n", r);
-               return -EIO;
-       }
-
-       len = sizeof(struct nand_chip) + sizeof(struct docg4_priv);
-       nand = kzalloc(len, GFP_KERNEL);
-       if (nand == NULL) {
-               retval = -ENOMEM;
-               goto unmap;
-       }
-
-       mtd = nand_to_mtd(nand);
-       doc = (struct docg4_priv *) (nand + 1);
-       nand_set_controller_data(nand, doc);
-       mtd->dev.parent = &pdev->dev;
-       doc->virtadr = virtadr;
-       doc->dev = dev;
-       platform_set_drvdata(pdev, doc);
-
-       /*
-        * Running nand_scan() with maxchips == 0 will skip nand_scan_ident(),
-        * which is a specific operation with this driver and done in the
-        * ->attach_chip callback.
-        */
-       nand->dummy_controller.ops = &docg4_controller_ops;
-       retval = nand_scan(mtd, 0);
-       if (retval)
-               goto free_nand;
-
-       retval = read_factory_bbt(mtd);
-       if (retval)
-               goto cleanup_nand;
-
-       retval = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
-       if (retval)
-               goto cleanup_nand;
-
-       doc->mtd = mtd;
-
-       return 0;
-
-cleanup_nand:
-       nand_cleanup(nand);
-free_nand:
-       kfree(nand);
-unmap:
-       iounmap(virtadr);
-
-       return retval;
-}
-
-static int __exit cleanup_docg4(struct platform_device *pdev)
-{
-       struct docg4_priv *doc = platform_get_drvdata(pdev);
-       nand_release(doc->mtd);
-       kfree(mtd_to_nand(doc->mtd));
-       iounmap(doc->virtadr);
-       return 0;
-}
-
-static struct platform_driver docg4_driver = {
-       .driver         = {
-               .name   = "docg4",
-       },
-       .suspend        = docg4_suspend,
-       .resume         = docg4_resume,
-       .remove         = __exit_p(cleanup_docg4),
-};
-
-module_platform_driver_probe(docg4_driver, probe_docg4);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Mike Dunn");
-MODULE_DESCRIPTION("M-Systems DiskOnChip G4 device driver");
index 55f449b711fd9fc4ad8ff2fc68f35524f37a481a..d6ed697fcfe6e6e4ddd8b4ddc97fca7000918502 100644 (file)
@@ -317,10 +317,10 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 }
 
 /* cmdfunc send commands to the FCM */
-static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
+static void fsl_elbc_cmdfunc(struct nand_chip *chip, unsigned int command,
                              int column, int page_addr)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
        struct fsl_lbc_ctrl *ctrl = priv->ctrl;
        struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
@@ -533,7 +533,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
        }
 }
 
-static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
+static void fsl_elbc_select_chip(struct nand_chip *chip, int cs)
 {
        /* The hardware does not seem to support multiple
         * chips per bank.
@@ -543,9 +543,9 @@ static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 /*
  * Write buf to the FCM Controller Data Buffer
  */
-static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+static void fsl_elbc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
        struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
        unsigned int bufsize = mtd->writesize + mtd->oobsize;
@@ -581,9 +581,8 @@ static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  * read a byte from either the FCM hardware buffer if it has any data left
  * otherwise issue a command to read a single byte.
  */
-static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
+static u8 fsl_elbc_read_byte(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
        struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 
@@ -598,9 +597,8 @@ static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 /*
  * Read from the FCM Controller Data Buffer
  */
-static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+static void fsl_elbc_read_buf(struct nand_chip *chip, u8 *buf, int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
        struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
        int avail;
@@ -623,7 +621,7 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 /* This function is called after Program and Erase Operations to
  * check for success or failure.
  */
-static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
+static int fsl_elbc_wait(struct nand_chip *chip)
 {
        struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
        struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
@@ -660,8 +658,8 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip)
                chip->chipsize);
        dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
                chip->pagemask);
-       dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
-               chip->chip_delay);
+       dev_dbg(priv->dev, "fsl_elbc_init: nand->legacy.chip_delay = %d\n",
+               chip->legacy.chip_delay);
        dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
                chip->badblockpos);
        dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
@@ -710,18 +708,19 @@ static const struct nand_controller_ops fsl_elbc_controller_ops = {
        .attach_chip = fsl_elbc_attach_chip,
 };
 
-static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
-                             uint8_t *buf, int oob_required, int page)
+static int fsl_elbc_read_page(struct nand_chip *chip, uint8_t *buf,
+                             int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
        struct fsl_lbc_ctrl *ctrl = priv->ctrl;
        struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 
        nand_read_page_op(chip, page, 0, buf, mtd->writesize);
        if (oob_required)
-               fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
+               fsl_elbc_read_buf(chip, chip->oob_poi, mtd->oobsize);
 
-       if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
+       if (fsl_elbc_wait(chip) & NAND_STATUS_FAIL)
                mtd->ecc_stats.failed++;
 
        return elbc_fcm_ctrl->max_bitflips;
@@ -730,11 +729,13 @@ static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 /* ECC will be calculated automatically, and errors will be detected in
  * waitfunc.
  */
-static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-                               const uint8_t *buf, int oob_required, int page)
+static int fsl_elbc_write_page(struct nand_chip *chip, const uint8_t *buf,
+                              int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
+
        nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
-       fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
+       fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize);
 
        return nand_prog_page_end_op(chip);
 }
@@ -742,13 +743,15 @@ static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 /* ECC will be calculated automatically, and errors will be detected in
  * waitfunc.
  */
-static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
-                               uint32_t offset, uint32_t data_len,
-                               const uint8_t *buf, int oob_required, int page)
+static int fsl_elbc_write_subpage(struct nand_chip *chip, uint32_t offset,
+                                 uint32_t data_len, const uint8_t *buf,
+                                 int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
+
        nand_prog_page_begin_op(chip, page, 0, NULL, 0);
-       fsl_elbc_write_buf(mtd, buf, mtd->writesize);
-       fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
+       fsl_elbc_write_buf(chip, buf, mtd->writesize);
+       fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize);
        return nand_prog_page_end_op(chip);
 }
 
@@ -773,14 +776,14 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 
        /* fill in nand_chip structure */
        /* set up function call table */
-       chip->read_byte = fsl_elbc_read_byte;
-       chip->write_buf = fsl_elbc_write_buf;
-       chip->read_buf = fsl_elbc_read_buf;
+       chip->legacy.read_byte = fsl_elbc_read_byte;
+       chip->legacy.write_buf = fsl_elbc_write_buf;
+       chip->legacy.read_buf = fsl_elbc_read_buf;
        chip->select_chip = fsl_elbc_select_chip;
-       chip->cmdfunc = fsl_elbc_cmdfunc;
-       chip->waitfunc = fsl_elbc_wait;
-       chip->set_features = nand_get_set_features_notsupp;
-       chip->get_features = nand_get_set_features_notsupp;
+       chip->legacy.cmdfunc = fsl_elbc_cmdfunc;
+       chip->legacy.waitfunc = fsl_elbc_wait;
+       chip->legacy.set_features = nand_get_set_features_notsupp;
+       chip->legacy.get_features = nand_get_set_features_notsupp;
 
        chip->bbt_td = &bbt_main_descr;
        chip->bbt_md = &bbt_mirror_descr;
@@ -915,7 +918,7 @@ static int fsl_elbc_nand_probe(struct platform_device *pdev)
                goto err;
 
        priv->chip.controller->ops = &fsl_elbc_controller_ops;
-       ret = nand_scan(mtd, 1);
+       ret = nand_scan(&priv->chip, 1);
        if (ret)
                goto err;
 
@@ -942,9 +945,8 @@ static int fsl_elbc_nand_remove(struct platform_device *pdev)
 {
        struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
        struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev);
-       struct mtd_info *mtd = nand_to_mtd(&priv->chip);
 
-       nand_release(mtd);
+       nand_release(&priv->chip);
        fsl_elbc_chip_remove(priv);
 
        mutex_lock(&fsl_elbc_nand_mutex);
index 24f59d0066afdd77d586f29b944f566e0038d98c..6f4afc44381a3e05affc9bfbe14d2069e876a398 100644 (file)
@@ -30,6 +30,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/fsl_ifc.h>
+#include <linux/iopoll.h>
 
 #define ERR_BYTE               0xFF /* Value returned for read
                                        bytes when read failed  */
@@ -300,9 +301,9 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
 }
 
 /* cmdfunc send commands to the IFC NAND Machine */
-static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
-                            int column, int page_addr) {
-       struct nand_chip *chip = mtd_to_nand(mtd);
+static void fsl_ifc_cmdfunc(struct nand_chip *chip, unsigned int command,
+                           int column, int page_addr) {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
        struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
@@ -508,7 +509,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
        }
 }
 
-static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
+static void fsl_ifc_select_chip(struct nand_chip *chip, int cs)
 {
        /* The hardware does not seem to support multiple
         * chips per bank.
@@ -518,9 +519,9 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 /*
  * Write buf to the IFC NAND Controller Data Buffer
  */
-static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+static void fsl_ifc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
        unsigned int bufsize = mtd->writesize + mtd->oobsize;
 
@@ -544,9 +545,8 @@ static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  * Read a byte from either the IFC hardware buffer
  * read function for 8-bit buswidth
  */
-static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
+static uint8_t fsl_ifc_read_byte(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
        unsigned int offset;
 
@@ -567,9 +567,8 @@ static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
  * Read two bytes from the IFC hardware buffer
  * read function for 16-bit buswith
  */
-static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
+static uint8_t fsl_ifc_read_byte16(struct nand_chip *chip)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
        uint16_t data;
 
@@ -590,9 +589,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 /*
  * Read from the IFC Controller Data Buffer
  */
-static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+static void fsl_ifc_read_buf(struct nand_chip *chip, u8 *buf, int len)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
        int avail;
 
@@ -616,8 +614,9 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  * This function is called after Program and Erase Operations to
  * check for success or failure.
  */
-static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
+static int fsl_ifc_wait(struct nand_chip *chip)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
        struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
@@ -678,20 +677,21 @@ static int check_erased_page(struct nand_chip *chip, u8 *buf)
        return bitflips;
 }
 
-static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
-                            uint8_t *buf, int oob_required, int page)
+static int fsl_ifc_read_page(struct nand_chip *chip, uint8_t *buf,
+                            int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
        struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 
        nand_read_page_op(chip, page, 0, buf, mtd->writesize);
        if (oob_required)
-               fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
+               fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
 
        if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) {
                if (!oob_required)
-                       fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
+                       fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
 
                return check_erased_page(chip, buf);
        }
@@ -705,11 +705,13 @@ static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 /* ECC will be calculated automatically, and errors will be detected in
  * waitfunc.
  */
-static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-                              const uint8_t *buf, int oob_required, int page)
+static int fsl_ifc_write_page(struct nand_chip *chip, const uint8_t *buf,
+                             int oob_required, int page)
 {
+       struct mtd_info *mtd = nand_to_mtd(chip);
+
        nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
-       fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
+       fsl_ifc_write_buf(chip, chip->oob_poi, mtd->oobsize);
 
        return nand_prog_page_end_op(chip);
 }
@@ -725,8 +727,8 @@ static int fsl_ifc_attach_chip(struct nand_chip *chip)
                                                        chip->chipsize);
        dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
                                                        chip->pagemask);
-       dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
-                                                       chip->chip_delay);
+       dev_dbg(priv->dev, "%s: nand->legacy.chip_delay = %d\n", __func__,
+               chip->legacy.chip_delay);
        dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
                                                        chip->badblockpos);
        dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
@@ -761,7 +763,7 @@ static const struct nand_controller_ops fsl_ifc_controller_ops = {
        .attach_chip = fsl_ifc_attach_chip,
 };
 
-static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
+static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
 {
        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
        struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
@@ -769,6 +771,27 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
        uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
        uint32_t cs = priv->bank;
 
+       if (ctrl->version < FSL_IFC_VERSION_1_1_0)
+               return 0;
+
+       if (ctrl->version > FSL_IFC_VERSION_1_1_0) {
+               u32 ncfgr, status;
+               int ret;
+
+               /* Trigger auto initialization */
+               ncfgr = ifc_in32(&ifc_runtime->ifc_nand.ncfgr);
+               ifc_out32(ncfgr | IFC_NAND_NCFGR_SRAM_INIT_EN, &ifc_runtime->ifc_nand.ncfgr);
+
+               /* Wait until done */
+               ret = readx_poll_timeout(ifc_in32, &ifc_runtime->ifc_nand.ncfgr,
+                                        status, !(status & IFC_NAND_NCFGR_SRAM_INIT_EN),
+                                        10, IFC_TIMEOUT_MSECS * 1000);
+               if (ret)
+                       dev_err(priv->dev, "Failed to initialize SRAM!\n");
+
+               return ret;
+       }
+
        /* Save CSOR and CSOR_ext */
        csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
        csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
@@ -805,12 +828,16 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
        wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
                           msecs_to_jiffies(IFC_TIMEOUT_MSECS));
 
-       if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
+       if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) {
                pr_err("fsl-ifc: Failed to Initialise SRAM\n");
+               return -ETIMEDOUT;
+       }
 
        /* Restore CSOR and CSOR_ext */
        ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
        ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
+
+       return 0;
 }
 
 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
@@ -821,6 +848,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
        struct nand_chip *chip = &priv->chip;
        struct mtd_info *mtd = nand_to_mtd(&priv->chip);
        u32 csor;
+       int ret;
 
        /* Fill in fsl_ifc_mtd structure */
        mtd->dev.parent = priv->dev;
@@ -830,17 +858,17 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
        /* set up function call table */
        if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
                & CSPR_PORT_SIZE_16)
-               chip->read_byte = fsl_ifc_read_byte16;
+               chip->legacy.read_byte = fsl_ifc_read_byte16;
        else
-               chip->read_byte = fsl_ifc_read_byte;
+               chip->legacy.read_byte = fsl_ifc_read_byte;
 
-       chip->write_buf = fsl_ifc_write_buf;
-       chip->read_buf = fsl_ifc_read_buf;
+       chip->legacy.write_buf = fsl_ifc_write_buf;
+       chip->legacy.read_buf = fsl_ifc_read_buf;
        chip->select_chip = fsl_ifc_select_chip;
-       chip->cmdfunc = fsl_ifc_cmdfunc;
-       chip->waitfunc = fsl_ifc_wait;
-       chip->set_features = nand_get_set_features_notsupp;
-       chip->get_features = nand_get_set_features_notsupp;
+       chip->legacy.cmdfunc = fsl_ifc_cmdfunc;
+       chip->legacy.waitfunc = fsl_ifc_wait;
+       chip->legacy.set_features = nand_get_set_features_notsupp;
+       chip->legacy.get_features = nand_get_set_features_notsupp;
 
        chip->bbt_td = &bbt_main_descr;
        chip->bbt_md = &bbt_mirror_descr;
@@ -853,10 +881,10 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 
        if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
                & CSPR_PORT_SIZE_16) {
-               chip->read_byte = fsl_ifc_read_byte16;
+               chip->legacy.read_byte = fsl_ifc_read_byte16;
                chip->options |= NAND_BUSWIDTH_16;
        } else {
-               chip->read_byte = fsl_ifc_read_byte;
+               chip->legacy.read_byte = fsl_ifc_read_byte;
        }
 
        chip->controller = &ifc_nand_ctrl->controller;
@@ -914,8 +942,9 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
                chip->ecc.algo = NAND_ECC_HAMMING;
        }
 
-       if (ctrl->version >= FSL_IFC_VERSION_1_1_0)
-               fsl_ifc_sram_init(priv);
+       ret = fsl_ifc_sram_init(priv);
+       if (ret)
+               return ret;
 
        /*
         * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
@@ -1051,7 +1080,7 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
                goto err;
 
        priv->chip.controller->ops = &fsl_ifc_controller_ops;
-       ret = nand_scan(mtd, 1);
+       ret = nand_scan(&priv->chip, 1);
        if (ret)
                goto err;
 
@@ -1077,9 +1106,8 @@ err:
 static int fsl_ifc_nand_remove(struct platform_device *dev)
 {
        struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
-       struct mtd_info *mtd = nand_to_mtd(&priv->chip);
 
-       nand_release(mtd);
+       nand_release(&priv->chip);
        fsl_ifc_chip_remove(priv);
 
        mutex_lock(&fsl_ifc_nand_mutex);
index a88e2cf66e0f69a0d5d94ea4d1340701c82884ec..673c5a0c9345691160bb76a2415f2a8791d44ec9 100644 (file)
@@ -52,9 +52,9 @@ static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
                            chip);
 }
 
-static int fun_chip_ready(struct mtd_info *mtd)
+static int fun_chip_ready(struct nand_chip *chip)
 {
-       struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
+       struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
 
        if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
                return 1;
@@ -69,7 +69,7 @@ static void fun_wait_rnb(struct fsl_upm_nand *fun)
                struct mtd_info *mtd = nand_to_mtd(&fun->chip);
                int cnt = 1000000;
 
-               while (--cnt && !fun_chip_ready(mtd))
+               while (--cnt && !fun_chip_ready(&fun->chip))
                        cpu_relax();
                if (!cnt)
                        dev_err(fun->dev, "tired waiting for RNB\n");
@@ -78,10 +78,9 @@ static void fun_wait_rnb(struct fsl_upm_nand *fun)
        }
 }
 
-static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void fun_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-       struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
+       struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
        u32 mar;
 
        if (!(ctrl & fun->last_ctrl)) {
@@ -102,51 +101,50 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 
        mar = (cmd << (32 - fun->upm.width)) |
                fun->mchip_offsets[fun->mchip_number];
-       fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);
+       fsl_upm_run_pattern(&fun->upm, chip->legacy.IO_ADDR_R, mar);
 
        if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
                fun_wait_rnb(fun);
 }
 
-static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
+static void fun_select_chip(struct nand_chip *chip, int mchip_nr)
 {
-       struct nand_chip *chip = mtd_to_nand(mtd);
-       struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
+       struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
 
        if (mchip_nr == -1) {
-               chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
+               chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
        } else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
                fun->mchip_number = mchip_nr;
-               chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
-               chip->IO_ADDR_W = chip->IO_ADDR_R;
+               chip->legacy.IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
+               chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
        } else {
                BUG();
        }
 }
 
-static uint8_t fun_read_byte(struct mtd_info *mtd)
+static uint8_t fun_read_byte(struct nand_chip *chip)
 {
-       struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
+       struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
 
-       return in_8(fun->chip.IO_ADDR_R);
+       return in_8(fun->chip.legacy.IO_ADDR_R);
 }
 
-static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+static void fun_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
 {
-       struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
+       struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
        int i;
 
        for (i = 0; i < len; i++)
-               buf[i] = in_8(fun->chip.IO_ADDR_R);
+               buf[i] = in_8(fun->chip.legacy.IO_ADDR_R);
 }
 
-static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+static void fun_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
 {
-       struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
+       struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
        int i;
 
        for (i = 0; i < len; i++) {
-               out_8(fun->chip.IO_ADDR_W, buf[i]);
+               out_8(fun->chip.legacy.IO_ADDR_W, buf[i]);
                if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
                        fun_wait_rnb(fun);
        }
@@ -162,20 +160,20 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
        int ret;
        struct device_node *flash_np;
 
-       fun->chip.IO_ADDR_R = fun->io_base;
-       fun->chip.IO_ADDR_W = fun->io_base;
-       fun->chip.cmd_ctrl = fun_cmd_ctrl;
-       fun->chip.chip_delay = fun->chip_delay;
-       fun->chip.read_byte = fun_read_byte;
-       fun->chip.read_buf = fun_read_buf;
-       fun->chip.write_buf = fun_write_buf;
+       fun->chip.legacy.IO_ADDR_R = fun->io_base;
+       fun->chip.legacy.IO_ADDR_W = fun->io_base;
+       fun->chip.legacy.cmd_ctrl = fun_cmd_ctrl;
+       fun->chip.legacy.chip_delay = fun->chip_delay;
+       fun->chip.legacy.read_byte = fun_read_byte;
+       fun->chip.legacy.read_buf = fun_read_buf;
+       fun->chip.legacy.write_buf = fun_write_buf;
        fun->chip.ecc.mode = NAND_ECC_SOFT;
        fun->chip.ecc.algo = NAND_ECC_HAMMING;
        if (fun->mchip_count > 1)
                fun->chip.select_chip = fun_select_chip;
 
        if (fun->rnb_gpio[0] >= 0)
-               fun->chip.dev_ready = fun_chip_ready;
+               fun->chip.legacy.dev_ready = fun_chip_ready;
 
        mtd->dev.parent = fun->dev;
 
@@ -184,14 +182,14 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
                return -ENODEV;
 
        nand_set_flash_node(&fun->chip, flash_np);
-       mtd->name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
-                             flash_np->name);
+       mtd->name = kasprintf(GFP_KERNEL, "0x%llx.%pOFn", (u64)io_res->start,
+                             flash_np);
        if (!mtd->name) {
                ret = -ENOMEM;
                goto err;
        }
 
-       ret = nand_scan(mtd, fun->mchip_count);
+       ret = nand_scan(&fun->chip, fun->mchip_count);
        if (ret)
                goto err;
 
@@ -326,7 +324,7 @@ static int fun_remove(struct platform_device *ofdev)
        struct mtd_info *mtd = nand_to_mtd(&fun->chip);
        int i;
 
-       nand_release(mtd);
+       nand_release(&fun->chip);
        kfree(mtd->name);
 
        for (i = 0; i < fun->mchip_count; i++) {
index f418236fa020adfdbd502efbc494c8ef66f90154..70ac8d875218e5010a30ad020f944586eee8241c 100644 (file)
@@ -340,10 +340,9 @@ static int fsmc_calc_timings(struct fsmc_nand_data *host,
        return 0;
 }
 
-static int fsmc_setup_data_interface(struct mtd_info *mtd, int csline,
+static int fsmc_setup_data_interface(struct nand_chip *nand, int csline,
                                     const struct nand_data_interface *conf)
 {
-       struct nand_chip *nand = mtd_to_nand(mtd);
        struct fsmc_nand_data *host = nand_get_controller_data(nand);
        struct fsmc_nand_timings tims;
        const struct nand_sdr_timings *sdrt;
@@ -368,9 +367,9 @@ static int fsmc_setup_data_interface(struct mtd_info *mtd, int csline,
 /*
  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
  */
-static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
+static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
 {
-       struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
+       struct fsmc_nand_data *host = mtd_to_fsmc(nand_to_mtd(chip));
 
        writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
                       host->regs_va + FSMC_PC);
@@ -385,10 +384,10 @@ static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
  * max of 8-bits)
  */
-static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
+static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const uint8_t *data,
                                uint8_t *ecc)
 {
-       struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
+       struct fsmc_nand_data *host = mtd_to_fsmc(nand_to_mtd(chip));
        uint32_t ecc_tmp;
        unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 
@@ -433,10 +432,10 @@ static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
  * max of 1-bit)
  */
-static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
+static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const uint8_t *data,
                                uint8_t *ecc)
 {
-       struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
+       struct fsmc_nand_data *host = mtd_to_fsmc(nand_to_mtd(chip));
        uint32_t ecc_tmp;
 
        ecc_tmp = readl_relaxed(host->regs_va + ECC1);
@@