Merge branches 'clk-stm32mp1', 'clk-samsung', 'clk-uniphier-mpeg', 'clk-stratix10...
authorStephen Boyd <sboyd@kernel.org>
Mon, 4 Jun 2018 19:27:34 +0000 (12:27 -0700)
committerStephen Boyd <sboyd@kernel.org>
Mon, 4 Jun 2018 19:27:34 +0000 (12:27 -0700)
* clk-stm32mp1:
  clk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()'
  clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock
  clk: stm32mp1: remove ck_apb_dbg clock
  clk: stm32mp1: set stgen_k clock as critical
  clk: stm32mp1: add missing tzc2 clock
  clk: stm32mp1: fix SAI3 & SAI4 clocks
  clk: stm32mp1: remove unused dfsdm_src[] const
  clk: stm32mp1: add missing static

* clk-samsung:
  clk: samsung: simplify getting .drvdata

* clk-uniphier-mpeg:
  clk: uniphier: add LD11/LD20 stream demux system clock

* clk-stratix10:
  clk: socfpga: stratix10: suppress unbinding platform's clock driver
  clk: socfpga: stratix10: use platform driver APIs

* clk-aspeed:
  clk:aspeed: Fix reset bits for PCI/VGA and PECI
  clk: aspeed: Support second reset register

drivers/clk/clk-aspeed.c
drivers/clk/clk-stm32mp1.c
drivers/clk/samsung/clk-s3c2410-dclk.c
drivers/clk/socfpga/clk-s10.c
drivers/clk/uniphier/clk-uniphier-sys.c
include/dt-bindings/clock/aspeed-clock.h
include/dt-bindings/clock/stm32mp1-clks.h

index 5eb50c31e4553c114a6ce62d38a4afb0b158f9b6..eb5fb7f88ccd39ab986310760cb675a7160ee87c 100644 (file)
@@ -16,6 +16,8 @@
 
 #define ASPEED_NUM_CLKS                35
 
+#define ASPEED_RESET2_OFFSET   32
+
 #define ASPEED_RESET_CTRL      0x04
 #define ASPEED_CLK_SELECTION   0x08
 #define ASPEED_CLK_STOP_CTRL   0x0c
@@ -30,6 +32,7 @@
 #define  CLKIN_25MHZ_EN                BIT(23)
 #define  AST2400_CLK_SOURCE_SEL        BIT(18)
 #define ASPEED_CLK_SELECTION_2 0xd8
+#define ASPEED_RESET_CTRL2     0xd4
 
 /* Globally visible clocks */
 static DEFINE_SPINLOCK(aspeed_clk_lock);
@@ -88,7 +91,7 @@ static const struct aspeed_gate_data aspeed_gates[] = {
        [ASPEED_CLK_GATE_GCLK] =        {  1,  7, "gclk-gate",          NULL,   0 }, /* 2D engine */
        [ASPEED_CLK_GATE_MCLK] =        {  2, -1, "mclk-gate",          "mpll", CLK_IS_CRITICAL }, /* SDRAM */
        [ASPEED_CLK_GATE_VCLK] =        {  3,  6, "vclk-gate",          NULL,   0 }, /* Video Capture */
-       [ASPEED_CLK_GATE_BCLK] =        {  4, 10, "bclk-gate",          "bclk", 0 }, /* PCIe/PCI */
+       [ASPEED_CLK_GATE_BCLK] =        {  4,  8, "bclk-gate",          "bclk", 0 }, /* PCIe/PCI */
        [ASPEED_CLK_GATE_DCLK] =        {  5, -1, "dclk-gate",          NULL,   0 }, /* DAC */
        [ASPEED_CLK_GATE_REFCLK] =      {  6, -1, "refclk-gate",        "clkin", CLK_IS_CRITICAL },
        [ASPEED_CLK_GATE_USBPORT2CLK] = {  7,  3, "usb-port2-gate",     NULL,   0 }, /* USB2.0 Host port 2 */
@@ -291,47 +294,72 @@ struct aspeed_reset {
 #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
 
 static const u8 aspeed_resets[] = {
+       /* SCU04 resets */
        [ASPEED_RESET_XDMA]     = 25,
        [ASPEED_RESET_MCTP]     = 24,
        [ASPEED_RESET_ADC]      = 23,
        [ASPEED_RESET_JTAG_MASTER] = 22,
        [ASPEED_RESET_MIC]      = 18,
        [ASPEED_RESET_PWM]      =  9,
-       [ASPEED_RESET_PCIVGA]   =  8,
+       [ASPEED_RESET_PECI]     = 10,
        [ASPEED_RESET_I2C]      =  2,
        [ASPEED_RESET_AHB]      =  1,
+
+       /*
+        * SCUD4 resets start at an offset to separate them from
+        * the SCU04 resets.
+        */
+       [ASPEED_RESET_CRT1]     = ASPEED_RESET2_OFFSET + 5,
 };
 
 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
                                 unsigned long id)
 {
        struct aspeed_reset *ar = to_aspeed_reset(rcdev);
-       u32 rst = BIT(aspeed_resets[id]);
+       u32 reg = ASPEED_RESET_CTRL;
+       u32 bit = aspeed_resets[id];
+
+       if (bit >= ASPEED_RESET2_OFFSET) {
+               bit -= ASPEED_RESET2_OFFSET;
+               reg = ASPEED_RESET_CTRL2;
+       }
 
-       return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0);
+       return regmap_update_bits(ar->map, reg, BIT(bit), 0);
 }
 
 static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
                               unsigned long id)
 {
        struct aspeed_reset *ar = to_aspeed_reset(rcdev);
-       u32 rst = BIT(aspeed_resets[id]);
+       u32 reg = ASPEED_RESET_CTRL;
+       u32 bit = aspeed_resets[id];
 
-       return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst);
+       if (bit >= ASPEED_RESET2_OFFSET) {
+               bit -= ASPEED_RESET2_OFFSET;
+               reg = ASPEED_RESET_CTRL2;
+       }
+
+       return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit));
 }
 
 static int aspeed_reset_status(struct reset_controller_dev *rcdev,
                               unsigned long id)
 {
        struct aspeed_reset *ar = to_aspeed_reset(rcdev);
-       u32 val, rst = BIT(aspeed_resets[id]);
-       int ret;
+       u32 reg = ASPEED_RESET_CTRL;
+       u32 bit = aspeed_resets[id];
+       int ret, val;
+
+       if (bit >= ASPEED_RESET2_OFFSET) {
+               bit -= ASPEED_RESET2_OFFSET;
+               reg = ASPEED_RESET_CTRL2;
+       }
 
-       ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val);
+       ret = regmap_read(ar->map, reg, &val);
        if (ret)
                return ret;
 
-       return !!(val & rst);
+       return !!(val & BIT(bit));
 }
 
 static const struct reset_control_ops aspeed_reset_ops = {
index f1d5967b4b39a8daeec89f47291ec9d25339832f..e68cb478f21f75e5da3557747541a0e0d13f35b7 100644 (file)
@@ -216,7 +216,7 @@ static const char * const usart1_src[] = {
        "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
 };
 
-const char * const usart234578_src[] = {
+static const char * const usart234578_src[] = {
        "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 };
 
@@ -224,10 +224,6 @@ static const char * const usart6_src[] = {
        "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 };
 
-static const char * const dfsdm_src[] = {
-       "pclk2", "ck_mcu"
-};
-
 static const char * const fdcan_src[] = {
        "ck_hse", "pll3_q", "pll4_q"
 };
@@ -316,10 +312,8 @@ struct stm32_clk_mgate {
 struct clock_config {
        u32 id;
        const char *name;
-       union {
-               const char *parent_name;
-               const char * const *parent_names;
-       };
+       const char *parent_name;
+       const char * const *parent_names;
        int num_parents;
        unsigned long flags;
        void *cfg;
@@ -469,7 +463,7 @@ static void mp1_gate_clk_disable(struct clk_hw *hw)
        }
 }
 
-const struct clk_ops mp1_gate_clk_ops = {
+static const struct clk_ops mp1_gate_clk_ops = {
        .enable         = mp1_gate_clk_enable,
        .disable        = mp1_gate_clk_disable,
        .is_enabled     = clk_gate_is_enabled,
@@ -585,14 +579,9 @@ clk_stm32_register_gate_ops(struct device *dev,
                            spinlock_t *lock)
 {
        struct clk_init_data init = { NULL };
-       struct clk_gate *gate;
        struct clk_hw *hw;
        int ret;
 
-       gate = kzalloc(sizeof(*gate), GFP_KERNEL);
-       if (!gate)
-               return ERR_PTR(-ENOMEM);
-
        init.name = name;
        init.parent_names = &parent_name;
        init.num_parents = 1;
@@ -610,10 +599,8 @@ clk_stm32_register_gate_ops(struct device *dev,
        hw->init = &init;
 
        ret = clk_hw_register(dev, hw);
-       if (ret) {
-               kfree(gate);
+       if (ret)
                hw = ERR_PTR(ret);
-       }
 
        return hw;
 }
@@ -698,7 +685,7 @@ static void mp1_mgate_clk_disable(struct clk_hw *hw)
                mp1_gate_clk_disable(hw);
 }
 
-const struct clk_ops mp1_mgate_clk_ops = {
+static const struct clk_ops mp1_mgate_clk_ops = {
        .enable         = mp1_mgate_clk_enable,
        .disable        = mp1_mgate_clk_disable,
        .is_enabled     = clk_gate_is_enabled,
@@ -732,7 +719,7 @@ static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
        return 0;
 }
 
-const struct clk_ops clk_mmux_ops = {
+static const struct clk_ops clk_mmux_ops = {
        .get_parent     = clk_mmux_get_parent,
        .set_parent     = clk_mmux_set_parent,
        .determine_rate = __clk_mux_determine_rate,
@@ -1048,10 +1035,10 @@ struct stm32_pll_cfg {
        u32 offset;
 };
 
-struct clk_hw *_clk_register_pll(struct device *dev,
-                                struct clk_hw_onecell_data *clk_data,
-                                void __iomem *base, spinlock_t *lock,
-                                const struct clock_config *cfg)
+static struct clk_hw *_clk_register_pll(struct device *dev,
+                                       struct clk_hw_onecell_data *clk_data,
+                                       void __iomem *base, spinlock_t *lock,
+                                       const struct clock_config *cfg)
 {
        struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
 
@@ -1405,7 +1392,8 @@ enum {
        G_USBH,
        G_ETHSTP,
        G_RTCAPB,
-       G_TZC,
+       G_TZC1,
+       G_TZC2,
        G_TZPC,
        G_IWDG1,
        G_BSEC,
@@ -1417,7 +1405,7 @@ enum {
        G_LAST
 };
 
-struct stm32_mgate mp1_mgate[G_LAST];
+static struct stm32_mgate mp1_mgate[G_LAST];
 
 #define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
               _mgate, _ops)\
@@ -1440,7 +1428,7 @@ struct stm32_mgate mp1_mgate[G_LAST];
               &mp1_mgate[_id], &mp1_mgate_clk_ops)
 
 /* Peripheral gates */
-struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
+static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
        /* Multi gates */
        K_GATE(G_MDIO,          RCC_APB1ENSETR, 31, 0),
        K_MGATE(G_DAC12,        RCC_APB1ENSETR, 29, 0),
@@ -1506,7 +1494,8 @@ struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
        K_GATE(G_BSEC,          RCC_APB5ENSETR, 16, 0),
        K_GATE(G_IWDG1,         RCC_APB5ENSETR, 15, 0),
        K_GATE(G_TZPC,          RCC_APB5ENSETR, 13, 0),
-       K_GATE(G_TZC,           RCC_APB5ENSETR, 12, 0),
+       K_GATE(G_TZC2,          RCC_APB5ENSETR, 12, 0),
+       K_GATE(G_TZC1,          RCC_APB5ENSETR, 11, 0),
        K_GATE(G_RTCAPB,        RCC_APB5ENSETR, 8, 0),
        K_MGATE(G_USART1,       RCC_APB5ENSETR, 4, 0),
        K_MGATE(G_I2C6,         RCC_APB5ENSETR, 3, 0),
@@ -1600,7 +1589,7 @@ enum {
        M_LAST
 };
 
-struct stm32_mmux ker_mux[M_LAST];
+static struct stm32_mmux ker_mux[M_LAST];
 
 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
        [_id] = {\
@@ -1623,7 +1612,7 @@ struct stm32_mmux ker_mux[M_LAST];
        _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
                        &ker_mux[_id], &clk_mmux_ops)
 
-const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
+static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
        /* Kernel multi mux */
        K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
        K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
@@ -1860,7 +1849,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
        PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
        PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
             CLK_IS_CRITICAL, G_RTCAPB),
-       PCLK(TZC, "tzc", "pclk5", CLK_IGNORE_UNUSED, G_TZC),
+       PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
+       PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
        PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
        PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
        PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
@@ -1916,8 +1906,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
        KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
        KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
        KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
-       KCLK(STGEN_K, "stgen_k",  stgen_src, CLK_IGNORE_UNUSED,
-            G_STGEN, M_STGEN),
+       KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
        KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
        KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
        KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
@@ -1948,8 +1937,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
        KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
        KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
        KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
-       KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI2, M_SAI3),
-       KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI2, M_SAI4),
+       KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
+       KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
        KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
        KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
        KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
@@ -1992,11 +1981,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
                  _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
 
        /* Debug clocks */
-       FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
-
-       GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
-
-       GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
+       GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
+            RCC_DBGCFGR, 8, 0),
 
        COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
                  _GATE(RCC_DBGCFGR, 9, 0),
index 077df3e539a71fef9a1ebfd98424525aeabb4885..f41d89cef0f19bff05bc03fc0c330a436ebbee6c 100644 (file)
@@ -219,8 +219,7 @@ static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
 #ifdef CONFIG_PM_SLEEP
 static int s3c24xx_dclk_suspend(struct device *dev)
 {
-       struct platform_device *pdev = to_platform_device(dev);
-       struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
+       struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
 
        s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
        return 0;
@@ -228,8 +227,7 @@ static int s3c24xx_dclk_suspend(struct device *dev)
 
 static int s3c24xx_dclk_resume(struct device *dev)
 {
-       struct platform_device *pdev = to_platform_device(dev);
-       struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
+       struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
 
        writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
        return 0;
index 3a11c382a663ed98407532b980b20cf9c3cb55bd..72714633e39c639cf84531130839b678934b6a91 100644 (file)
@@ -260,46 +260,45 @@ static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
        return 0;
 }
 
-static struct stratix10_clock_data *__socfpga_s10_clk_init(struct device_node *np,
+static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev,
                                                    int nr_clks)
 {
+       struct device_node *np = pdev->dev.of_node;
+       struct device *dev = &pdev->dev;
        struct stratix10_clock_data *clk_data;
        struct clk **clk_table;
+       struct resource *res;
        void __iomem *base;
 
-       base = of_iomap(np, 0);
-       if (!base) {
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       base = devm_ioremap_resource(dev, res);
+       if (IS_ERR(base)) {
                pr_err("%s: failed to map clock registers\n", __func__);
-               goto err;
+               return ERR_CAST(base);
        }
 
-       clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+       clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
        if (!clk_data)
-               goto err;
+               return ERR_PTR(-ENOMEM);
 
        clk_data->base = base;
-       clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
+       clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
        if (!clk_table)
-               goto err_data;
+               return ERR_PTR(-ENOMEM);
 
        clk_data->clk_data.clks = clk_table;
        clk_data->clk_data.clk_num = nr_clks;
        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
        return clk_data;
-
-err_data:
-       kfree(clk_data);
-err:
-       return NULL;
 }
 
-static int s10_clkmgr_init(struct device_node *np)
+static int s10_clkmgr_init(struct platform_device *pdev)
 {
        struct stratix10_clock_data *clk_data;
 
-       clk_data = __socfpga_s10_clk_init(np, STRATIX10_NUM_CLKS);
-       if (!clk_data)
-               return -ENOMEM;
+       clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS);
+       if (IS_ERR(clk_data))
+               return PTR_ERR(clk_data);
 
        s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
 
@@ -317,11 +316,7 @@ static int s10_clkmgr_init(struct device_node *np)
 
 static int s10_clkmgr_probe(struct platform_device *pdev)
 {
-       struct device_node *np = pdev->dev.of_node;
-
-       s10_clkmgr_init(np);
-
-       return 0;
+       return  s10_clkmgr_init(pdev);
 }
 
 static const struct of_device_id stratix10_clkmgr_match_table[] = {
@@ -334,6 +329,7 @@ static struct platform_driver stratix10_clkmgr_driver = {
        .probe          = s10_clkmgr_probe,
        .driver         = {
                .name   = "stratix10-clkmgr",
+               .suppress_bind_attrs = true,
                .of_match_table = stratix10_clkmgr_match_table,
        },
 };
index ebc78ab2df0596360858d43b35d33c99fc72da8d..4f5ff9fa11fdde223bb3600a3359a48b62559df6 100644 (file)
@@ -51,6 +51,9 @@
 #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx)                              \
        UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
 
+#define UNIPHIER_LD11_SYS_CLK_HSC(idx)                                 \
+       UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
+
 #define UNIPHIER_PRO4_SYS_CLK_GIO(idx)                                 \
        UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
 
@@ -182,6 +185,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
        /* Index 5 reserved for eMMC PHY */
        UNIPHIER_LD11_SYS_CLK_ETHER(6),
        UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC, MIO */
+       UNIPHIER_LD11_SYS_CLK_HSC(9),
        UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
        UNIPHIER_LD11_SYS_CLK_AIO(40),
        UNIPHIER_LD11_SYS_CLK_EVEA(41),
@@ -215,6 +219,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
        UNIPHIER_LD20_SYS_CLK_SD,
        UNIPHIER_LD11_SYS_CLK_ETHER(6),
        UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC */
+       UNIPHIER_LD11_SYS_CLK_HSC(9),
        /* GIO is always clock-enabled: no function for 0x210c bit5 */
        /*
         * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
index d3558d897a4d19f0fca6d254c1bea045f2a45e5f..4d01804e7c438a9a2a034e7de82b1792cadc3ff7 100644 (file)
@@ -45,8 +45,9 @@
 #define ASPEED_RESET_JTAG_MASTER       3
 #define ASPEED_RESET_MIC               4
 #define ASPEED_RESET_PWM               5
-#define ASPEED_RESET_PCIVGA            6
+#define ASPEED_RESET_PECI              6
 #define ASPEED_RESET_I2C               7
 #define ASPEED_RESET_AHB               8
+#define ASPEED_RESET_CRT1              9
 
 #endif
index 86e3ec662ef4d58391add4d1781b8a070cc82d50..90ec780bfc68622f264e7e7c7e1e030c3b83cfba 100644 (file)
@@ -76,7 +76,7 @@
 #define I2C6           63
 #define USART1         64
 #define RTCAPB         65
-#define TZC            66
+#define TZC1           66
 #define TZPC           67
 #define IWDG1          68
 #define BSEC           69
 #define CRC1           110
 #define USBH           111
 #define ETHSTP         112
+#define TZC2           113
 
 /* Kernel clocks */
 #define SDMMC1_K       118
 #define CK_MCO2                212
 
 /* TRACE & DEBUG clocks */
-#define DBG            213
 #define CK_DBG         214
 #define CK_TRACE       215