Merge branches 'clk-stm32mp1', 'clk-samsung', 'clk-uniphier-mpeg', 'clk-stratix10...
authorStephen Boyd <sboyd@kernel.org>
Mon, 4 Jun 2018 19:27:34 +0000 (12:27 -0700)
committerStephen Boyd <sboyd@kernel.org>
Mon, 4 Jun 2018 19:27:34 +0000 (12:27 -0700)
* clk-stm32mp1:
  clk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()'
  clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock
  clk: stm32mp1: remove ck_apb_dbg clock
  clk: stm32mp1: set stgen_k clock as critical
  clk: stm32mp1: add missing tzc2 clock
  clk: stm32mp1: fix SAI3 & SAI4 clocks
  clk: stm32mp1: remove unused dfsdm_src[] const
  clk: stm32mp1: add missing static

* clk-samsung:
  clk: samsung: simplify getting .drvdata

* clk-uniphier-mpeg:
  clk: uniphier: add LD11/LD20 stream demux system clock

* clk-stratix10:
  clk: socfpga: stratix10: suppress unbinding platform's clock driver
  clk: socfpga: stratix10: use platform driver APIs

* clk-aspeed:
  clk:aspeed: Fix reset bits for PCI/VGA and PECI
  clk: aspeed: Support second reset register

48 files changed:
Documentation/devicetree/bindings/clock/actions,s900-cmu.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt [new file with mode: 0644]
Documentation/devicetree/bindings/clock/qcom,gcc.txt
Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt [new file with mode: 0644]
MAINTAINERS
drivers/clk/Kconfig
drivers/clk/Makefile
drivers/clk/actions/Kconfig [new file with mode: 0644]
drivers/clk/actions/Makefile [new file with mode: 0644]
drivers/clk/actions/owl-common.c [new file with mode: 0644]
drivers/clk/actions/owl-common.h [new file with mode: 0644]
drivers/clk/actions/owl-composite.c [new file with mode: 0644]
drivers/clk/actions/owl-composite.h [new file with mode: 0644]
drivers/clk/actions/owl-divider.c [new file with mode: 0644]
drivers/clk/actions/owl-divider.h [new file with mode: 0644]
drivers/clk/actions/owl-factor.c [new file with mode: 0644]
drivers/clk/actions/owl-factor.h [new file with mode: 0644]
drivers/clk/actions/owl-fixed-factor.h [new file with mode: 0644]
drivers/clk/actions/owl-gate.c [new file with mode: 0644]
drivers/clk/actions/owl-gate.h [new file with mode: 0644]
drivers/clk/actions/owl-mux.c [new file with mode: 0644]
drivers/clk/actions/owl-mux.h [new file with mode: 0644]
drivers/clk/actions/owl-pll.c [new file with mode: 0644]
drivers/clk/actions/owl-pll.h [new file with mode: 0644]
drivers/clk/actions/owl-s900.c [new file with mode: 0644]
drivers/clk/clk-aspeed.c
drivers/clk/clk-npcm7xx.c [new file with mode: 0644]
drivers/clk/clk-stm32mp1.c
drivers/clk/clk.c
drivers/clk/qcom/Kconfig
drivers/clk/qcom/Makefile
drivers/clk/qcom/clk-rcg2.c
drivers/clk/qcom/gcc-msm8998.c [new file with mode: 0644]
drivers/clk/samsung/clk-s3c2410-dclk.c
drivers/clk/socfpga/clk-s10.c
drivers/clk/spear/spear6xx_clock.c
drivers/clocksource/timer-sp804.c
drivers/pinctrl/sunxi/pinctrl-sunxi.c
drivers/soc/rockchip/pm_domains.c
drivers/soc/tegra/pmc.c
include/dt-bindings/clock/actions,s900-cmu.h [new file with mode: 0644]
include/dt-bindings/clock/aspeed-clock.h
include/dt-bindings/clock/nuvoton,npcm7xx-clock.h [new file with mode: 0644]
include/dt-bindings/clock/qcom,gcc-msm8998.h [new file with mode: 0644]
include/dt-bindings/clock/qcom,rpmh.h [new file with mode: 0644]
include/dt-bindings/clock/stm32mp1-clks.h
include/linux/clk-provider.h
include/linux/of_clk.h [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
new file mode 100644 (file)
index 0000000..93e4fb8
--- /dev/null
@@ -0,0 +1,47 @@
+* Actions S900 Clock Management Unit (CMU)
+
+The Actions S900 clock management unit generates and supplies clock to various
+controllers within the SoC. The clock binding described here is applicable to
+S900 SoC.
+
+Required Properties:
+
+- compatible: should be "actions,s900-cmu"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- clocks: Reference to the parent clocks ("hosc", "losc")
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier, and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/actions,s900-cmu.h header and can be used in device
+tree sources.
+
+External clocks:
+
+The hosc clock used as input for the plls is generated outside the SoC. It is
+expected that it is defined using standard clock bindings as "hosc".
+
+Actions S900 CMU also requires one more clock:
+ - "losc" - internal low frequency oscillator
+
+Example: Clock Management Unit node:
+
+        cmu: clock-controller@e0160000 {
+                compatible = "actions,s900-cmu";
+                reg = <0x0 0xe0160000 0x0 0x1000>;
+                clocks = <&hosc>, <&losc>;
+                #clock-cells = <1>;
+        };
+
+Example: UART controller node that consumes clock generated by the clock
+management unit:
+
+        uart: serial@e012a000 {
+                compatible = "actions,s900-uart", "actions,owl-uart";
+                reg = <0x0 0xe012a000 0x0 0x2000>;
+                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cmu CLK_UART5>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt
new file mode 100644 (file)
index 0000000..f820645
--- /dev/null
@@ -0,0 +1,100 @@
+* Nuvoton NPCM7XX Clock Controller
+
+Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
+generates and supplies clocks to all modules within the BMC.
+
+External clocks:
+
+There are six fixed clocks that are generated outside the BMC. All clocks are of
+a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
+clk_sysbypck are inputs to the clock controller.
+clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
+network. They are set on the device tree, but not used by the clock module. The
+network devices use them directly.
+Example can be found below.
+
+All available clocks are defined as preprocessor macros in:
+dt-bindings/clock/nuvoton,npcm7xx-clock.h
+and can be reused as DT sources.
+
+Required Properties of clock controller:
+
+       - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
+                 Poleg BMC NPCM750
+
+       - reg: physical base address of the clock controller and length of
+               memory mapped region.
+
+       - #clock-cells: should be 1.
+
+Example: Clock controller node:
+
+       clk: clock-controller@f0801000 {
+               compatible = "nuvoton,npcm750-clk";
+               #clock-cells = <1>;
+               reg = <0xf0801000 0x1000>;
+               clock-names = "refclk", "sysbypck", "mcbypck";
+               clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
+       };
+
+Example: Required external clocks for network:
+
+       /* external reference clock */
+       clk_refclk: clk-refclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <25000000>;
+               clock-output-names = "refclk";
+       };
+
+       /* external reference clock for cpu. float in normal operation */
+       clk_sysbypck: clk-sysbypck {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <800000000>;
+               clock-output-names = "sysbypck";
+       };
+
+       /* external reference clock for MC. float in normal operation */
+       clk_mcbypck: clk-mcbypck {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <800000000>;
+               clock-output-names = "mcbypck";
+       };
+
+        /* external clock signal rg1refck, supplied by the phy */
+       clk_rg1refck: clk-rg1refck {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <125000000>;
+               clock-output-names = "clk_rg1refck";
+       };
+
+        /* external clock signal rg2refck, supplied by the phy */
+       clk_rg2refck: clk-rg2refck {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <125000000>;
+               clock-output-names = "clk_rg2refck";
+       };
+
+       clk_xin: clk-xin {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <50000000>;
+               clock-output-names = "clk_xin";
+       };
+
+
+Example: GMAC controller node that consumes two clocks: a generated clk by the
+clock controller and a fixed clock from DT (clk_rg1refck).
+
+       ethernet0: ethernet@f0802000 {
+               compatible = "snps,dwmac";
+               reg = <0xf0802000 0x2000>;
+               interrupts = <0 14 4>;
+               interrupt-names = "macirq";
+               clocks  = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
+               clock-names = "stmmaceth", "clk_gmac";
+       };
index 551d03be966587fe27d9f486c0f5b712a9f6f016..d1fb8b213ddeebae2b4ea332f258e65868bd9db5 100644 (file)
@@ -17,6 +17,7 @@ Required properties :
                        "qcom,gcc-msm8974pro-ac"
                        "qcom,gcc-msm8994"
                        "qcom,gcc-msm8996"
+                       "qcom,gcc-msm8998"
                        "qcom,gcc-mdm9615"
 
 - reg : shall contain base register location and length
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
new file mode 100644 (file)
index 0000000..3c00765
--- /dev/null
@@ -0,0 +1,22 @@
+Qualcomm Technologies, Inc. RPMh Clocks
+-------------------------------------------------------
+
+Resource Power Manager Hardened (RPMh) manages shared resources on
+some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
+other hardware subsystems via RSC to control clocks.
+
+Required properties :
+- compatible : shall contain "qcom,sdm845-rpmh-clk"
+
+- #clock-cells : must contain 1
+
+Example :
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+
+       &apps_rsc {
+               rpmhcc: clock-controller {
+                       compatible = "qcom,sdm845-rpmh-clk";
+                       #clock-cells = <1>;
+               };
+       };
index 0a1410d5a621835ded529ac2d6ade31c306e086f..b61b2bf1eb75d7db4fb69258c721c83a74cae793 100644 (file)
@@ -3556,6 +3556,7 @@ F:        drivers/clk/
 X:     drivers/clk/clkdev.c
 F:     include/linux/clk-pr*
 F:     include/linux/clk/
+F:     include/linux/of_clk.h
 
 COMMON INTERNET FILE SYSTEM (CIFS)
 M:     Steve French <sfrench@samba.org>
index 41492e980ef4c0deb4fd6f62020d76137c912b42..24a5bc3a2ddbf06921c84aa1a7edc38de2d7142b 100644 (file)
@@ -279,6 +279,7 @@ config COMMON_CLK_STM32H7
        ---help---
          Support for stm32h7 SoC family clocks
 
+source "drivers/clk/actions/Kconfig"
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/imgtec/Kconfig"
index de6d06ac790b63eb90b6d2b04077750fd985d64c..ae40cbe770f059d0ca1aded1dc7fc3530b3153df 100644 (file)
@@ -33,6 +33,7 @@ obj-$(CONFIG_CLK_HSDK)                        += clk-hsdk-pll.o
 obj-$(CONFIG_COMMON_CLK_MAX77686)      += clk-max77686.o
 obj-$(CONFIG_ARCH_MOXART)              += clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK)             += clk-nomadik.o
+obj-$(CONFIG_ARCH_NPCM7XX)             += clk-npcm7xx.o
 obj-$(CONFIG_ARCH_NSPIRE)              += clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_OXNAS)         += clk-oxnas.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)                += clk-palmas.o
@@ -59,6 +60,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X)               += clk-wm831x.o
 obj-$(CONFIG_COMMON_CLK_XGENE)         += clk-xgene.o
 
 # please keep this section sorted lexicographically by directory path name
+obj-y                                  += actions/
 obj-$(CONFIG_COMMON_CLK_AT91)          += at91/
 obj-$(CONFIG_ARCH_ARTPEC)              += axis/
 obj-$(CONFIG_ARC_PLAT_AXS10X)          += axs10x/
diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig
new file mode 100644 (file)
index 0000000..8854adb
--- /dev/null
@@ -0,0 +1,14 @@
+config CLK_ACTIONS
+       bool "Clock driver for Actions Semi SoCs"
+       depends on ARCH_ACTIONS || COMPILE_TEST
+       default ARCH_ACTIONS
+
+if CLK_ACTIONS
+
+# SoC Drivers
+
+config CLK_OWL_S900
+       bool "Support for the Actions Semi OWL S900 clocks"
+       depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
+       default ARM64 && ARCH_ACTIONS
+endif
diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
new file mode 100644 (file)
index 0000000..76e4314
--- /dev/null
@@ -0,0 +1,12 @@
+obj-$(CONFIG_CLK_ACTIONS)      += clk-owl.o
+
+clk-owl-y                      += owl-common.o
+clk-owl-y                      += owl-gate.o
+clk-owl-y                      += owl-mux.o
+clk-owl-y                      += owl-divider.o
+clk-owl-y                      += owl-factor.o
+clk-owl-y                      += owl-composite.o
+clk-owl-y                      += owl-pll.o
+
+# SoC support
+obj-$(CONFIG_CLK_OWL_S900)     += owl-s900.o
diff --git a/drivers/clk/actions/owl-common.c b/drivers/clk/actions/owl-common.c
new file mode 100644 (file)
index 0000000..61c1071
--- /dev/null
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL common clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "owl-common.h"
+
+static const struct regmap_config owl_regmap_config = {
+       .reg_bits       = 32,
+       .reg_stride     = 4,
+       .val_bits       = 32,
+       .max_register   = 0x00cc,
+       .fast_io        = true,
+};
+
+static void owl_clk_set_regmap(const struct owl_clk_desc *desc,
+                        struct regmap *regmap)
+{
+       int i;
+       struct owl_clk_common *clks;
+
+       for (i = 0; i < desc->num_clks; i++) {
+               clks = desc->clks[i];
+               if (!clks)
+                       continue;
+
+               clks->regmap = regmap;
+       }
+}
+
+int owl_clk_regmap_init(struct platform_device *pdev,
+                        const struct owl_clk_desc *desc)
+{
+       void __iomem *base;
+       struct regmap *regmap;
+       struct resource *res;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       base = devm_ioremap_resource(&pdev->dev, res);
+       if (IS_ERR(base))
+               return PTR_ERR(base);
+
+       regmap = devm_regmap_init_mmio(&pdev->dev, base, &owl_regmap_config);
+       if (IS_ERR(regmap)) {
+               pr_err("failed to init regmap\n");
+               return PTR_ERR(regmap);
+       }
+
+       owl_clk_set_regmap(desc, regmap);
+
+       return 0;
+}
+
+int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks)
+{
+       int i, ret;
+       struct clk_hw *hw;
+
+       for (i = 0; i < hw_clks->num; i++) {
+
+               hw = hw_clks->hws[i];
+
+               if (IS_ERR_OR_NULL(hw))
+                       continue;
+
+               ret = devm_clk_hw_register(dev, hw);
+               if (ret) {
+                       dev_err(dev, "Couldn't register clock %d - %s\n",
+                               i, hw->init->name);
+                       return ret;
+               }
+       }
+
+       ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_clks);
+       if (ret)
+               dev_err(dev, "Failed to add clock provider\n");
+
+       return ret;
+}
diff --git a/drivers/clk/actions/owl-common.h b/drivers/clk/actions/owl-common.h
new file mode 100644 (file)
index 0000000..4fd726e
--- /dev/null
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL common clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_COMMON_H_
+#define _OWL_COMMON_H_
+
+#include <linux/clk-provider.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+
+struct device_node;
+
+struct owl_clk_common {
+       struct regmap                   *regmap;
+       struct clk_hw                   hw;
+};
+
+struct owl_clk_desc {
+       struct owl_clk_common           **clks;
+       unsigned long                   num_clks;
+       struct clk_hw_onecell_data      *hw_clks;
+};
+
+static inline struct owl_clk_common *
+       hw_to_owl_clk_common(const struct clk_hw *hw)
+{
+       return container_of(hw, struct owl_clk_common, hw);
+}
+
+int owl_clk_regmap_init(struct platform_device *pdev,
+                        const struct owl_clk_desc *desc);
+int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks);
+
+#endif /* _OWL_COMMON_H_ */
diff --git a/drivers/clk/actions/owl-composite.c b/drivers/clk/actions/owl-composite.c
new file mode 100644 (file)
index 0000000..101706e
--- /dev/null
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL composite clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "owl-composite.h"
+
+static u8 owl_comp_get_parent(struct clk_hw *hw)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+
+       return owl_mux_helper_get_parent(&comp->common, &comp->mux_hw);
+}
+
+static int owl_comp_set_parent(struct clk_hw *hw, u8 index)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+
+       return owl_mux_helper_set_parent(&comp->common, &comp->mux_hw, index);
+}
+
+static void owl_comp_disable(struct clk_hw *hw)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+       struct owl_clk_common *common = &comp->common;
+
+       owl_gate_set(common, &comp->gate_hw, false);
+}
+
+static int owl_comp_enable(struct clk_hw *hw)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+       struct owl_clk_common *common = &comp->common;
+
+       owl_gate_set(common, &comp->gate_hw, true);
+
+       return 0;
+}
+
+static int owl_comp_is_enabled(struct clk_hw *hw)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+       struct owl_clk_common *common = &comp->common;
+
+       return owl_gate_clk_is_enabled(common, &comp->gate_hw);
+}
+
+static long owl_comp_div_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *parent_rate)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+
+       return owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
+                                       rate, parent_rate);
+}
+
+static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+
+       return owl_divider_helper_recalc_rate(&comp->common, &comp->rate.div_hw,
+                                       parent_rate);
+}
+
+static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long parent_rate)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+
+       return owl_divider_helper_set_rate(&comp->common, &comp->rate.div_hw,
+                                       rate, parent_rate);
+}
+
+static long owl_comp_fact_round_rate(struct clk_hw *hw, unsigned long rate,
+                       unsigned long *parent_rate)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+
+       return owl_factor_helper_round_rate(&comp->common,
+                                       &comp->rate.factor_hw,
+                                       rate, parent_rate);
+}
+
+static unsigned long owl_comp_fact_recalc_rate(struct clk_hw *hw,
+                       unsigned long parent_rate)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+
+       return owl_factor_helper_recalc_rate(&comp->common,
+                                       &comp->rate.factor_hw,
+                                       parent_rate);
+}
+
+static int owl_comp_fact_set_rate(struct clk_hw *hw, unsigned long rate,
+                       unsigned long parent_rate)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+
+       return owl_factor_helper_set_rate(&comp->common,
+                                       &comp->rate.factor_hw,
+                                       rate, parent_rate);
+}
+
+static long owl_comp_fix_fact_round_rate(struct clk_hw *hw, unsigned long rate,
+                       unsigned long *parent_rate)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+       struct clk_fixed_factor *fix_fact_hw = &comp->rate.fix_fact_hw;
+
+       return comp->fix_fact_ops->round_rate(&fix_fact_hw->hw, rate, parent_rate);
+}
+
+static unsigned long owl_comp_fix_fact_recalc_rate(struct clk_hw *hw,
+                       unsigned long parent_rate)
+{
+       struct owl_composite *comp = hw_to_owl_comp(hw);
+       struct clk_fixed_factor *fix_fact_hw = &comp->rate.fix_fact_hw;
+
+       return comp->fix_fact_ops->recalc_rate(&fix_fact_hw->hw, parent_rate);
+
+}
+
+static int owl_comp_fix_fact_set_rate(struct clk_hw *hw, unsigned long rate,
+                       unsigned long parent_rate)
+{
+       /*
+        * We must report success but we can do so unconditionally because
+        * owl_comp_fix_fact_round_rate returns values that ensure this call is
+        * a nop.
+        */
+
+       return 0;
+}
+
+const struct clk_ops owl_comp_div_ops = {
+       /* mux_ops */
+       .get_parent     = owl_comp_get_parent,
+       .set_parent     = owl_comp_set_parent,
+
+       /* gate_ops */
+       .disable        = owl_comp_disable,
+       .enable         = owl_comp_enable,
+       .is_enabled     = owl_comp_is_enabled,
+
+       /* div_ops */
+       .round_rate     = owl_comp_div_round_rate,
+       .recalc_rate    = owl_comp_div_recalc_rate,
+       .set_rate       = owl_comp_div_set_rate,
+};
+
+
+const struct clk_ops owl_comp_fact_ops = {
+       /* mux_ops */
+       .get_parent     = owl_comp_get_parent,
+       .set_parent     = owl_comp_set_parent,
+
+       /* gate_ops */
+       .disable        = owl_comp_disable,
+       .enable         = owl_comp_enable,
+       .is_enabled     = owl_comp_is_enabled,
+
+       /* fact_ops */
+       .round_rate     = owl_comp_fact_round_rate,
+       .recalc_rate    = owl_comp_fact_recalc_rate,
+       .set_rate       = owl_comp_fact_set_rate,
+};
+
+const struct clk_ops owl_comp_fix_fact_ops = {
+       /* gate_ops */
+       .disable        = owl_comp_disable,
+       .enable         = owl_comp_enable,
+       .is_enabled     = owl_comp_is_enabled,
+
+       /* fix_fact_ops */
+       .round_rate     = owl_comp_fix_fact_round_rate,
+       .recalc_rate    = owl_comp_fix_fact_recalc_rate,
+       .set_rate       = owl_comp_fix_fact_set_rate,
+};
+
+
+const struct clk_ops owl_comp_pass_ops = {
+       /* mux_ops */
+       .get_parent     = owl_comp_get_parent,
+       .set_parent     = owl_comp_set_parent,
+
+       /* gate_ops */
+       .disable        = owl_comp_disable,
+       .enable         = owl_comp_enable,
+       .is_enabled     = owl_comp_is_enabled,
+};
diff --git a/drivers/clk/actions/owl-composite.h b/drivers/clk/actions/owl-composite.h
new file mode 100644 (file)
index 0000000..b410ed5
--- /dev/null
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL composite clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_COMPOSITE_H_
+#define _OWL_COMPOSITE_H_
+
+#include "owl-common.h"
+#include "owl-mux.h"
+#include "owl-gate.h"
+#include "owl-factor.h"
+#include "owl-fixed-factor.h"
+#include "owl-divider.h"
+
+union owl_rate {
+       struct owl_divider_hw   div_hw;
+       struct owl_factor_hw    factor_hw;
+       struct clk_fixed_factor fix_fact_hw;
+};
+
+struct owl_composite {
+       struct owl_mux_hw       mux_hw;
+       struct owl_gate_hw      gate_hw;
+       union owl_rate          rate;
+
+       const struct clk_ops    *fix_fact_ops;
+
+       struct owl_clk_common   common;
+};
+
+#define OWL_COMP_DIV(_struct, _name, _parent,                          \
+                    _mux, _gate, _div, _flags)                         \
+       struct owl_composite _struct = {                                \
+               .mux_hw         = _mux,                                 \
+               .gate_hw        = _gate,                                \
+               .rate.div_hw    = _div,                                 \
+               .common = {                                             \
+                       .regmap         = NULL,                         \
+                       .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
+                                                    _parent,           \
+                                                     &owl_comp_div_ops,\
+                                                    _flags),           \
+               },                                                      \
+       }
+
+#define OWL_COMP_DIV_FIXED(_struct, _name, _parent,                    \
+                    _gate, _div, _flags)                               \
+       struct owl_composite _struct = {                                \
+               .gate_hw        = _gate,                                \
+               .rate.div_hw    = _div,                                 \
+               .common = {                                             \
+                       .regmap         = NULL,                         \
+                       .hw.init        = CLK_HW_INIT(_name,            \
+                                                    _parent,           \
+                                                     &owl_comp_div_ops,\
+                                                    _flags),           \
+               },                                                      \
+       }
+
+#define OWL_COMP_FACTOR(_struct, _name, _parent,                       \
+                       _mux, _gate, _factor, _flags)                   \
+       struct owl_composite _struct = {                                \
+               .mux_hw         = _mux,                                 \
+               .gate_hw        = _gate,                                \
+               .rate.factor_hw = _factor,                              \
+               .common = {                                             \
+                       .regmap         = NULL,                         \
+                       .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
+                                                    _parent,           \
+                                                    &owl_comp_fact_ops,\
+                                                    _flags),           \
+               },                                                      \
+       }
+
+#define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent,                 \
+                       _gate, _mul, _div, _flags)                      \
+       struct owl_composite _struct = {                                \
+               .gate_hw                = _gate,                        \
+               .rate.fix_fact_hw.mult  = _mul,                         \
+               .rate.fix_fact_hw.div   = _div,                         \
+               .fix_fact_ops           = &clk_fixed_factor_ops,        \
+               .common = {                                             \
+                       .regmap         = NULL,                         \
+                       .hw.init        = CLK_HW_INIT(_name,            \
+                                                _parent,               \
+                                                &owl_comp_fix_fact_ops,\
+                                                _flags),               \
+               },                                                      \
+       }
+
+#define OWL_COMP_PASS(_struct, _name, _parent,                         \
+                     _mux, _gate, _flags)                              \
+       struct owl_composite _struct = {                                \
+               .mux_hw         = _mux,                                 \
+               .gate_hw        = _gate,                                \
+               .common = {                                             \
+                       .regmap         = NULL,                         \
+                       .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
+                                                    _parent,           \
+                                                    &owl_comp_pass_ops,\
+                                                    _flags),           \
+               },                                                      \
+       }
+
+static inline struct owl_composite *hw_to_owl_comp(const struct clk_hw *hw)
+{
+       struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+       return container_of(common, struct owl_composite, common);
+}
+
+extern const struct clk_ops owl_comp_div_ops;
+extern const struct clk_ops owl_comp_fact_ops;
+extern const struct clk_ops owl_comp_fix_fact_ops;
+extern const struct clk_ops owl_comp_pass_ops;
+extern const struct clk_ops clk_fixed_factor_ops;
+
+#endif /* _OWL_COMPOSITE_H_ */
diff --git a/drivers/clk/actions/owl-divider.c b/drivers/clk/actions/owl-divider.c
new file mode 100644 (file)
index 0000000..cddac00
--- /dev/null
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL divider clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "owl-divider.h"
+
+long owl_divider_helper_round_rate(struct owl_clk_common *common,
+                               const struct owl_divider_hw *div_hw,
+                               unsigned long rate,
+                               unsigned long *parent_rate)
+{
+       return divider_round_rate(&common->hw, rate, parent_rate,
+                                 div_hw->table, div_hw->width,
+                                 div_hw->div_flags);
+}
+
+static long owl_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *parent_rate)
+{
+       struct owl_divider *div = hw_to_owl_divider(hw);
+
+       return owl_divider_helper_round_rate(&div->common, &div->div_hw,
+                                            rate, parent_rate);
+}
+
+unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
+                                        const struct owl_divider_hw *div_hw,
+                                        unsigned long parent_rate)
+{
+       unsigned long val;
+       unsigned int reg;
+
+       regmap_read(common->regmap, div_hw->reg, &reg);
+       val = reg >> div_hw->shift;
+       val &= (1 << div_hw->width) - 1;
+
+       return divider_recalc_rate(&common->hw, parent_rate,
+                                  val, div_hw->table,
+                                  div_hw->div_flags,
+                                  div_hw->width);
+}
+
+static unsigned long owl_divider_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+       struct owl_divider *div = hw_to_owl_divider(hw);
+
+       return owl_divider_helper_recalc_rate(&div->common,
+                                             &div->div_hw, parent_rate);
+}
+
+int owl_divider_helper_set_rate(const struct owl_clk_common *common,
+                               const struct owl_divider_hw *div_hw,
+                               unsigned long rate,
+                               unsigned long parent_rate)
+{
+       unsigned long val;
+       unsigned int reg;
+
+       val = divider_get_val(rate, parent_rate, div_hw->table,
+                             div_hw->width, 0);
+
+       regmap_read(common->regmap, div_hw->reg, &reg);
+       reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift);
+
+       regmap_write(common->regmap, div_hw->reg,
+                         reg | (val << div_hw->shift));
+
+       return 0;
+}
+
+static int owl_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long parent_rate)
+{
+       struct owl_divider *div = hw_to_owl_divider(hw);
+
+       return owl_divider_helper_set_rate(&div->common, &div->div_hw,
+                                       rate, parent_rate);
+}
+
+const struct clk_ops owl_divider_ops = {
+       .recalc_rate = owl_divider_recalc_rate,
+       .round_rate = owl_divider_round_rate,
+       .set_rate = owl_divider_set_rate,
+};
diff --git a/drivers/clk/actions/owl-divider.h b/drivers/clk/actions/owl-divider.h
new file mode 100644 (file)
index 0000000..92d3e3d
--- /dev/null
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL divider clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_DIVIDER_H_
+#define _OWL_DIVIDER_H_
+
+#include "owl-common.h"
+
+struct owl_divider_hw {
+       u32                     reg;
+       u8                      shift;
+       u8                      width;
+       u8                      div_flags;
+       struct clk_div_table    *table;
+};
+
+struct owl_divider {
+       struct owl_divider_hw   div_hw;
+       struct owl_clk_common   common;
+};
+
+#define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table)       \
+       {                                                               \
+               .reg            = _reg,                                 \
+               .shift          = _shift,                               \
+               .width          = _width,                               \
+               .div_flags      = _div_flags,                           \
+               .table          = _table,                               \
+       }
+
+#define OWL_DIVIDER(_struct, _name, _parent, _reg,                     \
+                   _shift, _width, _table, _div_flags, _flags)         \
+       struct owl_divider _struct = {                                  \
+               .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width,          \
+                                        _div_flags, _table),           \
+               .common = {                                             \
+                       .regmap         = NULL,                         \
+                       .hw.init        = CLK_HW_INIT(_name,            \
+                                                     _parent,          \
+                                                     &owl_divider_ops, \
+                                                     _flags),          \
+               },                                                      \
+       }
+
+static inline struct owl_divider *hw_to_owl_divider(const struct clk_hw *hw)
+{
+       struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+       return container_of(common, struct owl_divider, common);
+}
+
+long owl_divider_helper_round_rate(struct owl_clk_common *common,
+                               const struct owl_divider_hw *div_hw,
+                               unsigned long rate,
+                               unsigned long *parent_rate);
+
+unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
+                                        const struct owl_divider_hw *div_hw,
+                                        unsigned long parent_rate);
+
+int owl_divider_helper_set_rate(const struct owl_clk_common *common,
+                               const struct owl_divider_hw *div_hw,
+                               unsigned long rate,
+                               unsigned long parent_rate);
+
+extern const struct clk_ops owl_divider_ops;
+
+#endif /* _OWL_DIVIDER_H_ */
diff --git a/drivers/clk/actions/owl-factor.c b/drivers/clk/actions/owl-factor.c
new file mode 100644 (file)
index 0000000..317d4a9
--- /dev/null
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL factor clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "owl-factor.h"
+
+static unsigned int _get_table_maxval(const struct clk_factor_table *table)
+{
+       unsigned int maxval = 0;
+       const struct clk_factor_table *clkt;
+
+       for (clkt = table; clkt->div; clkt++)
+               if (clkt->val > maxval)
+                       maxval = clkt->val;
+       return maxval;
+}
+
+static int _get_table_div_mul(const struct clk_factor_table *table,
+                       unsigned int val, unsigned int *mul, unsigned int *div)
+{
+       const struct clk_factor_table *clkt;
+
+       for (clkt = table; clkt->div; clkt++) {
+               if (clkt->val == val) {
+                       *mul = clkt->mul;
+                       *div = clkt->div;
+                       return 1;
+               }
+       }
+
+       return 0;
+}
+
+static unsigned int _get_table_val(const struct clk_factor_table *table,
+                       unsigned long rate, unsigned long parent_rate)
+{
+       const struct clk_factor_table *clkt;
+       int val = -1;
+       u64 calc_rate;
+
+       for (clkt = table; clkt->div; clkt++) {
+               calc_rate = parent_rate * clkt->mul;
+               do_div(calc_rate, clkt->div);
+
+               if ((unsigned long)calc_rate <= rate) {
+                       val = clkt->val;
+                       break;
+               }
+       }
+
+       if (val == -1)
+               val = _get_table_maxval(table);
+
+       return val;
+}
+
+static int clk_val_best(struct clk_hw *hw, unsigned long rate,
+                       unsigned long *best_parent_rate)
+{
+       struct owl_factor *factor = hw_to_owl_factor(hw);
+       struct owl_factor_hw *factor_hw = &factor->factor_hw;
+       const struct clk_factor_table *clkt = factor_hw->table;
+       unsigned long parent_rate, try_parent_rate, best = 0, cur_rate;
+       unsigned long parent_rate_saved = *best_parent_rate;
+       int bestval = 0;
+
+       if (!rate)
+               rate = 1;
+
+       if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+               parent_rate = *best_parent_rate;
+               bestval = _get_table_val(clkt, rate, parent_rate);
+               return bestval;
+       }
+
+       for (clkt = factor_hw->table; clkt->div; clkt++) {
+               try_parent_rate = rate * clkt->div / clkt->mul;
+
+               if (try_parent_rate == parent_rate_saved) {
+                       pr_debug("%s: [%d %d %d] found try_parent_rate %ld\n",
+                               __func__, clkt->val, clkt->mul, clkt->div,
+                               try_parent_rate);
+                       /*
+                        * It's the most ideal case if the requested rate can be
+                        * divided from parent clock without any need to change
+                        * parent rate, so return the divider immediately.
+                        */
+                       *best_parent_rate = parent_rate_saved;
+                       return clkt->val;
+               }
+
+               parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
+                               try_parent_rate);
+               cur_rate = DIV_ROUND_UP(parent_rate, clkt->div) * clkt->mul;
+               if (cur_rate <= rate && cur_rate > best) {
+                       bestval = clkt->val;
+                       best = cur_rate;
+                       *best_parent_rate = parent_rate;
+               }
+       }
+
+       if (!bestval) {
+               bestval = _get_table_maxval(clkt);
+               *best_parent_rate = clk_hw_round_rate(
+                               clk_hw_get_parent(hw), 1);
+       }
+
+       return bestval;
+}
+
+long owl_factor_helper_round_rate(struct owl_clk_common *common,
+                               const struct owl_factor_hw *factor_hw,
+                               unsigned long rate,
+                               unsigned long *parent_rate)
+{
+       const struct clk_factor_table *clkt = factor_hw->table;
+       unsigned int val, mul = 0, div = 1;
+
+       val = clk_val_best(&common->hw, rate, parent_rate);
+       _get_table_div_mul(clkt, val, &mul, &div);
+
+       return *parent_rate * mul / div;
+}
+
+static long owl_factor_round_rate(struct clk_hw *hw, unsigned long rate,
+                       unsigned long *parent_rate)
+{
+       struct owl_factor *factor = hw_to_owl_factor(hw);
+       struct owl_factor_hw *factor_hw = &factor->factor_hw;
+
+       return owl_factor_helper_round_rate(&factor->common, factor_hw,
+                                       rate, parent_rate);
+}
+
+unsigned long owl_factor_helper_recalc_rate(struct owl_clk_common *common,
+                                        const struct owl_factor_hw *factor_hw,
+                                        unsigned long parent_rate)
+{
+       const struct clk_factor_table *clkt = factor_hw->table;
+       unsigned long long int rate;
+       u32 reg, val, mul, div;
+
+       div = 0;
+       mul = 0;
+
+       regmap_read(common->regmap, factor_hw->reg, &reg);
+
+       val = reg >> factor_hw->shift;
+       val &= div_mask(factor_hw);
+
+       _get_table_div_mul(clkt, val, &mul, &div);
+       if (!div) {
+               WARN(!(factor_hw->fct_flags & CLK_DIVIDER_ALLOW_ZERO),
+                       "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
+                       __clk_get_name(common->hw.clk));
+               return parent_rate;
+       }
+
+       rate = (unsigned long long int)parent_rate * mul;
+       do_div(rate, div);
+
+       return rate;
+}
+
+static unsigned long owl_factor_recalc_rate(struct clk_hw *hw,
+                       unsigned long parent_rate)
+{
+       struct owl_factor *factor = hw_to_owl_factor(hw);
+       struct owl_factor_hw *factor_hw = &factor->factor_hw;
+       struct owl_clk_common *common = &factor->common;
+
+       return owl_factor_helper_recalc_rate(common, factor_hw, parent_rate);
+}
+
+int owl_factor_helper_set_rate(const struct owl_clk_common *common,
+                               const struct owl_factor_hw *factor_hw,
+                               unsigned long rate,
+                               unsigned long parent_rate)
+{
+       u32 val, reg;
+
+       val = _get_table_val(factor_hw->table, rate, parent_rate);
+
+       if (val > div_mask(factor_hw))
+               val = div_mask(factor_hw);
+
+       regmap_read(common->regmap, factor_hw->reg, &reg);
+
+       reg &= ~(div_mask(factor_hw) << factor_hw->shift);
+       reg |= val << factor_hw->shift;
+
+       regmap_write(common->regmap, factor_hw->reg, reg);
+
+       return 0;
+}
+
+static int owl_factor_set_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long parent_rate)
+{
+       struct owl_factor *factor = hw_to_owl_factor(hw);
+       struct owl_factor_hw *factor_hw = &factor->factor_hw;
+       struct owl_clk_common *common = &factor->common;
+
+       return owl_factor_helper_set_rate(common, factor_hw,
+                                       rate, parent_rate);
+}
+
+const struct clk_ops owl_factor_ops = {
+       .round_rate     = owl_factor_round_rate,
+       .recalc_rate    = owl_factor_recalc_rate,
+       .set_rate       = owl_factor_set_rate,
+};
diff --git a/drivers/clk/actions/owl-factor.h b/drivers/clk/actions/owl-factor.h
new file mode 100644 (file)
index 0000000..f1a7ffe
--- /dev/null
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL factor clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_FACTOR_H_
+#define _OWL_FACTOR_H_
+
+#include "owl-common.h"
+
+struct clk_factor_table {
+       unsigned int            val;
+       unsigned int            mul;
+       unsigned int            div;
+};
+
+struct owl_factor_hw {
+       u32                     reg;
+       u8                      shift;
+       u8                      width;
+       u8                      fct_flags;
+       struct clk_factor_table *table;
+};
+
+struct owl_factor {
+       struct owl_factor_hw    factor_hw;
+       struct owl_clk_common   common;
+};
+
+#define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table)                \
+       {                                                               \
+               .reg            = _reg,                                 \
+               .shift          = _shift,                               \
+               .width          = _width,                               \
+               .fct_flags      = _fct_flags,                           \
+               .table          = _table,                               \
+       }
+
+#define OWL_FACTOR(_struct, _name, _parent, _reg,                      \
+                  _shift, _width, _table, _fct_flags, _flags)          \
+       struct owl_factor _struct = {                                   \
+               .factor_hw = OWL_FACTOR_HW(_reg, _shift,                \
+                                          _width, _fct_flags, _table), \
+               .common = {                                             \
+                       .regmap         = NULL,                         \
+                       .hw.init        = CLK_HW_INIT(_name,            \
+                                                     _parent,          \
+                                                     &owl_factor_ops,  \
+                                                     _flags),          \
+               },                                                      \
+       }
+
+#define div_mask(d) ((1 << ((d)->width)) - 1)
+
+static inline struct owl_factor *hw_to_owl_factor(const struct clk_hw *hw)
+{
+       struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+       return container_of(common, struct owl_factor, common);
+}
+
+long owl_factor_helper_round_rate(struct owl_clk_common *common,
+                               const struct owl_factor_hw *factor_hw,
+                               unsigned long rate,
+                               unsigned long *parent_rate);
+
+unsigned long owl_factor_helper_recalc_rate(struct owl_clk_common *common,
+                                        const struct owl_factor_hw *factor_hw,
+                                        unsigned long parent_rate);
+
+int owl_factor_helper_set_rate(const struct owl_clk_common *common,
+                               const struct owl_factor_hw *factor_hw,
+                               unsigned long rate,
+                               unsigned long parent_rate);
+
+extern const struct clk_ops owl_factor_ops;
+
+#endif /* _OWL_FACTOR_H_ */
diff --git a/drivers/clk/actions/owl-fixed-factor.h b/drivers/clk/actions/owl-fixed-factor.h
new file mode 100644 (file)
index 0000000..cc9fe36
--- /dev/null
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL fixed factor clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_FIXED_FACTOR_H_
+#define _OWL_FIXED_FACTOR_H_
+
+#include "owl-common.h"
+
+#define OWL_FIX_FACT(_struct, _name, _parent, _mul, _div, _flags)      \
+       struct clk_fixed_factor _struct = {                             \
+               .mult           = _mul,                                 \
+               .div            = _div,                                 \
+               .hw.init        = CLK_HW_INIT(_name,                    \
+                                             _parent,                  \
+                                             &clk_fixed_factor_ops,    \
+                                             _flags),                  \
+       }
+
+extern const struct clk_ops clk_fixed_factor_ops;
+
+#endif /* _OWL_FIXED_FACTOR_H_ */
diff --git a/drivers/clk/actions/owl-gate.c b/drivers/clk/actions/owl-gate.c
new file mode 100644 (file)
index 0000000..f11500b
--- /dev/null
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL gate clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "owl-gate.h"
+
+void owl_gate_set(const struct owl_clk_common *common,
+                const struct owl_gate_hw *gate_hw, bool enable)
+{
+       int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
+       u32 reg;
+
+       set ^= enable;
+
+       regmap_read(common->regmap, gate_hw->reg, &reg);
+
+       if (set)
+               reg |= BIT(gate_hw->bit_idx);
+       else
+               reg &= ~BIT(gate_hw->bit_idx);
+
+       regmap_write(common->regmap, gate_hw->reg, reg);
+}
+
+static void owl_gate_disable(struct clk_hw *hw)
+{
+       struct owl_gate *gate = hw_to_owl_gate(hw);
+       struct owl_clk_common *common = &gate->common;
+
+       owl_gate_set(common, &gate->gate_hw, false);
+}
+
+static int owl_gate_enable(struct clk_hw *hw)
+{
+       struct owl_gate *gate = hw_to_owl_gate(hw);
+       struct owl_clk_common *common = &gate->common;
+
+       owl_gate_set(common, &gate->gate_hw, true);
+
+       return 0;
+}
+
+int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
+                  const struct owl_gate_hw *gate_hw)
+{
+       u32 reg;
+
+       regmap_read(common->regmap, gate_hw->reg, &reg);
+
+       if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
+               reg ^= BIT(gate_hw->bit_idx);
+
+       return !!(reg & BIT(gate_hw->bit_idx));
+}
+
+static int owl_gate_is_enabled(struct clk_hw *hw)
+{
+       struct owl_gate *gate = hw_to_owl_gate(hw);
+       struct owl_clk_common *common = &gate->common;
+
+       return owl_gate_clk_is_enabled(common, &gate->gate_hw);
+}
+
+const struct clk_ops owl_gate_ops = {
+       .disable        = owl_gate_disable,
+       .enable         = owl_gate_enable,
+       .is_enabled     = owl_gate_is_enabled,
+};
diff --git a/drivers/clk/actions/owl-gate.h b/drivers/clk/actions/owl-gate.h
new file mode 100644 (file)
index 0000000..c2d61ce
--- /dev/null
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL gate clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_GATE_H_
+#define _OWL_GATE_H_
+
+#include "owl-common.h"
+
+struct owl_gate_hw {
+       u32                     reg;
+       u8                      bit_idx;
+       u8                      gate_flags;
+};
+
+struct owl_gate {
+       struct owl_gate_hw      gate_hw;
+       struct owl_clk_common   common;
+};
+
+#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags)       \
+       {                                               \
+               .reg            = _reg,                 \
+               .bit_idx        = _bit_idx,             \
+               .gate_flags     = _gate_flags,          \
+       }
+
+#define OWL_GATE(_struct, _name, _parent, _reg,                                \
+               _bit_idx, _gate_flags, _flags)                          \
+       struct owl_gate _struct = {                                     \
+               .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags),    \
+               .common = {                                             \
+                       .regmap         = NULL,                         \
+                       .hw.init        = CLK_HW_INIT(_name,            \
+                                                     _parent,          \
+                                                     &owl_gate_ops,    \
+                                                     _flags),          \
+               }                                                       \
+       }                                                               \
+
+#define OWL_GATE_NO_PARENT(_struct, _name, _reg,                       \
+               _bit_idx, _gate_flags, _flags)                          \
+       struct owl_gate _struct = {                                     \
+               .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags),    \
+               .common = {                                             \
+                       .regmap         = NULL,                         \
+                       .hw.init        = CLK_HW_INIT_NO_PARENT(_name,  \
+                                                     &owl_gate_ops,    \
+                                                     _flags),          \
+               },                                                      \
+       }                                                               \
+
+static inline struct owl_gate *hw_to_owl_gate(const struct clk_hw *hw)
+{
+       struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+       return container_of(common, struct owl_gate, common);
+}
+
+void owl_gate_set(const struct owl_clk_common *common,
+                const struct owl_gate_hw *gate_hw, bool enable);
+int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
+                  const struct owl_gate_hw *gate_hw);
+
+extern const struct clk_ops owl_gate_ops;
+
+#endif /* _OWL_GATE_H_ */
diff --git a/drivers/clk/actions/owl-mux.c b/drivers/clk/actions/owl-mux.c
new file mode 100644 (file)
index 0000000..f9c6cf2
--- /dev/null
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL mux clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "owl-mux.h"
+
+u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
+                            const struct owl_mux_hw *mux_hw)
+{
+       u32 reg;
+       u8 parent;
+
+       regmap_read(common->regmap, mux_hw->reg, &reg);
+       parent = reg >> mux_hw->shift;
+       parent &= BIT(mux_hw->width) - 1;
+
+       return parent;
+}
+
+static u8 owl_mux_get_parent(struct clk_hw *hw)
+{
+       struct owl_mux *mux = hw_to_owl_mux(hw);
+
+       return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw);
+}
+
+int owl_mux_helper_set_parent(const struct owl_clk_common *common,
+                             struct owl_mux_hw *mux_hw, u8 index)
+{
+       u32 reg;
+
+       regmap_read(common->regmap, mux_hw->reg, &reg);
+       reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);
+       regmap_write(common->regmap, mux_hw->reg,
+                       reg | (index << mux_hw->shift));
+
+       return 0;
+}
+
+static int owl_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+       struct owl_mux *mux = hw_to_owl_mux(hw);
+
+       return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index);
+}
+
+const struct clk_ops owl_mux_ops = {
+       .get_parent = owl_mux_get_parent,
+       .set_parent = owl_mux_set_parent,
+       .determine_rate = __clk_mux_determine_rate,
+};
diff --git a/drivers/clk/actions/owl-mux.h b/drivers/clk/actions/owl-mux.h
new file mode 100644 (file)
index 0000000..834284c
--- /dev/null
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL mux clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_MUX_H_
+#define _OWL_MUX_H_
+
+#include "owl-common.h"
+
+struct owl_mux_hw {
+       u32                     reg;
+       u8                      shift;
+       u8                      width;
+};
+
+struct owl_mux {
+       struct owl_mux_hw       mux_hw;
+       struct owl_clk_common   common;
+};
+
+#define OWL_MUX_HW(_reg, _shift, _width)               \
+       {                                               \
+               .reg    = _reg,                         \
+               .shift  = _shift,                       \
+               .width  = _width,                       \
+       }
+
+#define OWL_MUX(_struct, _name, _parents, _reg,                                \
+               _shift, _width, _flags)                                 \
+       struct owl_mux _struct = {                                      \
+               .mux_hw = OWL_MUX_HW(_reg, _shift, _width),             \
+               .common = {                                             \
+                       .regmap = NULL,                                 \
+                       .hw.init = CLK_HW_INIT_PARENTS(_name,           \
+                                                      _parents,        \
+                                                      &owl_mux_ops,    \
+                                                      _flags),         \
+               },                                                      \
+       }
+
+static inline struct owl_mux *hw_to_owl_mux(const struct clk_hw *hw)
+{
+       struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+       return container_of(common, struct owl_mux, common);
+}
+
+u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
+                            const struct owl_mux_hw *mux_hw);
+int owl_mux_helper_set_parent(const struct owl_clk_common *common,
+                             struct owl_mux_hw *mux_hw, u8 index);
+
+extern const struct clk_ops owl_mux_ops;
+
+#endif /* _OWL_MUX_H_ */
diff --git a/drivers/clk/actions/owl-pll.c b/drivers/clk/actions/owl-pll.c
new file mode 100644 (file)
index 0000000..058e06d
--- /dev/null
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL pll clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include "owl-pll.h"
+
+static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate)
+{
+       u32 mul;
+
+       mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq);
+       if (mul < pll_hw->min_mul)
+               mul = pll_hw->min_mul;
+       else if (mul > pll_hw->max_mul)
+               mul = pll_hw->max_mul;
+
+       return mul &= mul_mask(pll_hw);
+}
+
+static unsigned long _get_table_rate(const struct clk_pll_table *table,
+               unsigned int val)
+{
+       const struct clk_pll_table *clkt;
+
+       for (clkt = table; clkt->rate; clkt++)
+               if (clkt->val == val)
+                       return clkt->rate;
+
+       return 0;
+}
+
+static const struct clk_pll_table *_get_pll_table(
+               const struct clk_pll_table *table, unsigned long rate)
+{
+       const struct clk_pll_table *clkt;
+
+       for (clkt = table; clkt->rate; clkt++) {
+               if (clkt->rate == rate) {
+                       table = clkt;
+                       break;
+               } else if (clkt->rate < rate)
+                       table = clkt;
+       }
+
+       return table;
+}
+
+static long owl_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long *parent_rate)
+{
+       struct owl_pll *pll = hw_to_owl_pll(hw);
+       struct owl_pll_hw *pll_hw = &pll->pll_hw;
+       const struct clk_pll_table *clkt;
+       u32 mul;
+
+       if (pll_hw->table) {
+               clkt = _get_pll_table(pll_hw->table, rate);
+               return clkt->rate;
+       }
+
+       /* fixed frequency */
+       if (pll_hw->width == 0)
+               return pll_hw->bfreq;
+
+       mul = owl_pll_calculate_mul(pll_hw, rate);
+
+       return pll_hw->bfreq * mul;
+}
+
+static unsigned long owl_pll_recalc_rate(struct clk_hw *hw,
+               unsigned long parent_rate)
+{
+       struct owl_pll *pll = hw_to_owl_pll(hw);
+       struct owl_pll_hw *pll_hw = &pll->pll_hw;
+       const struct owl_clk_common *common = &pll->common;
+       u32 val;
+
+       if (pll_hw->table) {
+               regmap_read(common->regmap, pll_hw->reg, &val);
+
+               val = val >> pll_hw->shift;
+               val &= mul_mask(pll_hw);
+
+               return _get_table_rate(pll_hw->table, val);
+       }
+
+       /* fixed frequency */
+       if (pll_hw->width == 0)
+               return pll_hw->bfreq;
+
+       regmap_read(common->regmap, pll_hw->reg, &val);
+
+       val = val >> pll_hw->shift;
+       val &= mul_mask(pll_hw);
+
+       return pll_hw->bfreq * val;
+}
+
+static int owl_pll_is_enabled(struct clk_hw *hw)
+{
+       struct owl_pll *pll = hw_to_owl_pll(hw);
+       struct owl_pll_hw *pll_hw = &pll->pll_hw;
+       const struct owl_clk_common *common = &pll->common;
+       u32 reg;
+
+       regmap_read(common->regmap, pll_hw->reg, &reg);
+
+       return !!(reg & BIT(pll_hw->bit_idx));
+}
+
+static void owl_pll_set(const struct owl_clk_common *common,
+                      const struct owl_pll_hw *pll_hw, bool enable)
+{
+       u32 reg;
+
+       regmap_read(common->regmap, pll_hw->reg, &reg);
+
+       if (enable)
+               reg |= BIT(pll_hw->bit_idx);
+       else
+               reg &= ~BIT(pll_hw->bit_idx);
+
+       regmap_write(common->regmap, pll_hw->reg, reg);
+}
+
+static int owl_pll_enable(struct clk_hw *hw)
+{
+       struct owl_pll *pll = hw_to_owl_pll(hw);
+       const struct owl_clk_common *common = &pll->common;
+
+       owl_pll_set(common, &pll->pll_hw, true);
+
+       return 0;
+}
+
+static void owl_pll_disable(struct clk_hw *hw)
+{
+       struct owl_pll *pll = hw_to_owl_pll(hw);
+       const struct owl_clk_common *common = &pll->common;
+
+       owl_pll_set(common, &pll->pll_hw, false);
+}
+
+static int owl_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long parent_rate)
+{
+       struct owl_pll *pll = hw_to_owl_pll(hw);
+       struct owl_pll_hw *pll_hw = &pll->pll_hw;
+       const struct owl_clk_common *common = &pll->common;
+       const struct clk_pll_table *clkt;
+       u32 val, reg;
+
+       /* fixed frequency */
+       if (pll_hw->width == 0)
+               return 0;
+
+       if (pll_hw->table) {
+               clkt = _get_pll_table(pll_hw->table, rate);
+               val = clkt->val;
+       } else {
+               val = owl_pll_calculate_mul(pll_hw, rate);
+       }
+
+       regmap_read(common->regmap, pll_hw->reg, &reg);
+
+       reg &= ~mul_mask(pll_hw);
+       reg |= val << pll_hw->shift;
+
+       regmap_write(common->regmap, pll_hw->reg, reg);
+
+       udelay(PLL_STABILITY_WAIT_US);
+
+       return 0;
+}
+
+const struct clk_ops owl_pll_ops = {
+       .enable = owl_pll_enable,
+       .disable = owl_pll_disable,
+       .is_enabled = owl_pll_is_enabled,
+       .round_rate = owl_pll_round_rate,
+       .recalc_rate = owl_pll_recalc_rate,
+       .set_rate = owl_pll_set_rate,
+};
diff --git a/drivers/clk/actions/owl-pll.h b/drivers/clk/actions/owl-pll.h
new file mode 100644 (file)
index 0000000..0aae30a
--- /dev/null
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL pll clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_PLL_H_
+#define _OWL_PLL_H_
+
+#include "owl-common.h"
+
+/* last entry should have rate = 0 */
+struct clk_pll_table {
+       unsigned int            val;
+       unsigned long           rate;
+};
+
+struct owl_pll_hw {
+       u32                     reg;
+       u32                     bfreq;
+       u8                      bit_idx;
+       u8                      shift;
+       u8                      width;
+       u8                      min_mul;
+       u8                      max_mul;
+       const struct clk_pll_table *table;
+};
+
+struct owl_pll {
+       struct owl_pll_hw       pll_hw;
+       struct owl_clk_common   common;
+};
+
+#define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,                     \
+                  _width, _min_mul, _max_mul, _table)                  \
+       {                                                               \
+               .reg            = _reg,                                 \
+               .bfreq          = _bfreq,                               \
+               .bit_idx        = _bit_idx,                             \
+               .shift          = _shift,                               \
+               .width          = _width,                               \
+               .min_mul        = _min_mul,                             \
+               .max_mul        = _max_mul,                             \
+               .table          = _table,                               \
+       }
+
+#define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx,       \
+               _shift, _width, _min_mul, _max_mul, _table, _flags)     \
+       struct owl_pll _struct = {                                      \
+               .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,    \
+                                    _width, _min_mul,                  \
+                                    _max_mul, _table),                 \
+               .common = {                                             \
+                       .regmap = NULL,                                 \
+                       .hw.init = CLK_HW_INIT(_name,                   \
+                                              _parent,                 \
+                                              &owl_pll_ops,            \
+                                              _flags),                 \
+               },                                                      \
+       }
+
+#define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx,      \
+               _shift, _width, _min_mul, _max_mul, _table, _flags)     \
+       struct owl_pll _struct = {                                      \
+               .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,    \
+                                    _width, _min_mul,                  \
+                                    _max_mul, _table),                 \
+               .common = {                                             \
+                       .regmap = NULL,                                 \
+                       .hw.init = CLK_HW_INIT_NO_PARENT(_name,         \
+                                              &owl_pll_ops,            \
+                                              _flags),                 \
+               },                                                      \
+       }
+
+#define mul_mask(m)            ((1 << ((m)->width)) - 1)
+#define PLL_STABILITY_WAIT_US  (50)
+
+static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
+{
+       struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+       return container_of(common, struct owl_pll, common);
+}
+
+extern const struct clk_ops owl_pll_ops;
+
+#endif /* _OWL_PLL_H_ */
diff --git a/drivers/clk/actions/owl-s900.c b/drivers/clk/actions/owl-s900.c
new file mode 100644 (file)
index 0000000..7f60ed6
--- /dev/null
@@ -0,0 +1,721 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL S900 SoC clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "owl-common.h"
+#include "owl-composite.h"
+#include "owl-divider.h"
+#include "owl-factor.h"
+#include "owl-fixed-factor.h"
+#include "owl-gate.h"
+#include "owl-mux.h"
+#include "owl-pll.h"
+
+#include <dt-bindings/clock/actions,s900-cmu.h>
+
+#define CMU_COREPLL            (0x0000)
+#define CMU_DEVPLL             (0x0004)
+#define CMU_DDRPLL             (0x0008)
+#define CMU_NANDPLL            (0x000C)
+#define CMU_DISPLAYPLL         (0x0010)
+#define CMU_AUDIOPLL           (0x0014)
+#define CMU_TVOUTPLL           (0x0018)
+#define CMU_BUSCLK             (0x001C)
+#define CMU_SENSORCLK          (0x0020)
+#define CMU_LCDCLK             (0x0024)
+#define CMU_DSICLK             (0x0028)
+#define CMU_CSICLK             (0x002C)
+#define CMU_DECLK              (0x0030)
+#define CMU_BISPCLK            (0x0034)
+#define CMU_IMXCLK             (0x0038)
+#define CMU_HDECLK             (0x003C)
+#define CMU_VDECLK             (0x0040)
+#define CMU_VCECLK             (0x0044)
+#define CMU_NANDCCLK           (0x004C)
+#define CMU_SD0CLK             (0x0050)
+#define CMU_SD1CLK             (0x0054)
+#define CMU_SD2CLK             (0x0058)
+#define CMU_UART0CLK           (0x005C)
+#define CMU_UART1CLK           (0x0060)
+#define CMU_UART2CLK           (0x0064)
+#define CMU_PWM0CLK            (0x0070)
+#define CMU_PWM1CLK            (0x0074)
+#define CMU_PWM2CLK            (0x0078)
+#define CMU_PWM3CLK            (0x007C)
+#define CMU_USBPLL             (0x0080)
+#define CMU_ASSISTPLL          (0x0084)
+#define CMU_EDPCLK             (0x0088)
+#define CMU_GPU3DCLK           (0x0090)
+#define CMU_CORECTL            (0x009C)
+#define CMU_DEVCLKEN0          (0x00A0)
+#define CMU_DEVCLKEN1          (0x00A4)
+#define CMU_DEVRST0            (0x00A8)
+#define CMU_DEVRST1            (0x00AC)
+#define CMU_UART3CLK           (0x00B0)
+#define CMU_UART4CLK           (0x00B4)
+#define CMU_UART5CLK           (0x00B8)
+#define CMU_UART6CLK           (0x00BC)
+#define CMU_TLSCLK             (0x00C0)
+#define CMU_SD3CLK             (0x00C4)
+#define CMU_PWM4CLK            (0x00C8)
+#define CMU_PWM5CLK            (0x00CC)
+
+static struct clk_pll_table clk_audio_pll_table[] = {
+       { 0, 45158400 }, { 1, 49152000 },
+       { 0, 0 },
+};
+
+static struct clk_pll_table clk_edp_pll_table[] = {
+       { 0, 810000000 }, { 1, 135000000 }, { 2, 270000000 },
+       { 0, 0 },
+};
+
+/* pll clocks */
+static OWL_PLL_NO_PARENT(core_pll_clk, "core_pll_clk", CMU_COREPLL, 24000000, 9, 0, 8, 5, 107, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 24000000, 8, 0, 8, 5, 45, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 8, 4, 100, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(assist_pll_clk, "assist_pll_clk", CMU_ASSISTPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
+static OWL_PLL(edp_pll_clk, "edp_pll_clk", "edp24M_clk", CMU_EDPCLK, 0, 9, 0, 2, 0, 0, clk_edp_pll_table, CLK_IGNORE_UNUSED);
+
+static const char *cpu_clk_mux_p[] = { "losc", "hosc", "core_pll_clk", };
+static const char *dev_clk_p[] = { "hosc", "dev_pll_clk", };
+static const char *noc_clk_mux_p[] = { "dev_clk", "assist_pll_clk", };
+static const char *dmm_clk_mux_p[] = { "dev_clk", "nand_pll_clk", "assist_pll_clk", "ddr_clk_src", };
+static const char *bisp_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
+static const char *csi_clk_mux_p[] = { "display_pll_clk", "dev_clk", };
+static const char *de_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
+static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
+static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
+static const char *imx_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
+static const char *lcd_clk_mux_p[] = { "display_pll_clk", "nand_pll_clk", };
+static const char *nand_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
+static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
+static const char *sensor_clk_mux_p[] = { "hosc", "bisp_clk", };
+static const char *uart_clk_mux_p[] = { "hosc", "dev_pll_clk", };
+static const char *vce_clk_mux_p[] = { "dev_clk", "display_pll_clk", "assist_pll_clk", "ddr_clk_src", };
+static const char *i2s_clk_mux_p[] = { "audio_pll_clk", };
+static const char *edp_clk_mux_p[] = { "assist_pll_clk", "display_pll_clk", };
+
+/* mux clocks */
+static OWL_MUX(cpu_clk, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
+static OWL_MUX(dev_clk, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
+static OWL_MUX(noc_clk_mux, "noc_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 7, 1, CLK_SET_RATE_PARENT);
+
+static struct clk_div_table nand_div_table[] = {
+       { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
+       { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
+       { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
+       { 12, 24 }, { 13, 26 }, { 14, 28 }, { 15, 30 },
+       { 0, 0 },
+};
+
+static struct clk_div_table apb_div_table[] = {
+       { 1, 2 }, { 2, 3 }, { 3, 4 },
+       { 0, 0 },
+};
+
+static struct clk_div_table eth_mac_div_table[] = {
+       { 0, 2 }, { 1, 4 },
+       { 0, 0 },
+};
+
+static struct clk_div_table rmii_ref_div_table[] = {
+       { 0, 4 },         { 1, 10 },
+       { 0, 0 },
+};
+
+static struct clk_div_table usb3_mac_div_table[] = {
+       { 1, 2 }, { 2, 3 }, { 3, 4 },
+       { 0, 8 },
+};
+
+static struct clk_div_table i2s_div_table[] = {
+       { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
+       { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
+       { 8, 24 },
+       { 0, 0 },
+};
+
+static struct clk_div_table hdmia_div_table[] = {
+       { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
+       { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
+       { 8, 24 },
+       { 0, 0 },
+};
+
+/* divider clocks */
+static OWL_DIVIDER(noc_clk_div, "noc_clk_div", "noc_clk", CMU_BUSCLK, 19, 1, NULL, 0, 0);
+static OWL_DIVIDER(ahb_clk, "ahb_clk", "noc_clk_div", CMU_BUSCLK, 4, 1, NULL, 0, 0);
+static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK, 8, 2, apb_div_table, 0, 0);
+static OWL_DIVIDER(usb3_mac_clk, "usb3_mac_clk", "assist_pll_clk", CMU_ASSISTPLL, 12, 2, usb3_mac_div_table, 0, 0);
+static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "assist_pll_clk", CMU_ASSISTPLL, 8, 1, rmii_ref_div_table, 0, 0);
+
+static struct clk_factor_table sd_factor_table[] = {
+       /* bit0 ~ 4 */
+       { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
+       { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
+       { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
+       { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
+       { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
+       { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
+       { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
+       { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
+
+       /* bit8: /128 */
+       { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
+       { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
+       { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
+       { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
+       { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
+       { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
+       { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
+       { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
+
+       { 0, 0 },
+};
+
+static struct clk_factor_table dmm_factor_table[] = {
+       { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 },
+       { 4, 1, 4 },
+       { 0, 0, 0 },
+};
+
+static struct clk_factor_table noc_factor_table[] = {
+       { 0, 1, 1 },   { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 }, { 4, 1, 4 },
+       { 0, 0, 0 },
+};
+
+static struct clk_factor_table bisp_factor_table[] = {
+       { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
+       { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
+       { 0, 0, 0 },
+};
+
+/* factor clocks */
+static OWL_FACTOR(noc_clk, "noc_clk", "noc_clk_mux", CMU_BUSCLK, 16, 3, noc_factor_table, 0, 0);
+static OWL_FACTOR(de_clk1, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
+static OWL_FACTOR(de_clk2, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
+static OWL_FACTOR(de_clk3, "de_clk3", "de_clk", CMU_DECLK, 8, 3, bisp_factor_table, 0, 0);
+
+/* gate clocks */
+static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
+static OWL_GATE_NO_PARENT(gpu_clk, "gpu_clk", CMU_DEVCLKEN0, 30, 0, 0);
+static OWL_GATE(dmac_clk, "dmac_clk", "noc_clk_div", CMU_DEVCLKEN0, 1, 0, 0);
+static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
+static OWL_GATE_NO_PARENT(dsi_clk, "dsi_clk", CMU_DEVCLKEN0, 12, 0, 0);
+static OWL_GATE(ddr0_clk, "ddr0_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 31, 0, CLK_IGNORE_UNUSED);
+static OWL_GATE(ddr1_clk, "ddr1_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 29, 0, CLK_IGNORE_UNUSED);
+static OWL_GATE_NO_PARENT(usb3_480mpll0_clk, "usb3_480mpll0_clk", CMU_USBPLL, 3, 0, 0);
+static OWL_GATE_NO_PARENT(usb3_480mphy0_clk, "usb3_480mphy0_clk", CMU_USBPLL, 2, 0, 0);
+static OWL_GATE_NO_PARENT(usb3_5gphy_clk, "usb3_5gphy_clk", CMU_USBPLL, 1, 0, 0);
+static OWL_GATE_NO_PARENT(usb3_cce_clk, "usb3_cce_clk", CMU_USBPLL, 0, 0, 0);
+static OWL_GATE(edp24M_clk, "edp24M_clk", "diff24M", CMU_EDPCLK, 8, 0, 0);
+static OWL_GATE(edp_link_clk, "edp_link_clk", "edp_pll_clk", CMU_DEVCLKEN0, 10, 0, 0);
+static OWL_GATE_NO_PARENT(usbh0_pllen_clk, "usbh0_pllen_clk", CMU_USBPLL, 12, 0, 0);
+static OWL_GATE_NO_PARENT(usbh0_phy_clk, "usbh0_phy_clk", CMU_USBPLL, 10, 0, 0);
+static OWL_GATE_NO_PARENT(usbh0_cce_clk, "usbh0_cce_clk", CMU_USBPLL, 8, 0, 0);
+static OWL_GATE_NO_PARENT(usbh1_pllen_clk, "usbh1_pllen_clk", CMU_USBPLL, 13, 0, 0);
+static OWL_GATE_NO_PARENT(usbh1_phy_clk, "usbh1_phy_clk", CMU_USBPLL, 11, 0, 0);
+static OWL_GATE_NO_PARENT(usbh1_cce_clk, "usbh1_cce_clk", CMU_USBPLL, 9, 0, 0);
+static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
+static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
+static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
+static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
+
+/* composite clocks */
+static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
+                       OWL_MUX_HW(CMU_BISPCLK, 4, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
+                       OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
+                       0);
+
+static OWL_COMP_DIV(csi0_clk, "csi0_clk", csi_clk_mux_p,
+                       OWL_MUX_HW(CMU_CSICLK, 4, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
+                       OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
+                       0);
+
+static OWL_COMP_DIV(csi1_clk, "csi1_clk", csi_clk_mux_p,
+                       OWL_MUX_HW(CMU_CSICLK, 20, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 15, 0),
+                       OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL),
+                       0);
+
+static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
+                       OWL_MUX_HW(CMU_DECLK, 12, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
+                       0);
+
+static OWL_COMP_FACTOR(dmm_clk, "dmm_clk", dmm_clk_mux_p,
+                       OWL_MUX_HW(CMU_BUSCLK, 10, 2),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 19, 0),
+                       OWL_FACTOR_HW(CMU_BUSCLK, 12, 3, 0, dmm_factor_table),
+                       CLK_IGNORE_UNUSED);
+
+static OWL_COMP_FACTOR(edp_clk, "edp_clk", edp_clk_mux_p,
+                       OWL_MUX_HW(CMU_EDPCLK, 19, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
+                       OWL_FACTOR_HW(CMU_EDPCLK, 16, 3, 0, bisp_factor_table),
+                       0);
+
+static OWL_COMP_DIV_FIXED(eth_mac_clk, "eth_mac_clk", "assist_pll_clk",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
+                       OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table),
+                       0);
+
+static OWL_COMP_FACTOR(gpu_core_clk, "gpu_core_clk", gpu_clk_mux_p,
+                       OWL_MUX_HW(CMU_GPU3DCLK, 4, 2),
+                       OWL_GATE_HW(CMU_GPU3DCLK, 15, 0),
+                       OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, bisp_factor_table),
+                       0);
+
+static OWL_COMP_FACTOR(gpu_mem_clk, "gpu_mem_clk", gpu_clk_mux_p,
+                       OWL_MUX_HW(CMU_GPU3DCLK, 20, 2),
+                       OWL_GATE_HW(CMU_GPU3DCLK, 14, 0),
+                       OWL_FACTOR_HW(CMU_GPU3DCLK, 16, 3, 0, bisp_factor_table),
+                       0);
+
+static OWL_COMP_FACTOR(gpu_sys_clk, "gpu_sys_clk", gpu_clk_mux_p,
+                       OWL_MUX_HW(CMU_GPU3DCLK, 28, 2),
+                       OWL_GATE_HW(CMU_GPU3DCLK, 13, 0),
+                       OWL_FACTOR_HW(CMU_GPU3DCLK, 24, 3, 0, bisp_factor_table),
+                       0);
+
+static OWL_COMP_FACTOR(hde_clk, "hde_clk", hde_clk_mux_p,
+                       OWL_MUX_HW(CMU_HDECLK, 4, 2),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 27, 0),
+                       OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, bisp_factor_table),
+                       0);
+
+static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
+                       OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
+                       OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
+                       0);
+
+static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "assist_pll_clk",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
+                       1, 5, 0);
+
+static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "assist_pll_clk",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
+                       1, 5, 0);
+
+static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "assist_pll_clk",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
+                       1, 5, 0);
+
+static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "assist_pll_clk",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
+                       1, 5, 0);
+
+static OWL_COMP_FIXED_FACTOR(i2c4_clk, "i2c4_clk", "assist_pll_clk",
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 17, 0),
+                       1, 5, 0);
+
+static OWL_COMP_FIXED_FACTOR(i2c5_clk, "i2c5_clk", "assist_pll_clk",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 1, 0),
+                       1, 5, 0);
+
+static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
+                       OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
+                       OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
+                       0);
+
+static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
+                       OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
+                       OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
+                       0);
+
+static OWL_COMP_FACTOR(imx_clk, "imx_clk", imx_clk_mux_p,
+                       OWL_MUX_HW(CMU_IMXCLK, 4, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
+                       OWL_FACTOR_HW(CMU_IMXCLK, 0, 3, 0, bisp_factor_table),
+                       0);
+
+static OWL_COMP_DIV(lcd_clk, "lcd_clk", lcd_clk_mux_p,
+                       OWL_MUX_HW(CMU_LCDCLK, 12, 2),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
+                       OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL),
+                       0);
+
+static OWL_COMP_DIV(nand0_clk, "nand0_clk", nand_clk_mux_p,
+                       OWL_MUX_HW(CMU_NANDCCLK, 8, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
+                       OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table),
+                       CLK_SET_RATE_PARENT);
+
+static OWL_COMP_DIV(nand1_clk, "nand1_clk", nand_clk_mux_p,
+                       OWL_MUX_HW(CMU_NANDCCLK, 24, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
+                       OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table),
+                       CLK_SET_RATE_PARENT);
+
+static OWL_COMP_DIV_FIXED(pwm0_clk, "pwm0_clk", "hosc",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
+                       OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL),
+                       0);
+
+static OWL_COMP_DIV_FIXED(pwm1_clk, "pwm1_clk", "hosc",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
+                       OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL),
+                       0);
+/*
+ * pwm2 may be for backlight, do not gate it
+ * even it is "unused", because it may be
+ * enabled at boot stage, and in kernel, driver
+ * has no effective method to know the real status,
+ * so, the best way is keeping it as what it was.
+ */
+static OWL_COMP_DIV_FIXED(pwm2_clk, "pwm2_clk", "hosc",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
+                       OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL),
+                       CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV_FIXED(pwm3_clk, "pwm3_clk", "hosc",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
+                       OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL),
+                       0);
+
+static OWL_COMP_DIV_FIXED(pwm4_clk, "pwm4_clk", "hosc",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 4, 0),
+                       OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL),
+                       0);
+
+static OWL_COMP_DIV_FIXED(pwm5_clk, "pwm5_clk", "hosc",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 5, 0),
+                       OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL),
+                       0);
+
+static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
+                       OWL_MUX_HW(CMU_SD0CLK, 9, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
+                       OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
+                       0);
+
+static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
+                       OWL_MUX_HW(CMU_SD1CLK, 9, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
+                       OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
+                       0);
+
+static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
+                       OWL_MUX_HW(CMU_SD2CLK, 9, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
+                       OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
+                       0);
+
+static OWL_COMP_FACTOR(sd3_clk, "sd3_clk", sd_clk_mux_p,
+                       OWL_MUX_HW(CMU_SD3CLK, 9, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 16, 0),
+                       OWL_FACTOR_HW(CMU_SD3CLK, 0, 9, 0, sd_factor_table),
+                       0);
+
+static OWL_COMP_DIV(sensor_clk, "sensor_clk", sensor_clk_mux_p,
+                       OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
+                       OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL),
+                       0);
+
+static OWL_COMP_DIV_FIXED(speed_sensor_clk, "speed_sensor_clk",
+                       "hosc",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 0, 0),
+                       OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
+                       0);
+
+static OWL_COMP_DIV_FIXED(thermal_sensor_clk, "thermal_sensor_clk",
+                       "hosc",
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 2, 0),
+                       OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
+                       0);
+
+static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
+                       OWL_MUX_HW(CMU_UART0CLK, 16, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
+                       OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                       CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
+                       OWL_MUX_HW(CMU_UART1CLK, 16, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
+                       OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                       CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
+                       OWL_MUX_HW(CMU_UART2CLK, 16, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
+                       OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                       CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
+                       OWL_MUX_HW(CMU_UART3CLK, 16, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
+                       OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                       CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
+                       OWL_MUX_HW(CMU_UART4CLK, 16, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
+                       OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                       CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
+                       OWL_MUX_HW(CMU_UART5CLK, 16, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
+                       OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                       CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
+                       OWL_MUX_HW(CMU_UART6CLK, 16, 1),
+                       OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
+                       OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                       CLK_IGNORE_UNUSED);
+
+static OWL_COMP_FACTOR(vce_clk, "vce_clk", vce_clk_mux_p,
+                       OWL_MUX_HW(CMU_VCECLK, 4, 2),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
+                       OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
+                       0);
+
+static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
+                       OWL_MUX_HW(CMU_VDECLK, 4, 2),
+                       OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
+                       OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
+                       0);
+
+static struct owl_clk_common *s900_clks[] = {
+       &core_pll_clk.common,
+       &dev_pll_clk.common,
+       &ddr_pll_clk.common,
+       &nand_pll_clk.common,
+       &display_pll_clk.common,
+       &assist_pll_clk.common,
+       &audio_pll_clk.common,
+       &edp_pll_clk.common,
+       &cpu_clk.common,
+       &dev_clk.common,
+       &noc_clk_mux.common,
+       &noc_clk_div.common,
+       &ahb_clk.common,
+       &apb_clk.common,
+       &usb3_mac_clk.common,
+       &rmii_ref_clk.common,
+       &noc_clk.common,
+       &de_clk1.common,
+       &de_clk2.common,
+       &de_clk3.common,
+       &gpio_clk.common,
+       &gpu_clk.common,
+       &dmac_clk.common,
+       &timer_clk.common,
+       &dsi_clk.common,
+       &ddr0_clk.common,
+       &ddr1_clk.common,
+       &usb3_480mpll0_clk.common,
+       &usb3_480mphy0_clk.common,
+       &usb3_5gphy_clk.common,
+       &usb3_cce_clk.common,
+       &edp24M_clk.common,
+       &edp_link_clk.common,
+       &usbh0_pllen_clk.common,
+       &usbh0_phy_clk.common,
+       &usbh0_cce_clk.common,
+       &usbh1_pllen_clk.common,
+       &usbh1_phy_clk.common,
+       &usbh1_cce_clk.common,
+       &i2c0_clk.common,
+       &i2c1_clk.common,
+       &i2c2_clk.common,
+       &i2c3_clk.common,
+       &i2c4_clk.common,
+       &i2c5_clk.common,
+       &spi0_clk.common,
+       &spi1_clk.common,
+       &spi2_clk.common,
+       &spi3_clk.common,
+       &bisp_clk.common,
+       &csi0_clk.common,
+       &csi1_clk.common,
+       &de_clk.common,
+       &dmm_clk.common,
+       &edp_clk.common,
+       &eth_mac_clk.common,
+       &gpu_core_clk.common,
+       &gpu_mem_clk.common,
+       &gpu_sys_clk.common,
+       &hde_clk.common,
+       &hdmia_clk.common,
+       &i2srx_clk.common,
+       &i2stx_clk.common,
+       &imx_clk.common,
+       &lcd_clk.common,
+       &nand0_clk.common,
+       &nand1_clk.common,
+       &pwm0_clk.common,
+       &pwm1_clk.common,
+       &pwm2_clk.common,
+       &pwm3_clk.common,
+       &pwm4_clk.common,
+       &pwm5_clk.common,
+       &sd0_clk.common,
+       &sd1_clk.common,
+       &sd2_clk.common,
+       &sd3_clk.common,
+       &sensor_clk.common,
+       &speed_sensor_clk.common,
+       &thermal_sensor_clk.common,
+       &uart0_clk.common,
+       &uart1_clk.common,
+       &uart2_clk.common,
+       &uart3_clk.common,
+       &uart4_clk.common,
+       &uart5_clk.common,
+       &uart6_clk.common,
+       &vce_clk.common,
+       &vde_clk.common,
+};
+
+static struct clk_hw_onecell_data s900_hw_clks = {
+       .hws    = {
+               [CLK_CORE_PLL]          = &core_pll_clk.common.hw,
+               [CLK_DEV_PLL]           = &dev_pll_clk.common.hw,
+               [CLK_DDR_PLL]           = &ddr_pll_clk.common.hw,
+               [CLK_NAND_PLL]          = &nand_pll_clk.common.hw,
+               [CLK_DISPLAY_PLL]       = &display_pll_clk.common.hw,
+               [CLK_ASSIST_PLL]        = &assist_pll_clk.common.hw,
+               [CLK_AUDIO_PLL]         = &audio_pll_clk.common.hw,
+               [CLK_EDP_PLL]           = &edp_pll_clk.common.hw,
+               [CLK_CPU]               = &cpu_clk.common.hw,
+               [CLK_DEV]               = &dev_clk.common.hw,
+               [CLK_NOC_MUX]           = &noc_clk_mux.common.hw,
+               [CLK_NOC_DIV]           = &noc_clk_div.common.hw,
+               [CLK_AHB]               = &ahb_clk.common.hw,
+               [CLK_APB]               = &apb_clk.common.hw,
+               [CLK_USB3_MAC]          = &usb3_mac_clk.common.hw,
+               [CLK_RMII_REF]          = &rmii_ref_clk.common.hw,
+               [CLK_NOC]               = &noc_clk.common.hw,
+               [CLK_DE1]               = &de_clk1.common.hw,
+               [CLK_DE2]               = &de_clk2.common.hw,
+               [CLK_DE3]               = &de_clk3.common.hw,
+               [CLK_GPIO]              = &gpio_clk.common.hw,
+               [CLK_GPU]               = &gpu_clk.common.hw,
+               [CLK_DMAC]              = &dmac_clk.common.hw,
+               [CLK_TIMER]             = &timer_clk.common.hw,
+               [CLK_DSI]               = &dsi_clk.common.hw,
+               [CLK_DDR0]              = &ddr0_clk.common.hw,
+               [CLK_DDR1]              = &ddr1_clk.common.hw,
+               [CLK_USB3_480MPLL0]     = &usb3_480mpll0_clk.common.hw,
+               [CLK_USB3_480MPHY0]     = &usb3_480mphy0_clk.common.hw,
+               [CLK_USB3_5GPHY]        = &usb3_5gphy_clk.common.hw,
+               [CLK_USB3_CCE]          = &usb3_cce_clk.common.hw,
+               [CLK_24M_EDP]           = &edp24M_clk.common.hw,
+               [CLK_EDP_LINK]          = &edp_link_clk.common.hw,
+               [CLK_USB2H0_PLLEN]      = &usbh0_pllen_clk.common.hw,
+               [CLK_USB2H0_PHY]        = &usbh0_phy_clk.common.hw,
+               [CLK_USB2H0_CCE]        = &usbh0_cce_clk.common.hw,
+               [CLK_USB2H1_PLLEN]      = &usbh1_pllen_clk.common.hw,
+               [CLK_USB2H1_PHY]        = &usbh1_phy_clk.common.hw,
+               [CLK_USB2H1_CCE]        = &usbh1_cce_clk.common.hw,
+               [CLK_I2C0]              = &i2c0_clk.common.hw,
+               [CLK_I2C1]              = &i2c1_clk.common.hw,
+               [CLK_I2C2]              = &i2c2_clk.common.hw,
+               [CLK_I2C3]              = &i2c3_clk.common.hw,
+               [CLK_I2C4]              = &i2c4_clk.common.hw,
+               [CLK_I2C5]              = &i2c5_clk.common.hw,
+               [CLK_SPI0]              = &spi0_clk.common.hw,
+               [CLK_SPI1]              = &spi1_clk.common.hw,
+               [CLK_SPI2]              = &spi2_clk.common.hw,
+               [CLK_SPI3]              = &spi3_clk.common.hw,
+               [CLK_BISP]              = &bisp_clk.common.hw,
+               [CLK_CSI0]              = &csi0_clk.common.hw,
+               [CLK_CSI1]              = &csi1_clk.common.hw,
+               [CLK_DE0]               = &de_clk.common.hw,
+               [CLK_DMM]               = &dmm_clk.common.hw,
+               [CLK_EDP]               = &edp_clk.common.hw,
+               [CLK_ETH_MAC]           = &eth_mac_clk.common.hw,
+               [CLK_GPU_CORE]          = &gpu_core_clk.common.hw,
+               [CLK_GPU_MEM]           = &gpu_mem_clk.common.hw,
+               [CLK_GPU_SYS]           = &gpu_sys_clk.common.hw,
+               [CLK_HDE]               = &hde_clk.common.hw,
+               [CLK_HDMI_AUDIO]        = &hdmia_clk.common.hw,
+               [CLK_I2SRX]             = &i2srx_clk.common.hw,
+               [CLK_I2STX]             = &i2stx_clk.common.hw,
+               [CLK_IMX]               = &imx_clk.common.hw,
+               [CLK_LCD]               = &lcd_clk.common.hw,
+               [CLK_NAND0]             = &nand0_clk.common.hw,
+               [CLK_NAND1]             = &nand1_clk.common.hw,
+               [CLK_PWM0]              = &pwm0_clk.common.hw,
+               [CLK_PWM1]              = &pwm1_clk.common.hw,
+               [CLK_PWM2]              = &pwm2_clk.common.hw,
+               [CLK_PWM3]              = &pwm3_clk.common.hw,
+               [CLK_PWM4]              = &pwm4_clk.common.hw,
+               [CLK_PWM5]              = &pwm5_clk.common.hw,
+               [CLK_SD0]               = &sd0_clk.common.hw,
+               [CLK_SD1]               = &sd1_clk.common.hw,
+               [CLK_SD2]               = &sd2_clk.common.hw,
+               [CLK_SD3]               = &sd3_clk.common.hw,
+               [CLK_SENSOR]            = &sensor_clk.common.hw,
+               [CLK_SPEED_SENSOR]      = &speed_sensor_clk.common.hw,
+               [CLK_THERMAL_SENSOR]    = &thermal_sensor_clk.common.hw,
+               [CLK_UART0]             = &uart0_clk.common.hw,
+               [CLK_UART1]             = &uart1_clk.common.hw,
+               [CLK_UART2]             = &uart2_clk.common.hw,
+               [CLK_UART3]             = &uart3_clk.common.hw,
+               [CLK_UART4]             = &uart4_clk.common.hw,
+               [CLK_UART5]             = &uart5_clk.common.hw,
+               [CLK_UART6]             = &uart6_clk.common.hw,
+               [CLK_VCE]               = &vce_clk.common.hw,
+               [CLK_VDE]               = &vde_clk.common.hw,
+       },
+       .num    = CLK_NR_CLKS,
+};
+
+static const struct owl_clk_desc s900_clk_desc = {
+       .clks       = s900_clks,
+       .num_clks   = ARRAY_SIZE(s900_clks),
+
+       .hw_clks    = &s900_hw_clks,
+};
+
+static int s900_clk_probe(struct platform_device *pdev)
+{
+       const struct owl_clk_desc *desc;
+
+       desc = &s900_clk_desc;
+       owl_clk_regmap_init(pdev, desc);
+
+       return owl_clk_probe(&pdev->dev, desc->hw_clks);
+}
+
+static const struct of_device_id s900_clk_of_match[] = {
+       { .compatible = "actions,s900-cmu", },
+       { /* sentinel */ }
+};
+
+static struct platform_driver s900_clk_driver = {
+       .probe = s900_clk_probe,
+       .driver = {
+               .name = "s900-cmu",
+               .of_match_table = s900_clk_of_match,
+       },
+};
+
+static int __init s900_clk_init(void)
+{
+       return platform_driver_register(&s900_clk_driver);
+}
+core_initcall(s900_clk_init);
index 5eb50c31e4553c114a6ce62d38a4afb0b158f9b6..eb5fb7f88ccd39ab986310760cb675a7160ee87c 100644 (file)
@@ -16,6 +16,8 @@
 
 #define ASPEED_NUM_CLKS                35
 
+#define ASPEED_RESET2_OFFSET   32
+
 #define ASPEED_RESET_CTRL      0x04
 #define ASPEED_CLK_SELECTION   0x08
 #define ASPEED_CLK_STOP_CTRL   0x0c
@@ -30,6 +32,7 @@
 #define  CLKIN_25MHZ_EN                BIT(23)
 #define  AST2400_CLK_SOURCE_SEL        BIT(18)
 #define ASPEED_CLK_SELECTION_2 0xd8
+#define ASPEED_RESET_CTRL2     0xd4
 
 /* Globally visible clocks */
 static DEFINE_SPINLOCK(aspeed_clk_lock);
@@ -88,7 +91,7 @@ static const struct aspeed_gate_data aspeed_gates[] = {
        [ASPEED_CLK_GATE_GCLK] =        {  1,  7, "gclk-gate",          NULL,   0 }, /* 2D engine */
        [ASPEED_CLK_GATE_MCLK] =        {  2, -1, "mclk-gate",          "mpll", CLK_IS_CRITICAL }, /* SDRAM */
        [ASPEED_CLK_GATE_VCLK] =        {  3,  6, "vclk-gate",          NULL,   0 }, /* Video Capture */
-       [ASPEED_CLK_GATE_BCLK] =        {  4, 10, "bclk-gate",          "bclk", 0 }, /* PCIe/PCI */
+       [ASPEED_CLK_GATE_BCLK] =        {  4,  8, "bclk-gate",          "bclk", 0 }, /* PCIe/PCI */
        [ASPEED_CLK_GATE_DCLK] =        {  5, -1, "dclk-gate",          NULL,   0 }, /* DAC */
        [ASPEED_CLK_GATE_REFCLK] =      {  6, -1, "refclk-gate",        "clkin", CLK_IS_CRITICAL },
        [ASPEED_CLK_GATE_USBPORT2CLK] = {  7,  3, "usb-port2-gate",     NULL,   0 }, /* USB2.0 Host port 2 */
@@ -291,47 +294,72 @@ struct aspeed_reset {
 #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
 
 static const u8 aspeed_resets[] = {
+       /* SCU04 resets */
        [ASPEED_RESET_XDMA]     = 25,
        [ASPEED_RESET_MCTP]     = 24,
        [ASPEED_RESET_ADC]      = 23,
        [ASPEED_RESET_JTAG_MASTER] = 22,
        [ASPEED_RESET_MIC]      = 18,
        [ASPEED_RESET_PWM]      =  9,
-       [ASPEED_RESET_PCIVGA]   =  8,
+       [ASPEED_RESET_PECI]     = 10,
        [ASPEED_RESET_I2C]      =  2,
        [ASPEED_RESET_AHB]      =  1,
+
+       /*
+        * SCUD4 resets start at an offset to separate them from
+        * the SCU04 resets.
+        */
+       [ASPEED_RESET_CRT1]     = ASPEED_RESET2_OFFSET + 5,
 };
 
 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
                                 unsigned long id)
 {
        struct aspeed_reset *ar = to_aspeed_reset(rcdev);
-       u32 rst = BIT(aspeed_resets[id]);
+       u32 reg = ASPEED_RESET_CTRL;
+       u32 bit = aspeed_resets[id];
+
+       if (bit >= ASPEED_RESET2_OFFSET) {
+               bit -= ASPEED_RESET2_OFFSET;
+               reg = ASPEED_RESET_CTRL2;
+       }
 
-       return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0);
+       return regmap_update_bits(ar->map, reg, BIT(bit), 0);
 }
 
 static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
                               unsigned long id)
 {
        struct aspeed_reset *ar = to_aspeed_reset(rcdev);
-       u32 rst = BIT(aspeed_resets[id]);
+       u32 reg = ASPEED_RESET_CTRL;
+       u32 bit = aspeed_resets[id];
 
-       return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst);
+       if (bit >= ASPEED_RESET2_OFFSET) {
+               bit -= ASPEED_RESET2_OFFSET;
+               reg = ASPEED_RESET_CTRL2;
+       }
+
+       return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit));
 }
 
 static int aspeed_reset_status(struct reset_controller_dev *rcdev,
                               unsigned long id)
 {
        struct aspeed_reset *ar = to_aspeed_reset(rcdev);
-       u32 val, rst = BIT(aspeed_resets[id]);
-       int ret;
+       u32 reg = ASPEED_RESET_CTRL;
+       u32 bit = aspeed_resets[id];
+       int ret, val;
+
+       if (bit >= ASPEED_RESET2_OFFSET) {
+               bit -= ASPEED_RESET2_OFFSET;
+               reg = ASPEED_RESET_CTRL2;
+       }
 
-       ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val);
+       ret = regmap_read(ar->map, reg, &val);
        if (ret)
                return ret;
 
-       return !!(val & rst);
+       return !!(val & BIT(bit));
 }
 
 static const struct reset_control_ops aspeed_reset_ops = {
diff --git a/drivers/clk/clk-npcm7xx.c b/drivers/clk/clk-npcm7xx.c
new file mode 100644 (file)
index 0000000..740af90
--- /dev/null
@@ -0,0 +1,656 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Nuvoton NPCM7xx Clock Generator
+ * All the clocks are initialized by the bootloader, so this driver allow only
+ * reading of current settings directly from the hardware.
+ *
+ * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
+ */
+
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/bitfield.h>
+
+#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
+
+struct npcm7xx_clk_pll {
+       struct clk_hw   hw;
+       void __iomem    *pllcon;
+       u8              flags;
+};
+
+#define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw)
+
+#define PLLCON_LOKI    BIT(31)
+#define PLLCON_LOKS    BIT(30)
+#define PLLCON_FBDV    GENMASK(27, 16)
+#define PLLCON_OTDV2   GENMASK(15, 13)
+#define PLLCON_PWDEN   BIT(12)
+#define PLLCON_OTDV1   GENMASK(10, 8)
+#define PLLCON_INDV    GENMASK(5, 0)
+
+static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw,
+                                                unsigned long parent_rate)
+{
+       struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw);
+       unsigned long fbdv, indv, otdv1, otdv2;
+       unsigned int val;
+       u64 ret;
+
+       if (parent_rate == 0) {
+               pr_err("%s: parent rate is zero", __func__);
+               return 0;
+       }
+
+       val = readl_relaxed(pll->pllcon);
+
+       indv = FIELD_GET(PLLCON_INDV, val);
+       fbdv = FIELD_GET(PLLCON_FBDV, val);
+       otdv1 = FIELD_GET(PLLCON_OTDV1, val);
+       otdv2 = FIELD_GET(PLLCON_OTDV2, val);
+
+       ret = (u64)parent_rate * fbdv;
+       do_div(ret, indv * otdv1 * otdv2);
+
+       return ret;
+}
+
+static const struct clk_ops npcm7xx_clk_pll_ops = {
+       .recalc_rate = npcm7xx_clk_pll_recalc_rate,
+};
+
+static struct clk_hw *
+npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name,
+                        const char *parent_name, unsigned long flags)
+{
+       struct npcm7xx_clk_pll *pll;
+       struct clk_init_data init;
+       struct clk_hw *hw;
+       int ret;
+
+       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+       if (!pll)
+               return ERR_PTR(-ENOMEM);
+
+       pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
+
+       init.name = name;
+       init.ops = &npcm7xx_clk_pll_ops;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+       init.flags = flags;
+
+       pll->pllcon = pllcon;
+       pll->hw.init = &init;
+
+       hw = &pll->hw;
+
+       ret = clk_hw_register(NULL, hw);
+       if (ret) {
+               kfree(pll);
+               hw = ERR_PTR(ret);
+       }
+
+       return hw;
+}
+
+#define NPCM7XX_CLKEN1          (0x00)
+#define NPCM7XX_CLKEN2          (0x28)
+#define NPCM7XX_CLKEN3          (0x30)
+#define NPCM7XX_CLKSEL          (0x04)
+#define NPCM7XX_CLKDIV1         (0x08)
+#define NPCM7XX_CLKDIV2         (0x2C)
+#define NPCM7XX_CLKDIV3         (0x58)
+#define NPCM7XX_PLLCON0         (0x0C)
+#define NPCM7XX_PLLCON1         (0x10)
+#define NPCM7XX_PLLCON2         (0x54)
+#define NPCM7XX_SWRSTR          (0x14)
+#define NPCM7XX_IRQWAKECON      (0x18)
+#define NPCM7XX_IRQWAKEFLAG     (0x1C)
+#define NPCM7XX_IPSRST1         (0x20)
+#define NPCM7XX_IPSRST2         (0x24)
+#define NPCM7XX_IPSRST3         (0x34)
+#define NPCM7XX_WD0RCR          (0x38)
+#define NPCM7XX_WD1RCR          (0x3C)
+#define NPCM7XX_WD2RCR          (0x40)
+#define NPCM7XX_SWRSTC1         (0x44)
+#define NPCM7XX_SWRSTC2         (0x48)
+#define NPCM7XX_SWRSTC3         (0x4C)
+#define NPCM7XX_SWRSTC4         (0x50)
+#define NPCM7XX_CORSTC          (0x5C)
+#define NPCM7XX_PLLCONG         (0x60)
+#define NPCM7XX_AHBCKFI         (0x64)
+#define NPCM7XX_SECCNT          (0x68)
+#define NPCM7XX_CNTR25M         (0x6C)
+
+struct npcm7xx_clk_gate_data {
+       u32 reg;
+       u8 bit_idx;
+       const char *name;
+       const char *parent_name;
+       unsigned long flags;
+       /*
+        * If this clock is exported via DT, set onecell_idx to constant
+        * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
+        * this specific clock.  Otherwise, set to -1.
+        */
+       int onecell_idx;
+};
+
+struct npcm7xx_clk_mux_data {
+       u8 shift;
+       u8 mask;
+       u32 *table;
+       const char *name;
+       const char * const *parent_names;
+       u8 num_parents;
+       unsigned long flags;
+       /*
+        * If this clock is exported via DT, set onecell_idx to constant
+        * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
+        * this specific clock.  Otherwise, set to -1.
+        */
+       int onecell_idx;
+
+};
+
+struct npcm7xx_clk_div_fixed_data {
+       u8 mult;
+       u8 div;
+       const char *name;
+       const char *parent_name;
+       u8 clk_divider_flags;
+       /*
+        * If this clock is exported via DT, set onecell_idx to constant
+        * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
+        * this specific clock.  Otherwise, set to -1.
+        */
+       int onecell_idx;
+};
+
+
+struct npcm7xx_clk_div_data {
+       u32 reg;
+       u8 shift;
+       u8 width;
+       const char *name;
+       const char *parent_name;
+       u8 clk_divider_flags;
+       unsigned long flags;
+       /*
+        * If this clock is exported via DT, set onecell_idx to constant
+        * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
+        * this specific clock.  Otherwise, set to -1.
+        */
+       int onecell_idx;
+};
+
+struct npcm7xx_clk_pll_data {
+       u32 reg;
+       const char *name;
+       const char *parent_name;
+       unsigned long flags;
+       /*
+        * If this clock is exported via DT, set onecell_idx to constant
+        * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
+        * this specific clock.  Otherwise, set to -1.
+        */
+       int onecell_idx;
+};
+
+/*
+ * Single copy of strings used to refer to clocks within this driver indexed by
+ * above enum.
+ */
+#define NPCM7XX_CLK_S_REFCLK      "refclk"
+#define NPCM7XX_CLK_S_SYSBYPCK    "sysbypck"
+#define NPCM7XX_CLK_S_MCBYPCK     "mcbypck"
+#define NPCM7XX_CLK_S_GFXBYPCK    "gfxbypck"
+#define NPCM7XX_CLK_S_PLL0        "pll0"
+#define NPCM7XX_CLK_S_PLL1        "pll1"
+#define NPCM7XX_CLK_S_PLL1_DIV2   "pll1_div2"
+#define NPCM7XX_CLK_S_PLL2        "pll2"
+#define NPCM7XX_CLK_S_PLL_GFX     "pll_gfx"
+#define NPCM7XX_CLK_S_PLL2_DIV2   "pll2_div2"
+#define NPCM7XX_CLK_S_PIX_MUX     "gfx_pixel"
+#define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
+#define NPCM7XX_CLK_S_MC_MUX      "mc_phy"
+#define NPCM7XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/
+#define NPCM7XX_CLK_S_MC          "mc"
+#define NPCM7XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
+#define NPCM7XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/
+#define NPCM7XX_CLK_S_CLKOUT_MUX  "clkout_mux"
+#define NPCM7XX_CLK_S_UART_MUX    "uart_mux"
+#define NPCM7XX_CLK_S_TIM_MUX     "timer_mux"
+#define NPCM7XX_CLK_S_SD_MUX      "sd_mux"
+#define NPCM7XX_CLK_S_GFXM_MUX    "gfxm_mux"
+#define NPCM7XX_CLK_S_SU_MUX      "serial_usb_mux"
+#define NPCM7XX_CLK_S_DVC_MUX     "dvc_mux"
+#define NPCM7XX_CLK_S_GFX_MUX     "gfx_mux"
+#define NPCM7XX_CLK_S_GFX_PIXEL   "gfx_pixel"
+#define NPCM7XX_CLK_S_SPI0        "spi0"
+#define NPCM7XX_CLK_S_SPI3        "spi3"
+#define NPCM7XX_CLK_S_SPIX        "spix"
+#define NPCM7XX_CLK_S_APB1        "apb1"
+#define NPCM7XX_CLK_S_APB2        "apb2"
+#define NPCM7XX_CLK_S_APB3        "apb3"
+#define NPCM7XX_CLK_S_APB4        "apb4"
+#define NPCM7XX_CLK_S_APB5        "apb5"
+#define NPCM7XX_CLK_S_TOCK        "tock"
+#define NPCM7XX_CLK_S_CLKOUT      "clkout"
+#define NPCM7XX_CLK_S_UART        "uart"
+#define NPCM7XX_CLK_S_TIMER       "timer"
+#define NPCM7XX_CLK_S_MMC         "mmc"
+#define NPCM7XX_CLK_S_SDHC        "sdhc"
+#define NPCM7XX_CLK_S_ADC         "adc"
+#define NPCM7XX_CLK_S_GFX         "gfx0_gfx1_mem"
+#define NPCM7XX_CLK_S_USBIF       "serial_usbif"
+#define NPCM7XX_CLK_S_USB_HOST    "usb_host"
+#define NPCM7XX_CLK_S_USB_BRIDGE  "usb_bridge"
+#define NPCM7XX_CLK_S_PCI         "pci"
+
+static u32 pll_mux_table[] = {0, 1, 2, 3};
+static const char * const pll_mux_parents[] __initconst = {
+       NPCM7XX_CLK_S_PLL0,
+       NPCM7XX_CLK_S_PLL1_DIV2,
+       NPCM7XX_CLK_S_REFCLK,
+       NPCM7XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 cpuck_mux_table[] = {0, 1, 2, 3};
+static const char * const cpuck_mux_parents[] __initconst = {
+       NPCM7XX_CLK_S_PLL0,
+       NPCM7XX_CLK_S_PLL1_DIV2,
+       NPCM7XX_CLK_S_REFCLK,
+       NPCM7XX_CLK_S_SYSBYPCK,
+};
+
+static u32 pixcksel_mux_table[] = {0, 2};
+static const char * const pixcksel_mux_parents[] __initconst = {
+       NPCM7XX_CLK_S_PLL_GFX,
+       NPCM7XX_CLK_S_REFCLK,
+};
+
+static u32 sucksel_mux_table[] = {2, 3};
+static const char * const sucksel_mux_parents[] __initconst = {
+       NPCM7XX_CLK_S_REFCLK,
+       NPCM7XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 mccksel_mux_table[] = {0, 2, 3};
+static const char * const mccksel_mux_parents[] __initconst = {
+       NPCM7XX_CLK_S_PLL1_DIV2,
+       NPCM7XX_CLK_S_REFCLK,
+       NPCM7XX_CLK_S_MCBYPCK,
+};
+
+static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
+static const char * const clkoutsel_mux_parents[] __initconst = {
+       NPCM7XX_CLK_S_PLL0,
+       NPCM7XX_CLK_S_PLL1_DIV2,
+       NPCM7XX_CLK_S_REFCLK,
+       NPCM7XX_CLK_S_PLL_GFX, // divided by 2
+       NPCM7XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 gfxmsel_mux_table[] = {2, 3};
+static const char * const gfxmsel_mux_parents[] __initconst = {
+       NPCM7XX_CLK_S_REFCLK,
+       NPCM7XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 dvcssel_mux_table[] = {2, 3};
+static const char * const dvcssel_mux_parents[] __initconst = {
+       NPCM7XX_CLK_S_REFCLK,
+       NPCM7XX_CLK_S_PLL2,
+};
+
+static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = {
+       {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1},
+
+       {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1,
+       NPCM7XX_CLK_S_REFCLK, 0, -1},
+
+       {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2,
+       NPCM7XX_CLK_S_REFCLK, 0, -1},
+
+       {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX,
+       NPCM7XX_CLK_S_REFCLK, 0, -1},
+};
+
+static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = {
+       {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX,
+       cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
+       NPCM7XX_CLK_CPU},
+
+       {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX,
+       pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
+       NPCM7XX_CLK_GFX_PIXEL},
+
+       {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX,
+       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+       {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX,
+       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+       {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,
+       sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
+
+       {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX,
+       mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
+
+       {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX,
+       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+       {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX,
+       pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+       {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX,
+       clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
+
+       {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX,
+       gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
+
+       {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX,
+       dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
+};
+
+/* fixed ratio dividers (no register): */
+static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = {
+       { 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC},
+       { 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1},
+       { 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1},
+};
+
+/* configurable dividers: */
+static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = {
+       {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC,
+       NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC},
+       /*30-28 ADCCKDIV*/
+       {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB,
+       NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB},
+       /*27-26 CLK4DIV*/
+       {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER,
+       NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER},
+       /*25-21 TIMCKDIV*/
+       {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART,
+       NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART},
+       /*20-16 UARTDIV*/
+       {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC,
+       NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC},
+       /*15-11 MMCCKDIV*/
+       {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3,
+       NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3},
+       /*10-6 AHB3CKDIV*/
+       {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI,
+       NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI},
+       /*5-2 PCICKDIV*/
+       {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI,
+       NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL,
+       NPCM7XX_CLK_AXI},/*0 CLK2DIV*/
+
+       {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4,
+       NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4},
+       /*31-30 APB4CKDIV*/
+       {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3,
+       NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3},
+       /*29-28 APB3CKDIV*/
+       {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2,
+       NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2},
+       /*27-26 APB2CKDIV*/
+       {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1,
+       NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1},
+       /*25-24 APB1CKDIV*/
+       {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5,
+       NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5},
+       /*23-22 APB5CKDIV*/
+       {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT,
+       NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT},
+       /*20-16 CLKOUTDIV*/
+       {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX,
+       NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX},
+       /*15-13 GFXCKDIV*/
+       {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE,
+       NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU},
+       /*12-8 SUCKDIV*/
+       {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST,
+       NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48},
+       /*7-4 SU48CKDIV*/
+       {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC,
+       NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC}
+       ,/*3-0 SD1CKDIV*/
+
+       {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0,
+       NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0},
+       /*10-6 SPI0CKDV*/
+       {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX,
+       NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX},
+       /*5-1 SPIXCKDV*/
+
+};
+
+static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = {
+       {NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0},
+       {NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0},
+       {NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0},
+       {NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0},
+       {NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0},
+       {NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0},
+       /* bit 3 is reserved */
+       {NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0},
+
+       {NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0},
+       /* bit 29 is reserved */
+       {NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0},
+       {NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0},
+       /* bit 24 is reserved */
+       {NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0},
+       {NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0},
+       {NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0},
+       /* bit 20 is reserved */
+       {NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0},
+       {NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0},
+       /* bit 17 is reserved */
+       {NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0},
+       /*  bit 15 is reserved */
+       {NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0},
+       {NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0},
+       {NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0},
+       {NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0},
+       {NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0},
+       {NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0},
+       {NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0},
+       {NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0},
+
+       {NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0},
+       {NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0},
+       /* bit 11 is reserved */
+       /* bit 10 is reserved */
+       {NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0},
+       /* bit 8 is reserved */
+       {NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0},
+       {NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0},
+       {NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0},
+};
+
+static DEFINE_SPINLOCK(npcm7xx_clk_lock);
+
+static void __init npcm7xx_clk_init(struct device_node *clk_np)
+{
+       struct clk_hw_onecell_data *npcm7xx_clk_data;
+       void __iomem *clk_base;
+       struct resource res;
+       struct clk_hw *hw;
+       int ret;
+       int i;
+
+       ret = of_address_to_resource(clk_np, 0, &res);
+       if (ret) {
+               pr_err("%s: failed to get resource, ret %d\n", clk_np->name,
+                       ret);
+               return;
+       }
+
+       clk_base = ioremap(res.start, resource_size(&res));
+       if (!clk_base)
+               goto npcm7xx_init_error;
+
+       npcm7xx_clk_data = kzalloc(sizeof(*npcm7xx_clk_data->hws) *
+               NPCM7XX_NUM_CLOCKS + sizeof(npcm7xx_clk_data), GFP_KERNEL);
+       if (!npcm7xx_clk_data)
+               goto npcm7xx_init_np_err;
+
+       npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS;
+
+       for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++)
+               npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+       /* Register plls */
+       for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) {
+               const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i];
+
+               hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg,
+                       pll_data->name, pll_data->parent_name, pll_data->flags);
+               if (IS_ERR(hw)) {
+                       pr_err("npcm7xx_clk: Can't register pll\n");
+                       goto npcm7xx_init_fail;
+               }
+
+               if (pll_data->onecell_idx >= 0)
+                       npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw;
+       }
+
+       /* Register fixed dividers */
+       hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2,
+                       NPCM7XX_CLK_S_PLL1, 0, 1, 2);
+       if (IS_ERR(hw)) {
+               pr_err("npcm7xx_clk: Can't register fixed div\n");
+               goto npcm7xx_init_fail;
+       }
+
+       hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2,
+                       NPCM7XX_CLK_S_PLL2, 0, 1, 2);
+       if (IS_ERR(hw)) {
+               pr_err("npcm7xx_clk: Can't register div2\n");
+               goto npcm7xx_init_fail;
+       }
+
+       /* Register muxes */
+       for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) {
+               const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i];
+
+               hw = clk_hw_register_mux_table(NULL,
+                       mux_data->name,
+                       mux_data->parent_names, mux_data->num_parents,
+                       mux_data->flags, clk_base + NPCM7XX_CLKSEL,
+                       mux_data->shift, mux_data->mask, 0,
+                       mux_data->table, &npcm7xx_clk_lock);
+
+               if (IS_ERR(hw)) {
+                       pr_err("npcm7xx_clk: Can't register mux\n");
+                       goto npcm7xx_init_fail;
+               }
+
+               if (mux_data->onecell_idx >= 0)
+                       npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw;
+       }
+
+       /* Register clock dividers specified in npcm7xx_divs */
+       for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) {
+               const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i];
+
+               hw = clk_hw_register_divider(NULL, div_data->name,
+                               div_data->parent_name,
+                               div_data->flags,
+                               clk_base + div_data->reg,
+                               div_data->shift, div_data->width,
+                               div_data->clk_divider_flags, &npcm7xx_clk_lock);
+               if (IS_ERR(hw)) {
+                       pr_err("npcm7xx_clk: Can't register div table\n");
+                       goto npcm7xx_init_fail;
+               }
+
+               if (div_data->onecell_idx >= 0)
+                       npcm7xx_clk_data->hws[div_data->onecell_idx] = hw;
+       }
+
+       ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
+                                       npcm7xx_clk_data);
+       if (ret)
+               pr_err("failed to add DT provider: %d\n", ret);
+
+       of_node_put(clk_np);
+
+       return;
+
+npcm7xx_init_fail:
+       kfree(npcm7xx_clk_data->hws);
+npcm7xx_init_np_err:
+       iounmap(clk_base);
+npcm7xx_init_error:
+       of_node_put(clk_np);
+}
+CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);
index f1d5967b4b39a8daeec89f47291ec9d25339832f..e68cb478f21f75e5da3557747541a0e0d13f35b7 100644 (file)
@@ -216,7 +216,7 @@ static const char * const usart1_src[] = {
        "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
 };
 
-const char * const usart234578_src[] = {
+static const char * const usart234578_src[] = {
        "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 };
 
@@ -224,10 +224,6 @@ static const char * const usart6_src[] = {
        "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 };
 
-static const char * const dfsdm_src[] = {
-       "pclk2", "ck_mcu"
-};
-
 static const char * const fdcan_src[] = {
        "ck_hse", "pll3_q", "pll4_q"
 };
@@ -316,10 +312,8 @@ struct stm32_clk_mgate {
 struct clock_config {
        u32 id;
        const char *name;
-       union {
-               const char *parent_name;
-               const char * const *parent_names;
-       };
+       const char *parent_name;
+       const char * const *parent_names;
        int num_parents;
        unsigned long flags;
        void *cfg;
@@ -469,7 +463,7 @@ static void mp1_gate_clk_disable(struct clk_hw *hw)
        }
 }
 
-const struct clk_ops mp1_gate_clk_ops = {
+static const struct clk_ops mp1_gate_clk_ops = {
        .enable         = mp1_gate_clk_enable,
        .disable        = mp1_gate_clk_disable,
        .is_enabled     = clk_gate_is_enabled,
@@ -585,14 +579,9 @@ clk_stm32_register_gate_ops(struct device *dev,
                            spinlock_t *lock)
 {
        struct clk_init_data init = { NULL };
-       struct clk_gate *gate;
        struct clk_hw *hw;
        int ret;
 
-       gate = kzalloc(sizeof(*gate), GFP_KERNEL);
-       if (!gate)
-               return ERR_PTR(-ENOMEM);
-
        init.name = name;
        init.parent_names = &parent_name;
        init.num_parents = 1;
@@ -610,10 +599,8 @@ clk_stm32_register_gate_ops(struct device *dev,
        hw->init = &init;
 
        ret = clk_hw_register(dev, hw);
-       if (ret) {
-               kfree(gate);
+       if (ret)
                hw = ERR_PTR(ret);
-       }
 
        return hw;
 }
@@ -698,7 +685,7 @@ static void mp1_mgate_clk_disable(struct clk_hw *hw)
                mp1_gate_clk_disable(hw);
 }
 
-const struct clk_ops mp1_mgate_clk_ops = {
+static const struct clk_ops mp1_mgate_clk_ops = {
        .enable         = mp1_mgate_clk_enable,
        .disable        = mp1_mgate_clk_disable,
        .is_enabled     = clk_gate_is_enabled,
@@ -732,7 +719,7 @@ static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
        return 0;
 }
 
-const struct clk_ops clk_mmux_ops = {
+static const struct clk_ops clk_mmux_ops = {
        .get_parent     = clk_mmux_get_parent,
        .set_parent     = clk_mmux_set_parent,
        .determine_rate = __clk_mux_determine_rate,
@@ -1048,10 +1035,10 @@ struct stm32_pll_cfg {
        u32 offset;
 };
 
-struct clk_hw *_clk_register_pll(struct device *dev,
-                                struct clk_hw_onecell_data *clk_data,
-                                void __iomem *base, spinlock_t *lock,
-                                const struct clock_config *cfg)
+static struct clk_hw *_clk_register_pll(struct device *dev,
+                                       struct clk_hw_onecell_data *clk_data,
+                                       void __iomem *base, spinlock_t *lock,
+                                       const struct clock_config *cfg)
 {
        struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
 
@@ -1405,7 +1392,8 @@ enum {
        G_USBH,
        G_ETHSTP,
        G_RTCAPB,
-       G_TZC,
+       G_TZC1,
+       G_TZC2,
        G_TZPC,
        G_IWDG1,
        G_BSEC,
@@ -1417,7 +1405,7 @@ enum {
        G_LAST
 };
 
-struct stm32_mgate mp1_mgate[G_LAST];
+static struct stm32_mgate mp1_mgate[G_LAST];
 
 #define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
               _mgate, _ops)\
@@ -1440,7 +1428,7 @@ struct stm32_mgate mp1_mgate[G_LAST];
               &mp1_mgate[_id], &mp1_mgate_clk_ops)
 
 /* Peripheral gates */
-struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
+static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
        /* Multi gates */
        K_GATE(G_MDIO,          RCC_APB1ENSETR, 31, 0),
        K_MGATE(G_DAC12,        RCC_APB1ENSETR, 29, 0),
@@ -1506,7 +1494,8 @@ struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
        K_GATE(G_BSEC,          RCC_APB5ENSETR, 16, 0),
        K_GATE(G_IWDG1,         RCC_APB5ENSETR, 15, 0),
        K_GATE(G_TZPC,          RCC_APB5ENSETR, 13, 0),
-       K_GATE(G_TZC,           RCC_APB5ENSETR, 12, 0),
+       K_GATE(G_TZC2,          RCC_APB5ENSETR, 12, 0),
+       K_GATE(G_TZC1,          RCC_APB5ENSETR, 11, 0),
        K_GATE(G_RTCAPB,        RCC_APB5ENSETR, 8, 0),
        K_MGATE(G_USART1,       RCC_APB5ENSETR, 4, 0),
        K_MGATE(G_I2C6,         RCC_APB5ENSETR, 3, 0),
@@ -1600,7 +1589,7 @@ enum {
        M_LAST
 };
 
-struct stm32_mmux ker_mux[M_LAST];
+static struct stm32_mmux ker_mux[M_LAST];
 
 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
        [_id] = {\
@@ -1623,7 +1612,7 @@ struct stm32_mmux ker_mux[M_LAST];
        _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
                        &ker_mux[_id], &clk_mmux_ops)
 
-const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
+static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
        /* Kernel multi mux */
        K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
        K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
@@ -1860,7 +1849,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
        PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
        PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
             CLK_IS_CRITICAL, G_RTCAPB),
-       PCLK(TZC, "tzc", "pclk5", CLK_IGNORE_UNUSED, G_TZC),
+       PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
+       PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
        PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
        PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
        PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
@@ -1916,8 +1906,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
        KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
        KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
        KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
-       KCLK(STGEN_K, "stgen_k",  stgen_src, CLK_IGNORE_UNUSED,
-            G_STGEN, M_STGEN),
+       KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
        KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
        KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
        KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
@@ -1948,8 +1937,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
        KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
        KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
        KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
-       KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI2, M_SAI3),
-       KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI2, M_SAI4),
+       KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
+       KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
        KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
        KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
        KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
@@ -1992,11 +1981,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
                  _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
 
        /* Debug clocks */
-       FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
-
-       GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
-
-       GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
+       GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
+            RCC_DBGCFGR, 8, 0),
 
        COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
                  _GATE(RCC_DBGCFGR, 9, 0),
index ea67ac81c6f97db113cef4977936776d1673ae3f..9cd7cae221ddaa19f2472d7faa6067113a4eaf89 100644 (file)
@@ -548,7 +548,8 @@ static void clk_core_rate_unprotect(struct clk_core *core)
        if (!core)
                return;
 
-       if (WARN_ON(core->protect_count == 0))
+       if (WARN(core->protect_count == 0,
+           "%s already unprotected\n", core->name))
                return;
 
        if (--core->protect_count > 0)
@@ -681,16 +682,18 @@ static void clk_core_unprepare(struct clk_core *core)
        if (!core)
                return;
 
-       if (WARN_ON(core->prepare_count == 0))
+       if (WARN(core->prepare_count == 0,
+           "%s already unprepared\n", core->name))
                return;
 
-       if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL))
+       if (WARN(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL,
+           "Unpreparing critical %s\n", core->name))
                return;
 
        if (--core->prepare_count > 0)
                return;
 
-       WARN_ON(core->enable_count > 0);
+       WARN(core->enable_count > 0, "Unpreparing enabled %s\n", core->name);
 
        trace_clk_unprepare(core);
 
@@ -808,10 +811,11 @@ static void clk_core_disable(struct clk_core *core)
        if (!core)
                return;
 
-       if (WARN_ON(core->enable_count == 0))
+       if (WARN(core->enable_count == 0, "%s already disabled\n", core->name))
                return;
 
-       if (WARN_ON(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL))
+       if (WARN(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL,
+           "Disabling critical %s\n", core->name))
                return;
 
        if (--core->enable_count > 0)
@@ -866,7 +870,8 @@ static int clk_core_enable(struct clk_core *core)
        if (!core)
                return 0;
 
-       if (WARN_ON(core->prepare_count == 0))
+       if (WARN(core->prepare_count == 0,
+           "Enabling unprepared %s\n", core->name))
                return -ESHUTDOWN;
 
        if (core->enable_count == 0) {
@@ -3906,7 +3911,7 @@ int of_clk_parent_fill(struct device_node *np, const char **parents,
 EXPORT_SYMBOL_GPL(of_clk_parent_fill);
 
 struct clock_provider {
-       of_clk_init_cb_t clk_init_cb;
+       void (*clk_init_cb)(struct device_node *);
        struct device_node *np;
        struct list_head node;
 };
index fbf4532f94b8cc03fbf5c7ed26ed9cb532635637..e42e1afb0c519b2752e8511db39f6dc6a585c41f 100644 (file)
@@ -218,6 +218,14 @@ config MSM_MMCC_8996
          Say Y if you want to support multimedia devices such as display,
          graphics, video encode/decode, camera, etc.
 
+config MSM_GCC_8998
+       tristate "MSM8998 Global Clock Controller"
+       depends on COMMON_CLK_QCOM
+       help
+         Support for the global clock controller on msm8998 devices.
+         Say Y if you want to use peripheral devices such as UART, SPI,
+         i2c, USB, UFS, SD/eMMC, PCIe, etc.
+
 config SPMI_PMIC_CLKDIV
        tristate "SPMI PMIC clkdiv Support"
        depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
index 230332cf317e58e35f180c6febcc5d515df46384..7c09ab1a640c12e0cc4293baee611ef5dff2ef7c 100644 (file)
@@ -30,6 +30,7 @@ obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
 obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
 obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
 obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
+obj-$(CONFIG_MSM_GCC_8998) += gcc-msm8998.o
 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
index bbeaf9c09dbb4750cd6479ae16ab416626a19731..ec6cee8ff1bc3f059bd6a9b61b6bd65f6d117465 100644 (file)
@@ -211,6 +211,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
        clk_flags = clk_hw_get_flags(hw);
        p = clk_hw_get_parent_by_index(hw, index);
        if (clk_flags & CLK_SET_RATE_PARENT) {
+               rate = f->freq;
                if (f->pre_div) {
                        rate /= 2;
                        rate *= f->pre_div + 1;
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
new file mode 100644 (file)
index 0000000..78d87f5
--- /dev/null
@@ -0,0 +1,2834 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-msm8998.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-alpha-pll.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+#include "gdsc.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+       P_AUD_REF_CLK,
+       P_CORE_BI_PLL_TEST_SE,
+       P_GPLL0_OUT_MAIN,
+       P_GPLL4_OUT_MAIN,
+       P_PLL0_EARLY_DIV_CLK_SRC,
+       P_SLEEP_CLK,
+       P_XO,
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+       { P_XO, 0 },
+       { P_GPLL0_OUT_MAIN, 1 },
+       { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
+       { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_0[] = {
+       "xo",
+       "gpll0_out_main",
+       "gpll0_out_main",
+       "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+       { P_XO, 0 },
+       { P_GPLL0_OUT_MAIN, 1 },
+       { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_1[] = {
+       "xo",
+       "gpll0_out_main",
+       "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+       { P_XO, 0 },
+       { P_GPLL0_OUT_MAIN, 1 },
+       { P_SLEEP_CLK, 5 },
+       { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
+       { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_2[] = {
+       "xo",
+       "gpll0_out_main",
+       "core_pi_sleep_clk",
+       "gpll0_out_main",
+       "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+       { P_XO, 0 },
+       { P_SLEEP_CLK, 5 },
+       { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_3[] = {
+       "xo",
+       "core_pi_sleep_clk",
+       "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_4[] = {
+       { P_XO, 0 },
+       { P_GPLL0_OUT_MAIN, 1 },
+       { P_GPLL4_OUT_MAIN, 5 },
+       { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_4[] = {
+       "xo",
+       "gpll0_out_main",
+       "gpll4_out_main",
+       "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_5[] = {
+       { P_XO, 0 },
+       { P_GPLL0_OUT_MAIN, 1 },
+       { P_AUD_REF_CLK, 2 },
+       { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_5[] = {
+       "xo",
+       "gpll0_out_main",
+       "aud_ref_clk",
+       "core_bi_pll_test_se",
+};
+
+static struct pll_vco fabia_vco[] = {
+       { 250000000, 2000000000, 0 },
+       { 125000000, 1000000000, 1 },
+};
+
+static struct clk_alpha_pll gpll0 = {
+       .offset = 0x0,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .vco_table = fabia_vco,
+       .num_vco = ARRAY_SIZE(fabia_vco),
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gpll0",
+                       .parent_names = (const char *[]){ "xo" },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_ops,
+               }
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_even = {
+       .offset = 0x0,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll0_out_even",
+               .parent_names = (const char *[]){ "gpll0" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_main = {
+       .offset = 0x0,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll0_out_main",
+               .parent_names = (const char *[]){ "gpll0" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_odd = {
+       .offset = 0x0,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll0_out_odd",
+               .parent_names = (const char *[]){ "gpll0" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_test = {
+       .offset = 0x0,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll0_out_test",
+               .parent_names = (const char *[]){ "gpll0" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll gpll1 = {
+       .offset = 0x1000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .vco_table = fabia_vco,
+       .num_vco = ARRAY_SIZE(fabia_vco),
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(1),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gpll1",
+                       .parent_names = (const char *[]){ "xo" },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_ops,
+               }
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll1_out_even = {
+       .offset = 0x1000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll1_out_even",
+               .parent_names = (const char *[]){ "gpll1" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll1_out_main = {
+       .offset = 0x1000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll1_out_main",
+               .parent_names = (const char *[]){ "gpll1" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll1_out_odd = {
+       .offset = 0x1000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll1_out_odd",
+               .parent_names = (const char *[]){ "gpll1" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll1_out_test = {
+       .offset = 0x1000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll1_out_test",
+               .parent_names = (const char *[]){ "gpll1" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll gpll2 = {
+       .offset = 0x2000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .vco_table = fabia_vco,
+       .num_vco = ARRAY_SIZE(fabia_vco),
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(2),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gpll2",
+                       .parent_names = (const char *[]){ "xo" },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_ops,
+               }
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll2_out_even = {
+       .offset = 0x2000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll2_out_even",
+               .parent_names = (const char *[]){ "gpll2" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll2_out_main = {
+       .offset = 0x2000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll2_out_main",
+               .parent_names = (const char *[]){ "gpll2" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll2_out_odd = {
+       .offset = 0x2000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll2_out_odd",
+               .parent_names = (const char *[]){ "gpll2" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll2_out_test = {
+       .offset = 0x2000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll2_out_test",
+               .parent_names = (const char *[]){ "gpll2" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll gpll3 = {
+       .offset = 0x3000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .vco_table = fabia_vco,
+       .num_vco = ARRAY_SIZE(fabia_vco),
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(3),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gpll3",
+                       .parent_names = (const char *[]){ "xo" },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_ops,
+               }
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll3_out_even = {
+       .offset = 0x3000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll3_out_even",
+               .parent_names = (const char *[]){ "gpll3" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll3_out_main = {
+       .offset = 0x3000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll3_out_main",
+               .parent_names = (const char *[]){ "gpll3" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll3_out_odd = {
+       .offset = 0x3000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll3_out_odd",
+               .parent_names = (const char *[]){ "gpll3" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll3_out_test = {
+       .offset = 0x3000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll3_out_test",
+               .parent_names = (const char *[]){ "gpll3" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll gpll4 = {
+       .offset = 0x77000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .vco_table = fabia_vco,
+       .num_vco = ARRAY_SIZE(fabia_vco),
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(4),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gpll4",
+                       .parent_names = (const char *[]){ "xo" },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_ops,
+               }
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll4_out_even = {
+       .offset = 0x77000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll4_out_even",
+               .parent_names = (const char *[]){ "gpll4" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll4_out_main = {
+       .offset = 0x77000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll4_out_main",
+               .parent_names = (const char *[]){ "gpll4" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll4_out_odd = {
+       .offset = 0x77000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll4_out_odd",
+               .parent_names = (const char *[]){ "gpll4" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static struct clk_alpha_pll_postdiv gpll4_out_test = {
+       .offset = 0x77000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gpll4_out_test",
+               .parent_names = (const char *[]){ "gpll4" },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+       F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x19020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup1_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
+       F(960000, P_XO, 10, 1, 2),
+       F(4800000, P_XO, 4, 0, 0),
+       F(9600000, P_XO, 2, 0, 0),
+       F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
+       F(19200000, P_XO, 1, 0, 0),
+       F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
+       F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+       .cmd_rcgr = 0x1900c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup1_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x1b020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup2_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+       .cmd_rcgr = 0x1b00c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup2_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x1d020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup3_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+       .cmd_rcgr = 0x1d00c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup3_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x1f020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup4_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+       .cmd_rcgr = 0x1f00c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup4_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x21020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup5_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
+       .cmd_rcgr = 0x2100c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup5_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x23020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup6_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
+       .cmd_rcgr = 0x2300c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_qup6_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
+       F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
+       F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
+       F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
+       F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
+       F(19200000, P_XO, 1, 0, 0),
+       F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
+       F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
+       F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
+       F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
+       F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
+       F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
+       F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
+       F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
+       F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
+       F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+       .cmd_rcgr = 0x1a00c,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_uart1_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+       .cmd_rcgr = 0x1c00c,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_uart2_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
+       .cmd_rcgr = 0x1e00c,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp1_uart3_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x26020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup1_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
+       .cmd_rcgr = 0x2600c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup1_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x28020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup2_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
+       .cmd_rcgr = 0x2800c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup2_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x2a020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup3_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
+       .cmd_rcgr = 0x2a00c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup3_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x2c020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup4_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
+       .cmd_rcgr = 0x2c00c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup4_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x2e020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup5_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
+       .cmd_rcgr = 0x2e00c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup5_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
+       .cmd_rcgr = 0x30020,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup6_i2c_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
+       .cmd_rcgr = 0x3000c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_qup6_spi_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
+       .cmd_rcgr = 0x2700c,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_uart1_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
+       .cmd_rcgr = 0x2900c,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_uart2_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
+       .cmd_rcgr = 0x2b00c,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "blsp2_uart3_apps_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_gp1_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+       F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+       F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+       .cmd_rcgr = 0x64004,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_2,
+       .freq_tbl = ftbl_gp1_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gp1_clk_src",
+               .parent_names = gcc_parent_names_2,
+               .num_parents = 5,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+       .cmd_rcgr = 0x65004,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_2,
+       .freq_tbl = ftbl_gp1_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gp2_clk_src",
+               .parent_names = gcc_parent_names_2,
+               .num_parents = 5,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+       .cmd_rcgr = 0x66004,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_2,
+       .freq_tbl = ftbl_gp1_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gp3_clk_src",
+               .parent_names = gcc_parent_names_2,
+               .num_parents = 5,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+       F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
+       F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 hmss_ahb_clk_src = {
+       .cmd_rcgr = 0x48014,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_hmss_ahb_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "hmss_ahb_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 hmss_rbcpr_clk_src = {
+       .cmd_rcgr = 0x48044,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "hmss_rbcpr_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
+       F(1010526, P_XO, 1, 1, 19),
+       { }
+};
+
+static struct clk_rcg2 pcie_aux_clk_src = {
+       .cmd_rcgr = 0x6c000,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_3,
+       .freq_tbl = ftbl_pcie_aux_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "pcie_aux_clk_src",
+               .parent_names = gcc_parent_names_3,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_pdm2_clk_src[] = {
+       F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 pdm2_clk_src = {
+       .cmd_rcgr = 0x33010,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_pdm2_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "pdm2_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
+       F(144000, P_XO, 16, 3, 25),
+       F(400000, P_XO, 12, 1, 4),
+       F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
+       F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
+       F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+       F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+       F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+       .cmd_rcgr = 0x14010,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_4,
+       .freq_tbl = ftbl_sdcc2_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "sdcc2_apps_clk_src",
+               .parent_names = gcc_parent_names_4,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
+       F(144000, P_XO, 16, 3, 25),
+       F(400000, P_XO, 12, 1, 4),
+       F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
+       F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
+       F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+       F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 sdcc4_apps_clk_src = {
+       .cmd_rcgr = 0x16010,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_sdcc4_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "sdcc4_apps_clk_src",
+               .parent_names = gcc_parent_names_1,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
+       F(105495, P_XO, 1, 1, 182),
+       { }
+};
+
+static struct clk_rcg2 tsif_ref_clk_src = {
+       .cmd_rcgr = 0x36010,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_5,
+       .freq_tbl = ftbl_tsif_ref_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "tsif_ref_clk_src",
+               .parent_names = gcc_parent_names_5,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
+       F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+       F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+       F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 ufs_axi_clk_src = {
+       .cmd_rcgr = 0x75018,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_ufs_axi_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "ufs_axi_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
+       F(19200000, P_XO, 1, 0, 0),
+       F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
+       F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 usb30_master_clk_src = {
+       .cmd_rcgr = 0xf014,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_usb30_master_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "usb30_master_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 usb30_mock_utmi_clk_src = {
+       .cmd_rcgr = 0xf028,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "usb30_mock_utmi_clk_src",
+               .parent_names = gcc_parent_names_0,
+               .num_parents = 4,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
+       F(1200000, P_XO, 16, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 usb3_phy_aux_clk_src = {
+       .cmd_rcgr = 0x5000c,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_3,
+       .freq_tbl = ftbl_usb3_phy_aux_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "usb3_phy_aux_clk_src",
+               .parent_names = gcc_parent_names_3,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_branch gcc_aggre1_noc_xo_clk = {
+       .halt_reg = 0x8202c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x8202c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre1_noc_xo_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_aggre1_ufs_axi_clk = {
+       .halt_reg = 0x82028,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x82028,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre1_ufs_axi_clk",
+                       .parent_names = (const char *[]){
+                               "ufs_axi_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_aggre1_usb3_axi_clk = {
+       .halt_reg = 0x82024,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x82024,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre1_usb3_axi_clk",
+                       .parent_names = (const char *[]){
+                               "usb30_master_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
+       .halt_reg = 0x48090,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x48090,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_apss_qdss_tsctr_div2_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
+       .halt_reg = 0x48094,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x48094,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_apss_qdss_tsctr_div8_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_bimc_hmss_axi_clk = {
+       .halt_reg = 0x48004,
+       .halt_check = BRANCH_HALT_VOTED,
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(22),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_bimc_hmss_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
+       .halt_reg = 0x4401c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x4401c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_bimc_mss_q6_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+       .halt_reg = 0x17004,
+       .halt_check = BRANCH_HALT_VOTED,
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(17),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+       .halt_reg = 0x19008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x19008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup1_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup1_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+       .halt_reg = 0x19004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x19004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup1_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup1_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+       .halt_reg = 0x1b008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x1b008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup2_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup2_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+       .halt_reg = 0x1b004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x1b004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup2_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup2_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+       .halt_reg = 0x1d008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x1d008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup3_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup3_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+       .halt_reg = 0x1d004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x1d004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup3_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup3_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+       .halt_reg = 0x1f008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x1f008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup4_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup4_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+       .halt_reg = 0x1f004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x1f004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup4_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup4_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
+       .halt_reg = 0x21008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x21008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup5_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup5_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
+       .halt_reg = 0x21004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x21004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup5_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup5_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+       .halt_reg = 0x23008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x23008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup6_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup6_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
+       .halt_reg = 0x23004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x23004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_qup6_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_qup6_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_sleep_clk = {
+       .halt_reg = 0x17008,
+       .halt_check = BRANCH_HALT_VOTED,
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(16),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_sleep_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+       .halt_reg = 0x1a004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x1a004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_uart1_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_uart1_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+       .halt_reg = 0x1c004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x1c004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_uart2_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_uart2_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp1_uart3_apps_clk = {
+       .halt_reg = 0x1e004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x1e004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp1_uart3_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp1_uart3_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_ahb_clk = {
+       .halt_reg = 0x25004,
+       .halt_check = BRANCH_HALT_VOTED,
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(15),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
+       .halt_reg = 0x26008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x26008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup1_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup1_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
+       .halt_reg = 0x26004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x26004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup1_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup1_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
+       .halt_reg = 0x28008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x28008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup2_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup2_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
+       .halt_reg = 0x28004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x28004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup2_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup2_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
+       .halt_reg = 0x2a008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x2a008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup3_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup3_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
+       .halt_reg = 0x2a004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x2a004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup3_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup3_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
+       .halt_reg = 0x2c008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x2c008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup4_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup4_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
+       .halt_reg = 0x2c004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x2c004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup4_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup4_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
+       .halt_reg = 0x2e008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x2e008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup5_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup5_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
+       .halt_reg = 0x2e004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x2e004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup5_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup5_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
+       .halt_reg = 0x30008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x30008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup6_i2c_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup6_i2c_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
+       .halt_reg = 0x30004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x30004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_qup6_spi_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_qup6_spi_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_sleep_clk = {
+       .halt_reg = 0x25008,
+       .halt_check = BRANCH_HALT_VOTED,
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(14),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_sleep_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_uart1_apps_clk = {
+       .halt_reg = 0x27004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x27004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_uart1_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_uart1_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_uart2_apps_clk = {
+       .halt_reg = 0x29004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x29004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_uart2_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_uart2_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_blsp2_uart3_apps_clk = {
+       .halt_reg = 0x2b004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x2b004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_blsp2_uart3_apps_clk",
+                       .parent_names = (const char *[]){
+                               "blsp2_uart3_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
+       .halt_reg = 0x5018,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x5018,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_cfg_noc_usb3_axi_clk",
+                       .parent_names = (const char *[]){
+                               "usb30_master_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+       .halt_reg = 0x64000,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x64000,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gp1_clk",
+                       .parent_names = (const char *[]){
+                               "gp1_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+       .halt_reg = 0x65000,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x65000,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gp2_clk",
+                       .parent_names = (const char *[]){
+                               "gp2_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+       .halt_reg = 0x66000,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x66000,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gp3_clk",
+                       .parent_names = (const char *[]){
+                               "gp3_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_gpu_bimc_gfx_clk = {
+       .halt_reg = 0x71010,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x71010,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gpu_bimc_gfx_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
+       .halt_reg = 0x7100c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x7100c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gpu_bimc_gfx_src_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_gpu_cfg_ahb_clk = {
+       .halt_reg = 0x71004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x71004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gpu_cfg_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
+       .halt_reg = 0x71018,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x71018,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gpu_snoc_dvm_gfx_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_hmss_ahb_clk = {
+       .halt_reg = 0x48000,
+       .halt_check = BRANCH_HALT_VOTED,
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(21),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_hmss_ahb_clk",
+                       .parent_names = (const char *[]){
+                               "hmss_ahb_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_hmss_at_clk = {
+       .halt_reg = 0x48010,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x48010,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_hmss_at_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_hmss_dvm_bus_clk = {
+       .halt_reg = 0x4808c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x4808c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_hmss_dvm_bus_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_hmss_rbcpr_clk = {
+       .halt_reg = 0x48008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x48008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_hmss_rbcpr_clk",
+                       .parent_names = (const char *[]){
+                               "hmss_rbcpr_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_hmss_trig_clk = {
+       .halt_reg = 0x4800c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x4800c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_hmss_trig_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_lpass_at_clk = {
+       .halt_reg = 0x47020,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x47020,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_lpass_at_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_lpass_trig_clk = {
+       .halt_reg = 0x4701c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x4701c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_lpass_trig_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
+       .halt_reg = 0x9004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x9004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_mmss_noc_cfg_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_mmss_qm_ahb_clk = {
+       .halt_reg = 0x9030,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x9030,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_mmss_qm_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_mmss_qm_core_clk = {
+       .halt_reg = 0x900c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x900c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_mmss_qm_core_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
+       .halt_reg = 0x9000,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x9000,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_mmss_sys_noc_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_mss_at_clk = {
+       .halt_reg = 0x8a00c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x8a00c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_mss_at_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pcie_0_aux_clk = {
+       .halt_reg = 0x6b014,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x6b014,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie_0_aux_clk",
+                       .parent_names = (const char *[]){
+                               "pcie_aux_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
+       .halt_reg = 0x6b010,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x6b010,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie_0_cfg_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
+       .halt_reg = 0x6b00c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x6b00c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie_0_mstr_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pcie_0_pipe_clk = {
+       .halt_reg = 0x6b018,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x6b018,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie_0_pipe_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pcie_0_slv_axi_clk = {
+       .halt_reg = 0x6b008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x6b008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie_0_slv_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pcie_phy_aux_clk = {
+       .halt_reg = 0x6f004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x6f004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie_phy_aux_clk",
+                       .parent_names = (const char *[]){
+                               "pcie_aux_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+       .halt_reg = 0x3300c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x3300c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pdm2_clk",
+                       .parent_names = (const char *[]){
+                               "pdm2_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+       .halt_reg = 0x33004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x33004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pdm_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_pdm_xo4_clk = {
+       .halt_reg = 0x33008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x33008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pdm_xo4_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+       .halt_reg = 0x34004,
+       .halt_check = BRANCH_HALT_VOTED,
+       .clkr = {
+               .enable_reg = 0x52004,
+               .enable_mask = BIT(13),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_prng_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+       .halt_reg = 0x14008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x14008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_sdcc2_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+       .halt_reg = 0x14004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x14004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_sdcc2_apps_clk",
+                       .parent_names = (const char *[]){
+                               "sdcc2_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_sdcc4_ahb_clk = {
+       .halt_reg = 0x16008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x16008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_sdcc4_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_sdcc4_apps_clk = {
+       .halt_reg = 0x16004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x16004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_sdcc4_apps_clk",
+                       .parent_names = (const char *[]){
+                               "sdcc4_apps_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_tsif_ahb_clk = {
+       .halt_reg = 0x36004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x36004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_tsif_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_tsif_inactivity_timers_clk = {
+       .halt_reg = 0x3600c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x3600c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_tsif_inactivity_timers_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_tsif_ref_clk = {
+       .halt_reg = 0x36008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x36008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_tsif_ref_clk",
+                       .parent_names = (const char *[]){
+                               "tsif_ref_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ufs_ahb_clk = {
+       .halt_reg = 0x7500c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x7500c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ufs_axi_clk = {
+       .halt_reg = 0x75008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x75008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_axi_clk",
+                       .parent_names = (const char *[]){
+                               "ufs_axi_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ufs_ice_core_clk = {
+       .halt_reg = 0x7600c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x7600c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_ice_core_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ufs_phy_aux_clk = {
+       .halt_reg = 0x76040,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x76040,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_phy_aux_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
+       .halt_reg = 0x75014,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x75014,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_rx_symbol_0_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
+       .halt_reg = 0x7605c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x7605c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_rx_symbol_1_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
+       .halt_reg = 0x75010,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x75010,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_tx_symbol_0_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ufs_unipro_core_clk = {
+       .halt_reg = 0x76008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x76008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_unipro_core_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_usb30_master_clk = {
+       .halt_reg = 0xf008,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0xf008,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_usb30_master_clk",
+                       .parent_names = (const char *[]){
+                               "usb30_master_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_usb30_mock_utmi_clk = {
+       .halt_reg = 0xf010,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0xf010,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_usb30_mock_utmi_clk",
+                       .parent_names = (const char *[]){
+                               "usb30_mock_utmi_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_usb30_sleep_clk = {
+       .halt_reg = 0xf00c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0xf00c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_usb30_sleep_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_usb3_phy_aux_clk = {
+       .halt_reg = 0x50000,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x50000,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_usb3_phy_aux_clk",
+                       .parent_names = (const char *[]){
+                               "usb3_phy_aux_clk_src",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_usb3_phy_pipe_clk = {
+       .halt_reg = 0x50004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x50004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_usb3_phy_pipe_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
+       .halt_reg = 0x6a004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x6a004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_usb_phy_cfg_ahb2phy_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct gdsc pcie_0_gdsc = {
+       .gdscr = 0x6b004,
+       .gds_hw_ctrl = 0x0,
+       .pd = {
+               .name = "pcie_0_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+       .flags = VOTABLE,
+};
+
+static struct gdsc ufs_gdsc = {
+       .gdscr = 0x75004,
+       .gds_hw_ctrl = 0x0,
+       .pd = {
+               .name = "ufs_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+       .flags = VOTABLE,
+};
+
+static struct gdsc usb_30_gdsc = {
+       .gdscr = 0xf004,
+       .gds_hw_ctrl = 0x0,
+       .pd = {
+               .name = "usb_30_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+       .flags = VOTABLE,
+};
+
+static struct clk_regmap *gcc_msm8998_clocks[] = {
+       [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+       [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+       [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+       [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+       [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+       [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+       [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+       [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+       [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
+       [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
+       [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
+       [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
+       [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+       [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+       [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
+       [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
+       [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
+       [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
+       [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
+       [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
+       [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
+       [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
+       [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
+       [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
+       [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
+       [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
+       [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
+       [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
+       [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
+       [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
+       [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
+       [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
+       [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
+       [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
+       [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
+       [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
+       [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
+       [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+       [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+       [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+       [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+       [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+       [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+       [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+       [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+       [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+       [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
+       [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+       [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
+       [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
+       [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
+       [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+       [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+       [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
+       [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
+       [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
+       [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
+       [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
+       [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
+       [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
+       [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
+       [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
+       [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
+       [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
+       [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
+       [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
+       [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
+       [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
+       [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
+       [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
+       [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
+       [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
+       [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+       [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+       [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+       [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
+       [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
+       [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+       [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
+       [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
+       [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
+       [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
+       [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
+       [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
+       [GCC_LPASS_AT_CLK] = &gcc_lpass_at_clk.clkr,
+       [GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr,
+       [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
+       [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
+       [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
+       [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
+       [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
+       [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
+       [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
+       [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
+       [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
+       [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
+       [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
+       [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+       [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+       [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
+       [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+       [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+       [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+       [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
+       [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
+       [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
+       [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
+       [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
+       [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
+       [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
+       [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
+       [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
+       [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
+       [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
+       [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
+       [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
+       [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
+       [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
+       [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
+       [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
+       [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
+       [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+       [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+       [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+       [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+       [GPLL0] = &gpll0.clkr,
+       [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
+       [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
+       [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
+       [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
+       [GPLL1] = &gpll1.clkr,
+       [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
+       [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
+       [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
+       [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
+       [GPLL2] = &gpll2.clkr,
+       [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
+       [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
+       [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
+       [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
+       [GPLL3] = &gpll3.clkr,
+       [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
+       [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
+       [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
+       [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
+       [GPLL4] = &gpll4.clkr,
+       [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
+       [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
+       [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
+       [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
+       [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
+       [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
+       [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
+       [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+       [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+       [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
+       [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
+       [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
+       [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
+       [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
+       [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+};
+
+static struct gdsc *gcc_msm8998_gdscs[] = {
+       [PCIE_0_GDSC] = &pcie_0_gdsc,
+       [UFS_GDSC] = &ufs_gdsc,
+       [USB_30_GDSC] = &usb_30_gdsc,
+};
+
+static const struct qcom_reset_map gcc_msm8998_resets[] = {
+       [GCC_BLSP1_QUP1_BCR] = { 0x102400 },
+       [GCC_BLSP1_QUP2_BCR] = { 0x110592 },
+       [GCC_BLSP1_QUP3_BCR] = { 0x118784 },
+       [GCC_BLSP1_QUP4_BCR] = { 0x126976 },
+       [GCC_BLSP1_QUP5_BCR] = { 0x135168 },
+       [GCC_BLSP1_QUP6_BCR] = { 0x143360 },
+       [GCC_BLSP2_QUP1_BCR] = { 0x155648 },
+       [GCC_BLSP2_QUP2_BCR] = { 0x163840 },
+       [GCC_BLSP2_QUP3_BCR] = { 0x172032 },
+       [GCC_BLSP2_QUP4_BCR] = { 0x180224 },
+       [GCC_BLSP2_QUP5_BCR] = { 0x188416 },
+       [GCC_BLSP2_QUP6_BCR] = { 0x196608 },
+       [GCC_PCIE_0_BCR] = { 0x438272 },
+       [GCC_PDM_BCR] = { 0x208896 },
+       [GCC_SDCC2_BCR] = { 0x81920 },
+       [GCC_SDCC4_BCR] = { 0x90112 },
+       [GCC_TSIF_BCR] = { 0x221184 },
+       [GCC_UFS_BCR] = { 0x479232 },
+       [GCC_USB_30_BCR] = { 0x61440 },
+};
+
+static const struct regmap_config gcc_msm8998_regmap_config = {
+       .reg_bits       = 32,
+       .reg_stride     = 4,
+       .val_bits       = 32,
+       .max_register   = 0x8f000,
+       .fast_io        = true,
+};
+
+static const struct qcom_cc_desc gcc_msm8998_desc = {
+       .config = &gcc_msm8998_regmap_config,
+       .clks = gcc_msm8998_clocks,
+       .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
+       .resets = gcc_msm8998_resets,
+       .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
+       .gdscs = gcc_msm8998_gdscs,
+       .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
+};
+
+static int gcc_msm8998_probe(struct platform_device *pdev)
+{
+       struct regmap *regmap;
+       int ret;
+
+       regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
+       if (IS_ERR(regmap))
+               return PTR_ERR(regmap);
+
+       /*
+        * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
+        * turned off by hardware during certain apps low power modes.
+        */
+       ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
+       if (ret)
+               return ret;
+
+       return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
+}
+
+static const struct of_device_id gcc_msm8998_match_table[] = {
+       { .compatible = "qcom,gcc-msm8998" },
+       { }
+};
+MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
+
+static struct platform_driver gcc_msm8998_driver = {
+       .probe          = gcc_msm8998_probe,
+       .driver         = {
+               .name   = "gcc-msm8998",
+               .of_match_table = gcc_msm8998_match_table,
+       },
+};
+
+static int __init gcc_msm8998_init(void)
+{
+       return platform_driver_register(&gcc_msm8998_driver);
+}
+core_initcall(gcc_msm8998_init);
+
+static void __exit gcc_msm8998_exit(void)
+{
+       platform_driver_unregister(&gcc_msm8998_driver);
+}
+module_exit(gcc_msm8998_exit);
+
+MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:gcc-msm8998");
index 077df3e539a71fef9a1ebfd98424525aeabb4885..f41d89cef0f19bff05bc03fc0c330a436ebbee6c 100644 (file)
@@ -219,8 +219,7 @@ static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
 #ifdef CONFIG_PM_SLEEP
 static int s3c24xx_dclk_suspend(struct device *dev)
 {
-       struct platform_device *pdev = to_platform_device(dev);
-       struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
+       struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
 
        s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
        return 0;
@@ -228,8 +227,7 @@ static int s3c24xx_dclk_suspend(struct device *dev)
 
 static int s3c24xx_dclk_resume(struct device *dev)
 {
-       struct platform_device *pdev = to_platform_device(dev);
-       struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
+       struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
 
        writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
        return 0;
index 3a11c382a663ed98407532b980b20cf9c3cb55bd..72714633e39c639cf84531130839b678934b6a91 100644 (file)
@@ -260,46 +260,45 @@ static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
        return 0;
 }
 
-static struct stratix10_clock_data *__socfpga_s10_clk_init(struct device_node *np,
+static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev,
                                                    int nr_clks)
 {
+       struct device_node *np = pdev->dev.of_node;
+       struct device *dev = &pdev->dev;
        struct stratix10_clock_data *clk_data;
        struct clk **clk_table;
+       struct resource *res;
        void __iomem *base;
 
-       base = of_iomap(np, 0);
-       if (!base) {
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       base = devm_ioremap_resource(dev, res);
+       if (IS_ERR(base)) {
                pr_err("%s: failed to map clock registers\n", __func__);
-               goto err;
+               return ERR_CAST(base);
        }
 
-       clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+       clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
        if (!clk_data)
-               goto err;
+               return ERR_PTR(-ENOMEM);
 
        clk_data->base = base;
-       clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
+       clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
        if (!clk_table)
-               goto err_data;
+               return ERR_PTR(-ENOMEM);
 
        clk_data->clk_data.clks = clk_table;
        clk_data->clk_data.clk_num = nr_clks;
        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
        return clk_data;
-
-err_data:
-       kfree(clk_data);
-err:
-       return NULL;
 }
 
-static int s10_clkmgr_init(struct device_node *np)
+static int s10_clkmgr_init(struct platform_device *pdev)
 {
        struct stratix10_clock_data *clk_data;
 
-       clk_data = __socfpga_s10_clk_init(np, STRATIX10_NUM_CLKS);
-       if (!clk_data)
-               return -ENOMEM;
+       clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS);
+       if (IS_ERR(clk_data))
+               return PTR_ERR(clk_data);
 
        s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
 
@@ -317,11 +316,7 @@ static int s10_clkmgr_init(struct device_node *np)
 
 static int s10_clkmgr_probe(struct platform_device *pdev)
 {
-       struct device_node *np = pdev->dev.of_node;
-
-       s10_clkmgr_init(np);
-
-       return 0;
+       return  s10_clkmgr_init(pdev);
 }
 
 static const struct of_device_id stratix10_clkmgr_match_table[] = {
@@ -334,6 +329,7 @@ static struct platform_driver stratix10_clkmgr_driver = {
        .probe          = s10_clkmgr_probe,
        .driver         = {
                .name   = "stratix10-clkmgr",
+               .suppress_bind_attrs = true,
                .of_match_table = stratix10_clkmgr_match_table,
        },
 };
index f911d9f7776320a602a7894c664d5f875cf3be44..47810be7f15c9fef79f68ef1c85725fd895874de 100644 (file)
@@ -147,7 +147,7 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 
        clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
                        1);
-       clk_register_clkdev(clk, NULL, "wdt");
+       clk_register_clkdev(clk, NULL, "fc880000.wdt");
 
        /* clock derived from pll1 clk */
        clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
index 3ac9dec9a03852f921070ecc0f992e10b5650e8f..e01222ea888ff9d2b9187e4b02c8c0daa9448b40 100644 (file)
@@ -27,6 +27,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_clk.h>
 #include <linux/of_irq.h>
 #include <linux/sched_clock.h>
 
@@ -245,7 +246,7 @@ static int __init sp804_of_init(struct device_node *np)
                clk1 = NULL;
 
        /* Get the 2nd clock if the timer has 3 timer clocks */
-       if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
+       if (of_clk_get_parent_count(np) == 3) {
                clk2 = of_clk_get(np, 1);
                if (IS_ERR(clk2)) {
                        pr_err("sp804: %s clock not found: %d\n", np->name,
index 020d6d84639ca002e20f843c7d0e33ba80031e02..25e80a5370ca02f65999abd8932aec8b6aa05fc6 100644 (file)
 
 #include <linux/io.h>
 #include <linux/clk.h>
-#include <linux/clk-provider.h>
 #include <linux/gpio/driver.h>
 #include <linux/irqdomain.h>
 #include <linux/irqchip/chained_irq.h>
 #include <linux/export.h>
 #include <linux/of.h>
+#include <linux/of_clk.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
 #include <linux/of_irq.h>
@@ -1361,7 +1361,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
                        goto gpiochip_error;
        }
 
-       ret = of_count_phandle_with_args(node, "clocks", "#clock-cells");
+       ret = of_clk_get_parent_count(node);
        clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
        if (IS_ERR(clk)) {
                ret = PTR_ERR(clk);
index 53efc386b1ada8cf8821403aa0eb7a333535cd30..13913d40c8213e361396930e4829c9cab2f40dfe 100644 (file)
@@ -14,6 +14,7 @@
 #include <linux/pm_clock.h>
 #include <linux/pm_domain.h>
 #include <linux/of_address.h>
+#include <linux/of_clk.h>
 #include <linux/of_platform.h>
 #include <linux/clk.h>
 #include <linux/regmap.h>
@@ -400,8 +401,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
        pd->info = pd_info;
        pd->pmu = pmu;
 
-       pd->num_clks = of_count_phandle_with_args(node, "clocks",
-                                                 "#clock-cells");
+       pd->num_clks = of_clk_get_parent_count(node);
        if (pd->num_clks > 0) {
                pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
                                        sizeof(*pd->clks), GFP_KERNEL);
index d9fcdb592b3966a561b1514fa671689315a5fa3d..d8cb48a4b8eb1b78a63d75ea9f4ef4f362306c10 100644 (file)
@@ -31,6 +31,7 @@
 #include <linux/iopoll.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_clk.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
@@ -725,7 +726,7 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
        unsigned int i, count;
        int err;
 
-       count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+       count = of_clk_get_parent_count(np);
        if (count == 0)
                return -ENODEV;
 
diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h
new file mode 100644 (file)
index 0000000..7c12515
--- /dev/null
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree binding constants for Actions Semi S900 Clock Management Unit
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
+#define __DT_BINDINGS_CLOCK_S900_CMU_H
+
+#define CLK_NONE                       0
+
+/* fixed rate clocks */
+#define CLK_LOSC                       1
+#define CLK_HOSC                       2
+
+/* pll clocks */
+#define CLK_CORE_PLL                   3
+#define CLK_DEV_PLL                    4
+#define CLK_DDR_PLL                    5
+#define CLK_NAND_PLL                   6
+#define CLK_DISPLAY_PLL                        7
+#define CLK_DSI_PLL                    8
+#define CLK_ASSIST_PLL                 9
+#define CLK_AUDIO_PLL                  10
+
+/* system clock */
+#define CLK_CPU                                15
+#define CLK_DEV                                16
+#define CLK_NOC                                17
+#define CLK_NOC_MUX                    18
+#define CLK_NOC_DIV                    19
+#define CLK_AHB                                20
+#define CLK_APB                                21
+#define CLK_DMAC                       22
+
+/* peripheral device clock */
+#define CLK_GPIO                       23
+
+#define CLK_BISP                       24
+#define CLK_CSI0                       25
+#define CLK_CSI1                       26
+
+#define CLK_DE0                                27
+#define CLK_DE1                                28
+#define CLK_DE2                                29
+#define CLK_DE3                                30
+#define CLK_DSI                                32
+
+#define CLK_GPU                                33
+#define CLK_GPU_CORE                   34
+#define CLK_GPU_MEM                    35
+#define CLK_GPU_SYS                    36
+
+#define CLK_HDE                                37
+#define CLK_I2C0                       38
+#define CLK_I2C1                       39
+#define CLK_I2C2                       40
+#define CLK_I2C3                       41
+#define CLK_I2C4                       42
+#define CLK_I2C5                       43
+#define CLK_I2SRX                      44
+#define CLK_I2STX                      45
+#define CLK_IMX                                46
+#define CLK_LCD                                47
+#define CLK_NAND0                      48
+#define CLK_NAND1                      49
+#define CLK_PWM0                       50
+#define CLK_PWM1                       51
+#define CLK_PWM2                       52
+#define CLK_PWM3                       53
+#define CLK_PWM4                       54
+#define CLK_PWM5                       55
+#define CLK_SD0                                56
+#define CLK_SD1                                57
+#define CLK_SD2                                58
+#define CLK_SD3                                59
+#define CLK_SENSOR                     60
+#define CLK_SPEED_SENSOR               61
+#define CLK_SPI0                       62
+#define CLK_SPI1                       63
+#define CLK_SPI2                       64
+#define CLK_SPI3                       65
+#define CLK_THERMAL_SENSOR             66
+#define CLK_UART0                      67
+#define CLK_UART1                      68
+#define CLK_UART2                      69
+#define CLK_UART3                      70
+#define CLK_UART4                      71
+#define CLK_UART5                      72
+#define CLK_UART6                      73
+#define CLK_VCE                                74
+#define CLK_VDE                                75
+
+#define CLK_USB3_480MPLL0              76
+#define CLK_USB3_480MPHY0              77
+#define CLK_USB3_5GPHY                 78
+#define CLK_USB3_CCE                   79
+#define CLK_USB3_MAC                   80
+
+#define CLK_TIMER                      83
+
+#define CLK_HDMI_AUDIO                 84
+
+#define CLK_24M                                85
+
+#define CLK_EDP                                86
+
+#define CLK_24M_EDP                    87
+#define CLK_EDP_PLL                    88
+#define CLK_EDP_LINK                   89
+
+#define CLK_USB2H0_PLLEN               90
+#define CLK_USB2H0_PHY                 91
+#define CLK_USB2H0_CCE                 92
+#define CLK_USB2H1_PLLEN               93
+#define CLK_USB2H1_PHY                 94
+#define CLK_USB2H1_CCE                 95
+
+#define CLK_DDR0                       96
+#define CLK_DDR1                       97
+#define CLK_DMM                                98
+
+#define CLK_ETH_MAC                    99
+#define CLK_RMII_REF                   100
+
+#define CLK_NR_CLKS                    (CLK_RMII_REF + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
index d3558d897a4d19f0fca6d254c1bea045f2a45e5f..4d01804e7c438a9a2a034e7de82b1792cadc3ff7 100644 (file)
@@ -45,8 +45,9 @@
 #define ASPEED_RESET_JTAG_MASTER       3
 #define ASPEED_RESET_MIC               4
 #define ASPEED_RESET_PWM               5
-#define ASPEED_RESET_PCIVGA            6
+#define ASPEED_RESET_PECI              6
 #define ASPEED_RESET_I2C               7
 #define ASPEED_RESET_AHB               8
+#define ASPEED_RESET_CRT1              9
 
 #endif
diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
new file mode 100644 (file)
index 0000000..f215226
--- /dev/null
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Nuvoton NPCM7xx Clock Generator binding
+ * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
+ *
+ * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
+#define __DT_BINDINGS_CLOCK_NPCM7XX_H
+
+
+#define NPCM7XX_CLK_CPU 0
+#define NPCM7XX_CLK_GFX_PIXEL 1
+#define NPCM7XX_CLK_MC 2
+#define NPCM7XX_CLK_ADC 3
+#define NPCM7XX_CLK_AHB 4
+#define NPCM7XX_CLK_TIMER 5
+#define NPCM7XX_CLK_UART 6
+#define NPCM7XX_CLK_MMC  7
+#define NPCM7XX_CLK_SPI3 8
+#define NPCM7XX_CLK_PCI  9
+#define NPCM7XX_CLK_AXI 10
+#define NPCM7XX_CLK_APB4 11
+#define NPCM7XX_CLK_APB3 12
+#define NPCM7XX_CLK_APB2 13
+#define NPCM7XX_CLK_APB1 14
+#define NPCM7XX_CLK_APB5 15
+#define NPCM7XX_CLK_CLKOUT 16
+#define NPCM7XX_CLK_GFX  17
+#define NPCM7XX_CLK_SU   18
+#define NPCM7XX_CLK_SU48 19
+#define NPCM7XX_CLK_SDHC 20
+#define NPCM7XX_CLK_SPI0 21
+#define NPCM7XX_CLK_SPIX 22
+
+#define NPCM7XX_CLK_REFCLK 23
+#define NPCM7XX_CLK_SYSBYPCK 24
+#define NPCM7XX_CLK_MCBYPCK 25
+
+#define NPCM7XX_NUM_CLOCKS      (NPCM7XX_CLK_MCBYPCK+1)
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
new file mode 100644 (file)
index 0000000..58a242e
--- /dev/null
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
+#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
+
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC                            0
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC                            1
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC                            2
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC                            3
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC                            4
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC                            5
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC                            6
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC                            7
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC                            8
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC                            9
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC                            10
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC                            11
+#define BLSP1_UART1_APPS_CLK_SRC                               12
+#define BLSP1_UART2_APPS_CLK_SRC                               13
+#define BLSP1_UART3_APPS_CLK_SRC                               14
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC                            15
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC                            16
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC                            17
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC                            18
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC                            19
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC                            20
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC                            21
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC                            22
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC                            23
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC                            24
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC                            25
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC                            26
+#define BLSP2_UART1_APPS_CLK_SRC                               27
+#define BLSP2_UART2_APPS_CLK_SRC                               28
+#define BLSP2_UART3_APPS_CLK_SRC                               29
+#define GCC_AGGRE1_NOC_XO_CLK                                  30
+#define GCC_AGGRE1_UFS_AXI_CLK                                 31
+#define GCC_AGGRE1_USB3_AXI_CLK                                        32
+#define GCC_APSS_QDSS_TSCTR_DIV2_CLK                           33
+#define GCC_APSS_QDSS_TSCTR_DIV8_CLK                           34
+#define GCC_BIMC_HMSS_AXI_CLK                                  35
+#define GCC_BIMC_MSS_Q6_AXI_CLK                                        36
+#define GCC_BLSP1_AHB_CLK                                      37
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK                            38
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK                            39
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK                            40
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK                            41
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK                            42
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK                            43
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK                            44
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK                            45
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK                            46
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK                            47
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK                            48
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK                            49
+#define GCC_BLSP1_SLEEP_CLK                                    50
+#define GCC_BLSP1_UART1_APPS_CLK                               51
+#define GCC_BLSP1_UART2_APPS_CLK                               52
+#define GCC_BLSP1_UART3_APPS_CLK                               53
+#define GCC_BLSP2_AHB_CLK                                      54
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK                            55
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK                            56
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK                            57
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK                            58
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK                            59
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK                            60
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK                            61
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK                            62
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK                            63
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK                            64
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK                            65
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK                            66
+#define GCC_BLSP2_SLEEP_CLK                                    67
+#define GCC_BLSP2_UART1_APPS_CLK                               68
+#define GCC_BLSP2_UART2_APPS_CLK                               69
+#define GCC_BLSP2_UART3_APPS_CLK                               70
+#define GCC_CFG_NOC_USB3_AXI_CLK                               71
+#define GCC_GP1_CLK                                            72
+#define GCC_GP2_CLK                                            73
+#define GCC_GP3_CLK                                            74
+#define GCC_GPU_BIMC_GFX_CLK                                   75
+#define GCC_GPU_BIMC_GFX_SRC_CLK                               76
+#define GCC_GPU_CFG_AHB_CLK                                    77
+#define GCC_GPU_SNOC_DVM_GFX_CLK                               78
+#define GCC_HMSS_AHB_CLK                                       79
+#define GCC_HMSS_AT_CLK                                                80
+#define GCC_HMSS_DVM_BUS_CLK                                   81
+#define GCC_HMSS_RBCPR_CLK                                     82
+#define GCC_HMSS_TRIG_CLK                                      83
+#define GCC_LPASS_AT_CLK                                       84
+#define GCC_LPASS_TRIG_CLK                                     85
+#define GCC_MMSS_NOC_CFG_AHB_CLK                               86
+#define GCC_MMSS_QM_AHB_CLK                                    87
+#define GCC_MMSS_QM_CORE_CLK                                   88
+#define GCC_MMSS_SYS_NOC_AXI_CLK                               89
+#define GCC_MSS_AT_CLK                                         90
+#define GCC_PCIE_0_AUX_CLK                                     91
+#define GCC_PCIE_0_CFG_AHB_CLK                                 92
+#define GCC_PCIE_0_MSTR_AXI_CLK                                        93
+#define GCC_PCIE_0_PIPE_CLK                                    94
+#define GCC_PCIE_0_SLV_AXI_CLK                                 95
+#define GCC_PCIE_PHY_AUX_CLK                                   96
+#define GCC_PDM2_CLK                                           97
+#define GCC_PDM_AHB_CLK                                                98
+#define GCC_PDM_XO4_CLK                                                99
+#define GCC_PRNG_AHB_CLK                                       100
+#define GCC_SDCC2_AHB_CLK                                      101
+#define GCC_SDCC2_APPS_CLK                                     102
+#define GCC_SDCC4_AHB_CLK                                      103
+#define GCC_SDCC4_APPS_CLK                                     104
+#define GCC_TSIF_AHB_CLK                                       105
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK                         106
+#define GCC_TSIF_REF_CLK                                       107
+#define GCC_UFS_AHB_CLK                                                108
+#define GCC_UFS_AXI_CLK                                                109
+#define GCC_UFS_ICE_CORE_CLK                                   110
+#define GCC_UFS_PHY_AUX_CLK                                    111
+#define GCC_UFS_RX_SYMBOL_0_CLK                                        112
+#define GCC_UFS_RX_SYMBOL_1_CLK                                        113
+#define GCC_UFS_TX_SYMBOL_0_CLK                                        114
+#define GCC_UFS_UNIPRO_CORE_CLK                                        115
+#define GCC_USB30_MASTER_CLK                                   116
+#define GCC_USB30_MOCK_UTMI_CLK                                        117
+#define GCC_USB30_SLEEP_CLK                                    118
+#define GCC_USB3_PHY_AUX_CLK                                   119
+#define GCC_USB3_PHY_PIPE_CLK                                  120
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK                            121
+#define GP1_CLK_SRC                                            122
+#define GP2_CLK_SRC                                            123
+#define GP3_CLK_SRC                                            124
+#define GPLL0                                                  125
+#define GPLL0_OUT_EVEN                                         126
+#define GPLL0_OUT_MAIN                                         127
+#define GPLL0_OUT_ODD                                          128
+#define GPLL0_OUT_TEST                                         129
+#define GPLL1                                                  130
+#define GPLL1_OUT_EVEN                                         131
+#define GPLL1_OUT_MAIN                                         132
+#define GPLL1_OUT_ODD                                          133
+#define GPLL1_OUT_TEST                                         134
+#define GPLL2                                                  135
+#define GPLL2_OUT_EVEN                                         136
+#define GPLL2_OUT_MAIN                                         137
+#define GPLL2_OUT_ODD                                          138
+#define GPLL2_OUT_TEST                                         139
+#define GPLL3                                                  140
+#define GPLL3_OUT_EVEN                                         141
+#define GPLL3_OUT_MAIN                                         142
+#define GPLL3_OUT_ODD                                          143
+#define GPLL3_OUT_TEST                                         144
+#define GPLL4                                                  145
+#define GPLL4_OUT_EVEN                                         146
+#define GPLL4_OUT_MAIN                                         147
+#define GPLL4_OUT_ODD                                          148
+#define GPLL4_OUT_TEST                                         149
+#define GPLL6                                                  150
+#define GPLL6_OUT_EVEN                                         151
+#define GPLL6_OUT_MAIN                                         152
+#define GPLL6_OUT_ODD                                          153
+#define GPLL6_OUT_TEST                                         154
+#define HMSS_AHB_CLK_SRC                                       155
+#define HMSS_RBCPR_CLK_SRC                                     156
+#define PCIE_AUX_CLK_SRC                                       157
+#define PDM2_CLK_SRC                                           158
+#define SDCC2_APPS_CLK_SRC                                     159
+#define SDCC4_APPS_CLK_SRC                                     160
+#define TSIF_REF_CLK_SRC                                       161
+#define UFS_AXI_CLK_SRC                                                162
+#define USB30_MASTER_CLK_SRC                                   163
+#define USB30_MOCK_UTMI_CLK_SRC                                        164
+#define USB3_PHY_AUX_CLK_SRC                                   165
+
+#define PCIE_0_GDSC                                            0
+#define UFS_GDSC                                               1
+#define USB_30_GDSC                                            2
+
+#define GCC_BLSP1_QUP1_BCR                                     0
+#define GCC_BLSP1_QUP2_BCR                                     1
+#define GCC_BLSP1_QUP3_BCR                                     2
+#define GCC_BLSP1_QUP4_BCR                                     3
+#define GCC_BLSP1_QUP5_BCR                                     4
+#define GCC_BLSP1_QUP6_BCR                                     5
+#define GCC_BLSP2_QUP1_BCR                                     6
+#define GCC_BLSP2_QUP2_BCR                                     7
+#define GCC_BLSP2_QUP3_BCR                                     8
+#define GCC_BLSP2_QUP4_BCR                                     9
+#define GCC_BLSP2_QUP5_BCR                                     10
+#define GCC_BLSP2_QUP6_BCR                                     11
+#define GCC_PCIE_0_BCR                                         12
+#define GCC_PDM_BCR                                            13
+#define GCC_SDCC2_BCR                                          14
+#define GCC_SDCC4_BCR                                          15
+#define GCC_TSIF_BCR                                           16
+#define GCC_UFS_BCR                                            17
+#define GCC_USB_30_BCR                                         18
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
new file mode 100644 (file)
index 0000000..f48fbd6
--- /dev/null
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
+
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
+#define _DT_BINDINGS_CLK_MSM_RPMH_H
+
+/* RPMh controlled clocks */
+#define RPMH_CXO_CLK                           0
+#define RPMH_CXO_CLK_A                         1
+#define RPMH_LN_BB_CLK2                                2
+#define RPMH_LN_BB_CLK2_A                      3
+#define RPMH_LN_BB_CLK3                                4
+#define RPMH_LN_BB_CLK3_A                      5
+#define RPMH_RF_CLK1                           6
+#define RPMH_RF_CLK1_A                         7
+#define RPMH_RF_CLK2                           8
+#define RPMH_RF_CLK2_A                         9
+#define RPMH_RF_CLK3                           10
+#define RPMH_RF_CLK3_A                         11
+
+#endif
index 86e3ec662ef4d58391add4d1781b8a070cc82d50..90ec780bfc68622f264e7e7c7e1e030c3b83cfba 100644 (file)
@@ -76,7 +76,7 @@
 #define I2C6           63
 #define USART1         64
 #define RTCAPB         65
-#define TZC            66
+#define TZC1           66
 #define TZPC           67
 #define IWDG1          68
 #define BSEC           69
 #define CRC1           110
 #define USBH           111
 #define ETHSTP         112
+#define TZC2           113
 
 /* Kernel clocks */
 #define SDMMC1_K       118
 #define CK_MCO2                212
 
 /* TRACE & DEBUG clocks */
-#define DBG            213
 #define CK_DBG         214
 #define CK_TRACE       215
 
index 210a890008f9e12987e578b949e6702864d076f6..f2c8fb81e9b01c944ba827625a48e3e063ac3d53 100644 (file)
@@ -13,6 +13,7 @@
 
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_clk.h>
 
 #ifdef CONFIG_COMMON_CLK
 
@@ -802,8 +803,6 @@ unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
 
 struct of_device_id;
 
-typedef void (*of_clk_init_cb_t)(struct device_node *);
-
 struct clk_onecell_data {
        struct clk **clks;
        unsigned int clk_num;
@@ -890,13 +889,10 @@ struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
                                     void *data);
-unsigned int of_clk_get_parent_count(struct device_node *np);
 int of_clk_parent_fill(struct device_node *np, const char **parents,
                       unsigned int size);
-const char *of_clk_get_parent_name(struct device_node *np, int index);
 int of_clk_detect_critical(struct device_node *np, int index,
                            unsigned long *flags);
-void of_clk_init(const struct of_device_id *matches);
 
 #else /* !CONFIG_OF */
 
@@ -943,26 +939,16 @@ of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
 {
        return ERR_PTR(-ENOENT);
 }
-static inline unsigned int of_clk_get_parent_count(struct device_node *np)
-{
-       return 0;
-}
 static inline int of_clk_parent_fill(struct device_node *np,
                                     const char **parents, unsigned int size)
 {
        return 0;
 }
-static inline const char *of_clk_get_parent_name(struct device_node *np,
-                                                int index)
-{
-       return NULL;
-}
 static inline int of_clk_detect_critical(struct device_node *np, int index,
                                          unsigned long *flags)
 {
        return 0;
 }
-static inline void of_clk_init(const struct of_device_id *matches) {}
 #endif /* CONFIG_OF */
 
 /*
diff --git a/include/linux/of_clk.h b/include/linux/of_clk.h
new file mode 100644 (file)
index 0000000..b27da9f
--- /dev/null
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * OF clock helpers
+ */
+
+#ifndef __LINUX_OF_CLK_H
+#define __LINUX_OF_CLK_H
+
+#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_OF)
+
+unsigned int of_clk_get_parent_count(struct device_node *np);
+const char *of_clk_get_parent_name(struct device_node *np, int index);
+void of_clk_init(const struct of_device_id *matches);
+
+#else /* !CONFIG_COMMON_CLK || !CONFIG_OF */
+
+static inline unsigned int of_clk_get_parent_count(struct device_node *np)
+{
+       return 0;
+}
+static inline const char *of_clk_get_parent_name(struct device_node *np,
+                                                int index)
+{
+       return NULL;
+}
+static inline void of_clk_init(const struct of_device_id *matches) {}
+
+#endif /* !CONFIG_COMMON_CLK || !CONFIG_OF */
+
+#endif /* __LINUX_OF_CLK_H */