Merge tag 'amlogic-dt64' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman...
authorOlof Johansson <olof@lixom.net>
Fri, 25 May 2018 11:50:57 +0000 (04:50 -0700)
committerOlof Johansson <olof@lixom.net>
Fri, 25 May 2018 11:50:57 +0000 (04:50 -0700)
Amlogic 64-bit DT updates for v4.18
- AXG family: support more peripherals (wifi, eMMC, clocks)
- GX family: add/enable USB host support

* tag 'amlogic-dt64' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  dt-bindings: arm: amlogic: add support for the Tronsmart MXIII Plus
  dt-bindings: arm: amlogic: add support for the Meson8m2 SoC
  ARM64: dts: meson-axg: enable AP6255 wifi module
  ARM64: dts: meson: add MMC resets
  ARM64: dts: meson-axg: add an 32K alt aoclk
  ARM64: dts: meson-axg: add tdm pins
  ARM64: dts: meson-axg: add GPIO interrupt controller support
  ARM64: dts: meson-axg: enable the eMMC controller
  ARM64: dts: meson-gx: fix gxl clock controller compatible
  ARM64: dts: meson-axg: use hhi syscon for the clock controller
  ARM64: dts: meson-gx: sysctrl is the parent of the clock controller
  dt-bindings: clock: meson: update documentation with hhi syscon

Signed-off-by: Olof Johansson <olof@lixom.net>
Documentation/devicetree/bindings/arm/amlogic.txt
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

index f747f47922c55dfabdf56a2ba3db6bbf1d704816..69880560c0f0219aa0a875396d0587b4274c97fc 100644 (file)
@@ -25,6 +25,10 @@ Boards with the Amlogic Meson8b SoC shall have the following properties:
   Required root node property:
     compatible: "amlogic,meson8b";
 
+Boards with the Amlogic Meson8m2 SoC shall have the following properties:
+  Required root node property:
+    compatible: "amlogic,meson8m2";
+
 Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
   Required root node property:
     compatible: "amlogic,meson-gxbb";
@@ -54,6 +58,8 @@ Board compatible values (alphabetically, grouped by SoC):
   - "hardkernel,odroid-c1" (Meson8b)
   - "tronfy,mxq" (Meson8b)
 
+  - "tronsmart,mxiii-plus" (Meson8m2)
+
   - "amlogic,p200" (Meson gxbb)
   - "amlogic,p201" (Meson gxbb)
   - "friendlyarm,nanopi-k2" (Meson gxbb)
index e2b377ed6f915440997b3715eed53a94775ab70d..e950599566a99876b9be5e7536828e469fef4f80 100644 (file)
@@ -10,9 +10,6 @@ Required Properties:
                "amlogic,gxl-clkc" for GXL and GXM SoC,
                "amlogic,axg-clkc" for AXG SoC.
 
-- reg: physical base address of the clock controller and length of memory
-       mapped region.
-
 - #clock-cells: should be 1.
 
 Each clock is assigned an identifier and client nodes can use this identifier
@@ -20,13 +17,22 @@ to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
 used in device tree sources.
 
+Parent node should have the following properties :
+- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
+              "amlogic,meson-axg-hhi-sysctrl"
+- reg: base address and size of the HHI system control register space.
+
 Example: Clock controller node:
 
-       clkc: clock-controller@c883c000 {
+sysctrl: system-controller@0 {
+       compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
+       reg = <0 0 0 0x400>;
+
+       clkc: clock-controller {
                #clock-cells = <1>;
                compatible = "amlogic,gxbb-clkc";
-               reg = <0x0 0xc883c000 0x0 0x3db>;
        };
+};
 
 Example: UART controller node that consumes the clock generated by the clock
   controller:
index 57eedced5a5168fbc72fc1224be13e7d12b80aa5..b3e1bdca32bb3ff7b43a65f82330b2186326713e 100644 (file)
                serial0 = &uart_AO;
                serial1 = &uart_A;
        };
+
+       vddio_boot: regulator-vddio_boot {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDIO_BOOT";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+
+       vddao_3v3: regulator-vddao_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDAO_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       vddio_ao18: regulator-vddio_ao18 {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDIO_AO18";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+
+       vcc_3v3: regulator-vcc_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       emmc_pwrseq: emmc-pwrseq {
+               compatible = "mmc-pwrseq-emmc";
+               reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+       };
+
+       sdio_pwrseq: sdio-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
+               clocks = <&wifi32k>;
+               clock-names = "ext_clock";
+       };
+
+       wifi32k: wifi32k {
+               compatible = "pwm-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
+       };
 };
 
 &ethmac {
        pinctrl-0 = <&i2c1_z_pins>;
        pinctrl-names = "default";
 };
+
+&pwm_ab {
+       status = "okay";
+       pinctrl-0 = <&pwm_a_x20_pins>;
+       pinctrl-names = "default";
+};
+
+/* emmc storage */
+&sd_emmc_c {
+       status = "okay";
+       pinctrl-0 = <&emmc_pins>;
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <8>;
+       cap-sd-highspeed;
+       cap-mmc-highspeed;
+       max-frequency = <180000000>;
+       non-removable;
+       disable-wp;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+
+       vmmc-supply = <&vcc_3v3>;
+       vqmmc-supply = <&vddio_boot>;
+};
+
+/* wifi module */
+&sd_emmc_b {
+       status = "okay";
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       pinctrl-0 = <&sdio_pins>;
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       max-frequency = <100000000>;
+       non-removable;
+       disable-wp;
+
+       mmc-pwrseq = <&sdio_pwrseq>;
+
+       vmmc-supply = <&vddao_3v3>;
+       vqmmc-supply = <&vddio_boot>;
+
+       brcmf: wifi@1 {
+               reg = <1>;
+               compatible = "brcm,bcm4329-fmac";
+       };
+};
index b58808eb3cc84037ab9cc87edeb2d624a65a073b..381bd2c707a73cdafaa5691a8daf7d570aa0682e 100644 (file)
@@ -7,6 +7,8 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/axg-clkc.h>
+#include <dt-bindings/gpio/meson-axg-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
 
 / {
        compatible = "amlogic,meson-axg";
                #clock-cells = <0>;
        };
 
+       ao_alt_xtal: ao_alt_xtal-clk {
+               compatible = "fixed-clock";
+               clock-frequency = <32000000>;
+               clock-output-names = "ao_alt_xtal";
+               #clock-cells = <0>;
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
 
+               apb: apb@ffe00000 {
+                       compatible = "simple-bus";
+                       reg = <0x0 0xffe00000 0x0 0x200000>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
+
+                       sd_emmc_b: sd@5000 {
+                               compatible = "amlogic,meson-axg-mmc";
+                               reg = <0x0 0x5000 0x0 0x2000>;
+                               interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
+                               status = "disabled";
+                               clocks = <&clkc CLKID_SD_EMMC_B>,
+                                       <&clkc CLKID_SD_EMMC_B_CLK0>,
+                                       <&clkc CLKID_FCLK_DIV2>;
+                               clock-names = "core", "clkin0", "clkin1";
+                               resets = <&reset RESET_SD_EMMC_B>;
+                       };
+
+                       sd_emmc_c: mmc@7000 {
+                               compatible = "amlogic,meson-axg-mmc";
+                               reg = <0x0 0x7000 0x0 0x2000>;
+                               interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
+                               status = "disabled";
+                               clocks = <&clkc CLKID_SD_EMMC_C>,
+                                       <&clkc CLKID_SD_EMMC_C_CLK0>,
+                                       <&clkc CLKID_FCLK_DIV2>;
+                               clock-names = "core", "clkin0", "clkin1";
+                               resets = <&reset RESET_SD_EMMC_C>;
+                       };
+               };
+
                cbus: bus@ffd00000 {
                        compatible = "simple-bus";
                        reg = <0x0 0xffd00000 0x0 0x25000>;
                        #size-cells = <2>;
                        ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
 
+                       gpio_intc: interrupt-controller@f080 {
+                               compatible = "amlogic,meson-gpio-intc";
+                               reg = <0x0 0xf080 0x0 0x10>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
+                               status = "disabled";
+                       };
+
                        pwm_ab: pwm@1b000 {
                                compatible = "amlogic,meson-axg-ee-pwm";
                                reg = <0x0 0x1b000 0x0 0x20>;
                        #size-cells = <2>;
                        ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
 
-                       clkc: clock-controller@0 {
-                               compatible = "amlogic,axg-clkc";
-                               #clock-cells = <1>;
-                               reg = <0x0 0x0 0x0 0x320>;
+                       sysctrl: system-controller@0 {
+                               compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
+                               reg = <0 0 0 0x400>;
+
+                               clkc: clock-controller {
+                                       compatible = "amlogic,axg-clkc";
+                                       #clock-cells = <1>;
+                               };
                        };
                };
 
                                        gpio-ranges = <&pinctrl_periphs 0 0 86>;
                                };
 
+                               emmc_pins: emmc {
+                                       mux {
+                                               groups = "emmc_nand_d0",
+                                                       "emmc_nand_d1",
+                                                       "emmc_nand_d2",
+                                                       "emmc_nand_d3",
+                                                       "emmc_nand_d4",
+                                                       "emmc_nand_d5",
+                                                       "emmc_nand_d6",
+                                                       "emmc_nand_d7",
+                                                       "emmc_clk",
+                                                       "emmc_cmd",
+                                                       "emmc_ds";
+                                               function = "emmc";
+                                       };
+                               };
+
+                               emmc_clk_gate_pins: emmc_clk_gate {
+                                       mux {
+                                               groups = "BOOT_8";
+                                               function = "gpio_periphs";
+                                       };
+                                       cfg-pull-down {
+                                               pins = "BOOT_8";
+                                               bias-pull-down;
+                                       };
+                               };
+
+                               sdio_pins: sdio {
+                                       mux {
+                                               groups = "sdio_d0",
+                                                       "sdio_d1",
+                                                       "sdio_d2",
+                                                       "sdio_d3",
+                                                       "sdio_cmd",
+                                                       "sdio_clk";
+                                               function = "sdio";
+                                       };
+                               };
+
+                               sdio_clk_gate_pins: sdio_clk_gate {
+                                       mux {
+                                               groups = "GPIOX_4";
+                                               function = "gpio_periphs";
+                                       };
+                                       cfg-pull-down {
+                                               pins = "GPIOX_4";
+                                               bias-pull-down;
+                                       };
+                               };
+
                                eth_rmii_x_pins: eth-x-rmii {
                                        mux {
                                                groups = "eth_mdio_x",
                                                function = "uart_ao_b_z";
                                        };
                                };
+
+                               mclk_b_pins: mclk_b {
+                                       mux {
+                                               groups = "mclk_b";
+                                               function = "mclk_b";
+                                       };
+                               };
+
+                               mclk_c_pins: mclk_c {
+                                       mux {
+                                               groups = "mclk_c";
+                                               function = "mclk_c";
+                                       };
+                               };
+
+                               tdma_sclk_pins: tdma_sclk {
+                                       mux {
+                                               groups = "tdma_sclk";
+                                               function = "tdma";
+                                       };
+                               };
+
+                               tdma_sclk_slv_pins: tdma_sclk_slv {
+                                       mux {
+                                               groups = "tdma_sclk_slv";
+                                               function = "tdma";
+                                       };
+                               };
+
+                               tdma_fs_pins: tdma_fs {
+                                       mux {
+                                               groups = "tdma_fs";
+                                               function = "tdma";
+                                       };
+                               };
+
+                               tdma_fs_slv_pins: tdma_fs_slv {
+                                       mux {
+                                               groups = "tdma_fs_slv";
+                                               function = "tdma";
+                                       };
+                               };
+
+                               tdma_din0_pins: tdma_din0 {
+                                       mux {
+                                               groups = "tdma_din0";
+                                               function = "tdma";
+                                       };
+                               };
+
+                               tdma_dout0_x14_pins: tdma_dout0_x14 {
+                                       mux {
+                                               groups = "tdma_dout0_x14";
+                                               function = "tdma";
+                                       };
+                               };
+
+                               tdma_dout0_x15_pins: tdma_dout0_x15 {
+                                       mux {
+                                               groups = "tdma_dout0_x15";
+                                               function = "tdma";
+                                       };
+                               };
+
+                               tdma_dout1_pins: tdma_dout1 {
+                                       mux {
+                                               groups = "tdma_dout1";
+                                               function = "tdma";
+                                       };
+                               };
+
+                               tdma_din1_pins: tdma_din1 {
+                                       mux {
+                                               groups = "tdma_din1";
+                                               function = "tdma";
+                                       };
+                               };
+
+                               tdmb_sclk_pins: tdmb_sclk {
+                                       mux {
+                                               groups = "tdmb_sclk";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_sclk_slv_pins: tdmb_sclk_slv {
+                                       mux {
+                                               groups = "tdmb_sclk_slv";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_fs_pins: tdmb_fs {
+                                       mux {
+                                               groups = "tdmb_fs";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_fs_slv_pins: tdmb_fs_slv {
+                                       mux {
+                                               groups = "tdmb_fs_slv";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_din0_pins: tdmb_din0 {
+                                       mux {
+                                               groups = "tdmb_din0";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_dout0_pins: tdmb_dout0 {
+                                       mux {
+                                               groups = "tdmb_dout0";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_din1_pins: tdmb_din1 {
+                                       mux {
+                                               groups = "tdmb_din1";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_dout1_pins: tdmb_dout1 {
+                                       mux {
+                                               groups = "tdmb_dout1";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_din2_pins: tdmb_din2 {
+                                       mux {
+                                               groups = "tdmb_din2";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_dout2_pins: tdmb_dout2 {
+                                       mux {
+                                               groups = "tdmb_dout2";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_din3_pins: tdmb_din3 {
+                                       mux {
+                                               groups = "tdmb_din3";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmb_dout3_pins: tdmb_dout3 {
+                                       mux {
+                                               groups = "tdmb_dout3";
+                                               function = "tdmb";
+                                       };
+                               };
+
+                               tdmc_sclk_pins: tdmc_sclk {
+                                       mux {
+                                               groups = "tdmc_sclk";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_sclk_slv_pins: tdmc_sclk_slv {
+                                       mux {
+                                               groups = "tdmc_sclk_slv";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_fs_pins: tdmc_fs {
+                                       mux {
+                                               groups = "tdmc_fs";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_fs_slv_pins: tdmc_fs_slv {
+                                       mux {
+                                               groups = "tdmc_fs_slv";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_din0_pins: tdmc_din0 {
+                                       mux {
+                                               groups = "tdmc_din0";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_dout0_pins: tdmc_dout0 {
+                                       mux {
+                                               groups = "tdmc_dout0";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_din1_pins: tdmc_din1 {
+                                       mux {
+                                               groups = "tdmc_din1";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_dout1_pins: tdmc_dout1 {
+                                       mux {
+                                               groups = "tdmc_dout1";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_din2_pins: tdmc_din2 {
+                                       mux {
+                                               groups = "tdmc_din2";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_dout2_pins: tdmc_dout2 {
+                                       mux {
+                                               groups = "tdmc_dout2";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_din3_pins: tdmc_din3 {
+                                       mux {
+                                               groups = "tdmc_din3";
+                                               function = "tdmc";
+                                       };
+                               };
+
+                               tdmc_dout3_pins: tdmc_dout3 {
+                                       mux {
+                                               groups = "tdmc_dout3";
+                                               function = "tdmc";
+                                       };
+                               };
                        };
                };
 
index 562c26a0ba333ed2989351f1d854b0a20fcab042..1cbb0829b15d084db78df033336ad9a4c5174075 100644 (file)
        clock-names = "isfr", "iahb", "venci";
 };
 
-&hiubus {
-       clkc: clock-controller@0 {
+&sysctrl {
+       clkc: clock-controller {
                compatible = "amlogic,gxbb-clkc";
                #clock-cells = <1>;
-               reg = <0x0 0x0 0x0 0x3db>;
        };
 };
 
                 <&clkc CLKID_SD_EMMC_A_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_A>;
 };
 
 &sd_emmc_b {
                 <&clkc CLKID_SD_EMMC_B_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_B>;
 };
 
 &sd_emmc_c {
                 <&clkc CLKID_SD_EMMC_C_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_C>;
 };
 
 &spicc {
index dba365ed4bd5f903e34f4c6fdf1b14d539db0d89..6e4a07112ed8d3d27063a4b01eb861bab690f120 100644 (file)
        clock-names = "isfr", "iahb", "venci";
 };
 
-&hiubus {
-       clkc: clock-controller@0 {
-               compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
+&sysctrl {
+       clkc: clock-controller {
+               compatible = "amlogic,gxl-clkc";
                #clock-cells = <1>;
-               reg = <0x0 0x0 0x0 0x3db>;
        };
 };
 
                 <&clkc CLKID_SD_EMMC_A_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_A>;
 };
 
 &sd_emmc_b {
        clocks = <&clkc CLKID_SD_EMMC_B>,
                 <&clkc CLKID_SD_EMMC_B_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
-       clock-names = "core", "clkin0", "clkin1";
+       clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_B>;
 };
 
 &sd_emmc_c {
                 <&clkc CLKID_SD_EMMC_C_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
+       resets = <&reset RESET_SD_EMMC_C>;
 };
 
 &spicc {