Merge tag 'v4.18-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matth...
authorOlof Johansson <olof@lixom.net>
Thu, 26 Jul 2018 20:06:14 +0000 (13:06 -0700)
committerOlof Johansson <olof@lixom.net>
Thu, 26 Jul 2018 20:06:14 +0000 (13:06 -0700)
- mt7622:
- add EINT support
- add gpio-ranges property to pinctrl
- add earlycon to rfb1 to find boot errros more easily
- fix uart clock
- add iommu and smi bindings

- mt6797:
- add support for the 96 board x20 development board

- fix cooling-cells of mt7622 and mt8173

* tag 'v4.18-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: Add Mediatek X20 Development Board support
  dt-bindings: arm: mediatek: Document Mediatek X20 Development Board
  dt-bindings: mediatek: Add binding for mt2712 IOMMU and SMI
  arm64: dts: mt7622: update a clock property for UART0
  arm64: dts: mt7622: add earlycon to mt7622-rfb1 board
  arm64: dts: mt7622: use gpio-ranges to pinctrl device
  arm64: dts: mediatek: Add missing cooling device properties for CPUs
  arm64: dts: mt7622: add EINT support to pinctrl

Signed-off-by: Olof Johansson <olof@lixom.net>
Documentation/devicetree/bindings/arm/mediatek.txt
Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
arch/arm64/boot/dts/mediatek/Makefile
arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts [new file with mode: 0644]
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
arch/arm64/boot/dts/mediatek/mt7622.dtsi
arch/arm64/boot/dts/mediatek/mt8173.dtsi
include/dt-bindings/memory/mt2712-larb-port.h [new file with mode: 0644]

index c07ddf4b781997f7171bab252ace9a5947d3a891..b7cc1b8889426b5c76879b00e241ec637a03ae6d 100644 (file)
@@ -47,6 +47,9 @@ Supported boards:
 - Evaluation board for MT6797(Helio X20):
     Required root node properties:
       - compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
+- Mediatek X20 Development Board:
+    Required root node properties:
+      - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
 - Reference board variant 1 for MT7622:
     Required root node properties:
       - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
index 53c20cae309f21b0e2e67303c83041ec7ba1e5c8..df5db732138d10658b5d659f25ca1ea3df28e025 100644 (file)
@@ -40,6 +40,7 @@ video decode local arbiter, all these ports are according to the video HW.
 Required properties:
 - compatible : must be one of the following string:
        "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
+       "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
        "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
 - reg : m4u register base and size.
 - interrupts : the interrupt of m4u.
@@ -50,8 +51,9 @@ Required properties:
        according to the local arbiter index, like larb0, larb1, larb2...
 - iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
        Specifies the mtk_m4u_id as defined in
-       dt-binding/memory/mt2701-larb-port.h for mt2701 and
-       dt-binding/memory/mt8173-larb-port.h for mt8173
+       dt-binding/memory/mt2701-larb-port.h for mt2701,
+       dt-binding/memory/mt2712-larb-port.h for mt2712, and
+       dt-binding/memory/mt8173-larb-port.h for mt8173.
 
 Example:
        iommu: iommu@10205000 {
index aa614b2d7cab5dcea3a761d5d4281cc53efc71ad..615abdd0eb0de6db2a35ee61b727f71d31c5cee2 100644 (file)
@@ -2,8 +2,9 @@ SMI (Smart Multimedia Interface) Common
 
 The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
 
-Mediatek SMI have two generations of HW architecture, mt8173 uses the second
-generation of SMI HW while mt2701 uses the first generation HW of SMI.
+Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use
+the second generation of SMI HW while mt2701 uses the first generation HW of
+SMI.
 
 There's slight differences between the two SMI, for generation 2, the
 register which control the iommu port is at each larb's register base. But
@@ -15,6 +16,7 @@ not needed for SMI generation 2.
 Required properties:
 - compatible : must be one of :
        "mediatek,mt2701-smi-common"
+       "mediatek,mt2712-smi-common"
        "mediatek,mt8173-smi-common"
 - reg : the register and size of the SMI block.
 - power-domains : a phandle to the power domain of this local arbiter.
index ddf46b8856a565da83744c4402ec9ae738e67b9e..083155cdc2a0e787df4510b919bf8d97ec1cce15 100644 (file)
@@ -4,8 +4,9 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
 
 Required properties:
 - compatible : must be one of :
-               "mediatek,mt8173-smi-larb"
                "mediatek,mt2701-smi-larb"
+               "mediatek,mt2712-smi-larb"
+               "mediatek,mt8173-smi-larb"
 - reg : the register and size of this local arbiter.
 - mediatek,smi : a phandle to the smi_common node.
 - power-domains : a phandle to the power domain of this local arbiter.
@@ -15,7 +16,7 @@ Required properties:
            the register.
   - "smi" : It's the clock for transfer data and command.
 
-Required property for mt2701:
+Required property for mt2701 and mt2712:
 - mediatek,larb-id :the hardware id of this larb.
 
 Example:
index ac17f60f998c58ed21a7c134dffae9436752b553..5b7fd6ad96e424b2ba4b656b388968ff3e3c7d72 100644 (file)
@@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
new file mode 100644 (file)
index 0000000..742938a
--- /dev/null
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for MediaTek X20 Development Board
+ *
+ * Copyright (C) 2018, Linaro Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "mt6797.dtsi"
+
+/ {
+       model = "Mediatek X20 Development Board";
+       compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0 0x40000000 0 0x80000000>;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+};
+
+&uart1 {
+       status = "okay";
+};
index b7837642c33a8b6aae187b8c6df2dc71c9994edb..a747b7bf132d1dafe8ff4d6b5ebcaaa5b7021f1e 100644 (file)
@@ -18,7 +18,7 @@
        compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
 
        chosen {
-               bootargs = "console=ttyS0,115200n1 swiotlb=512";
+               bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
        };
 
        cpus {
@@ -34,7 +34,7 @@
        };
 
        gpio-keys {
-               compatible = "gpio-keys-polled";
+               compatible = "gpio-keys";
                poll-interval = <100>;
 
                factory {
index 9213c966c2242ee6c8a14d270ffeb4712533f54f..de2c47bdbe6468698ca6c2548b5a08b6386c7b93 100644 (file)
@@ -89,6 +89,7 @@
                                 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
                        clock-names = "cpu", "intermediate";
                        operating-points-v2 = <&cpu_opp_table>;
+                       #cooling-cells = <2>;
                        enable-method = "psci";
                        clock-frequency = <1300000000>;
                };
 
        pio: pinctrl@10211000 {
                compatible = "mediatek,mt7622-pinctrl";
-               reg = <0 0x10211000 0 0x1000>;
+               reg = <0 0x10211000 0 0x1000>,
+                     <0 0x10005000 0 0x1000>;
+               reg-names = "base", "eint";
                gpio-controller;
                #gpio-cells = <2>;
+               gpio-ranges = <&pio 0 0 103>;
+               interrupt-controller;
+               interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               #interrupt-cells = <2>;
        };
 
        watchdog: watchdog@10212000 {
                reg = <0 0x11002000 0 0x400>;
                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
                clocks = <&topckgen CLK_TOP_UART_SEL>,
-                        <&pericfg CLK_PERI_UART1_PD>;
+                        <&pericfg CLK_PERI_UART0_PD>;
                clock-names = "baud", "bus";
                status = "disabled";
        };
index 94597e33c8065eb4b12ee805885988991d43e42c..abd2f15a544b24f7f411456389897f7b4a52a47b 100644 (file)
                        reg = <0x001>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       #cooling-cells = <2>;
                        clocks = <&infracfg CLK_INFRA_CA53SEL>,
                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
                        clock-names = "cpu", "intermediate";
                        reg = <0x101>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       #cooling-cells = <2>;
                        clocks = <&infracfg CLK_INFRA_CA57SEL>,
                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
                        clock-names = "cpu", "intermediate";
diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h
new file mode 100644 (file)
index 0000000..6f9aa73
--- /dev/null
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef __DTS_IOMMU_PORT_MT2712_H
+#define __DTS_IOMMU_PORT_MT2712_H
+
+#define MTK_M4U_ID(larb, port)         (((larb) << 5) | (port))
+
+#define M4U_LARB0_ID                   0
+#define M4U_LARB1_ID                   1
+#define M4U_LARB2_ID                   2
+#define M4U_LARB3_ID                   3
+#define M4U_LARB4_ID                   4
+#define M4U_LARB5_ID                   5
+#define M4U_LARB6_ID                   6
+#define M4U_LARB7_ID                   7
+#define M4U_LARB8_ID                   8
+#define M4U_LARB9_ID                   9
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0             MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_RDMA0            MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_WDMA0            MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_OD_R             MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_OD_W             MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_MDP_RDMA0             MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_WDMA              MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_DISP_RDMA2            MTK_M4U_ID(M4U_LARB0_ID, 7)
+
+/* larb1 */
+#define M4U_PORT_HW_VDEC_MC_EXT                MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT                MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_HW_VDEC_UFO_EXT       MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_HW_VDEC_VLD_EXT       MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_HW_VDEC_VLD2_EXT      MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT    MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT   MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT   MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT    MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_HW_VDEC_TILE          MTK_M4U_ID(M4U_LARB1_ID, 9)
+#define M4U_PORT_HW_IMG_RESZ_EXT       MTK_M4U_ID(M4U_LARB1_ID, 10)
+
+/* larb2 */
+#define M4U_PORT_CAM_DMA0              MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_CAM_DMA1              MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_CAM_DMA2              MTK_M4U_ID(M4U_LARB2_ID, 2)
+
+/* larb3 */
+#define M4U_PORT_VENC_RCPU             MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_VENC_REC              MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_VENC_BSDMA            MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_VENC_SV_COMV          MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_VENC_RD_COMV          MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_VENC_CUR_CHROMA       MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_VENC_REF_CHROMA       MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_VENC_CUR_LUMA         MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_VENC_REF_LUMA         MTK_M4U_ID(M4U_LARB3_ID, 8)
+
+/* larb4 */
+#define M4U_PORT_DISP_OVL1             MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define M4U_PORT_DISP_RDMA1            MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define M4U_PORT_DISP_WDMA1            MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define M4U_PORT_DISP_OD1_R            MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define M4U_PORT_DISP_OD1_W            MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define M4U_PORT_MDP_RDMA1             MTK_M4U_ID(M4U_LARB4_ID, 5)
+#define M4U_PORT_MDP_WROT1             MTK_M4U_ID(M4U_LARB4_ID, 6)
+
+/* larb5 */
+#define M4U_PORT_DISP_OVL2             MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_DISP_WDMA2            MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_MDP_RDMA2             MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_MDP_WROT0             MTK_M4U_ID(M4U_LARB5_ID, 3)
+
+/* larb6 */
+#define M4U_PORT_JPGDEC_WDMA_0         MTK_M4U_ID(M4U_LARB6_ID, 0)
+#define M4U_PORT_JPGDEC_WDMA_1         MTK_M4U_ID(M4U_LARB6_ID, 1)
+#define M4U_PORT_JPGDEC_BSDMA_0                MTK_M4U_ID(M4U_LARB6_ID, 2)
+#define M4U_PORT_JPGDEC_BSDMA_1                MTK_M4U_ID(M4U_LARB6_ID, 3)
+
+/* larb7 */
+#define M4U_PORT_MDP_RDMA3             MTK_M4U_ID(M4U_LARB7_ID, 0)
+#define M4U_PORT_MDP_WROT2             MTK_M4U_ID(M4U_LARB7_ID, 1)
+
+/* larb8 */
+#define M4U_PORT_VDO                   MTK_M4U_ID(M4U_LARB8_ID, 0)
+#define M4U_PORT_NR                    MTK_M4U_ID(M4U_LARB8_ID, 1)
+#define M4U_PORT_WR_CHANNEL0           MTK_M4U_ID(M4U_LARB8_ID, 2)
+
+/* larb9 */
+#define M4U_PORT_TVD                   MTK_M4U_ID(M4U_LARB9_ID, 0)
+#define M4U_PORT_WR_CHANNEL1           MTK_M4U_ID(M4U_LARB9_ID, 1)
+
+#endif