Merge tag 'renesas-arm-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel...
authorOlof Johansson <olof@lixom.net>
Sun, 23 Sep 2018 13:14:40 +0000 (06:14 -0700)
committerOlof Johansson <olof@lixom.net>
Sun, 23 Sep 2018 13:14:40 +0000 (06:14 -0700)
Renesas ARM Based SoC DT Updates for v4.20

* R-Car Gen1 SoCs: Include product name in DTSI files for ease of maintenance
* R-Car Gen2 SoCs:
  - Convert to new DU DT bindings
  - Correct SATA device sizes to 2 MiB
* R-Car H2 (r8a7790) based Porter board: Add DA9063 OnKey PMIC node
* R-Car E2 (r8a7794) based Silk board: Add DA9063 PMIC, RTC and OnKey nodes
* R-Car M2-N (r8a7793) based Gose board: Add DA9210 node for CPU DVFS
* RZ/G1C (R8A77470) SoC:
  - Add GPIO nodes
  - Add PFC support
  - Use r8a77470-sysc binding definitions
* RZ/G1C (r8a77470) iW-RainboW-G23S dev platform:
  - Specify EtherAVB PHY IRQ
  - Add pinctl support for scif1
* RZ/N1D (r9a06g032) SoC: Use r9a06g032-sysctrl binding definitions

* tag 'renesas-arm-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions
  ARM: dts: Include R-Car Gen1 product name in DTSI files
  ARM: dts: stout: Add DA9063 OnKey node
  ARM: dts: silk: Add DA9063 RTC and OnKey node
  ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ
  ARM: dts: r8a77470: Add GPIO support
  ARM: dts: silk: Add DA9063 PMIC node
  ARM: dts: gose: Add DA9210 node for CPU DVFS
  ARM: dts: rcar-gen2: Convert to new DU DT bindings
  ARM: dts: iwg23s-sbc: Add pinctl support for scif1
  ARM: dts: r8a77470: Add PFC support
  ARM: dts: r8a77470: Use r8a77470-sysc binding definitions
  ARM: dts: rcar: Correct SATA device sizes to 2 MiB

Signed-off-by: Olof Johansson <olof@lixom.net>
12 files changed:
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
arch/arm/boot/dts/r8a77470.dtsi
arch/arm/boot/dts/r8a7778.dtsi
arch/arm/boot/dts/r8a7779.dtsi
arch/arm/boot/dts/r8a7790-stout.dts
arch/arm/boot/dts/r8a7790.dtsi
arch/arm/boot/dts/r8a7791.dtsi
arch/arm/boot/dts/r8a7792.dtsi
arch/arm/boot/dts/r8a7793-gose.dts
arch/arm/boot/dts/r8a7794-silk.dts
arch/arm/boot/dts/r8a7794.dtsi
arch/arm/boot/dts/r9a06g032.dtsi

index e3585daafdd644a189a7098624558d2bccfdc422..22da819f186be395daae3c4ca1c97a590fa21fff 100644 (file)
@@ -35,6 +35,8 @@
 
        phy3: ethernet-phy@3 {
                reg = <3>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
                micrel,led-mode = <1>;
        };
 };
        clock-frequency = <20000000>;
 };
 
+&pfc {
+       scif1_pins: scif1 {
+               groups = "scif1_data_b";
+               function = "scif1";
+       };
+};
+
 &scif1 {
+       pinctrl-0 = <&scif1_pins>;
+       pinctrl-names = "default";
+
        status = "okay";
 };
index 87d32d3e23de2c177efccb146845e98aefd7f217..c053a28cd132a31896ce868b07a6078ccbb2540e 100644 (file)
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
+#include <dt-bindings/power/r8a77470-sysc.h>
 / {
        compatible = "renesas,r8a77470";
        #address-cells = <2>;
@@ -23,7 +24,7 @@
                        reg = <0>;
                        clock-frequency = <1000000000>;
                        clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
-                       power-domains = <&sysc 5>;
+                       power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
                        next-level-cache = <&L2_CA7>;
                };
 
@@ -32,7 +33,7 @@
                        compatible = "cache";
                        cache-unified;
                        cache-level = <2>;
-                       power-domains = <&sysc 21>;
+                       power-domains = <&sysc R8A77470_PD_CA7_SCU>;
                };
        };
 
                #size-cells = <2>;
                ranges;
 
+               gpio0: gpio@e6050000 {
+                       compatible = "renesas,gpio-r8a77470",
+                                    "renesas,rcar-gen2-gpio";
+                       reg = <0 0xe6050000 0 0x50>;
+                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+                       gpio-ranges = <&pfc 0 0 23>;
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       clocks = <&cpg CPG_MOD 912>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 912>;
+               };
+
+               gpio1: gpio@e6051000 {
+                       compatible = "renesas,gpio-r8a77470",
+                                    "renesas,rcar-gen2-gpio";
+                       reg = <0 0xe6051000 0 0x50>;
+                       interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+                       gpio-ranges = <&pfc 0 32 23>;
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       clocks = <&cpg CPG_MOD 911>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 911>;
+               };
+
+               gpio2: gpio@e6052000 {
+                       compatible = "renesas,gpio-r8a77470",
+                                    "renesas,rcar-gen2-gpio";
+                       reg = <0 0xe6052000 0 0x50>;
+                       interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+                       gpio-ranges = <&pfc 0 64 32>;
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       clocks = <&cpg CPG_MOD 910>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 910>;
+               };
+
+               gpio3: gpio@e6053000 {
+                       compatible = "renesas,gpio-r8a77470",
+                                    "renesas,rcar-gen2-gpio";
+                       reg = <0 0xe6053000 0 0x50>;
+                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+                       gpio-ranges = <&pfc 0 96 30>;
+                       gpio-reserved-ranges = <17 10>;
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       clocks = <&cpg CPG_MOD 909>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 909>;
+               };
+
+               gpio4: gpio@e6054000 {
+                       compatible = "renesas,gpio-r8a77470",
+                                    "renesas,rcar-gen2-gpio";
+                       reg = <0 0xe6054000 0 0x50>;
+                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+                       gpio-ranges = <&pfc 0 128 26>;
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       clocks = <&cpg CPG_MOD 908>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 908>;
+               };
+
+               gpio5: gpio@e6055000 {
+                       compatible = "renesas,gpio-r8a77470",
+                                    "renesas,rcar-gen2-gpio";
+                       reg = <0 0xe6055000 0 0x50>;
+                       interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+                       gpio-ranges = <&pfc 0 160 32>;
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       clocks = <&cpg CPG_MOD 907>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                       resets = <&cpg 907>;
+               };
+
+               pfc: pin-controller@e6060000 {
+                       compatible = "renesas,pfc-r8a77470";
+                       reg = <0 0xe6060000 0 0x118>;
+               };
+
                cpg: clock-controller@e6150000 {
                        compatible = "renesas,r8a77470-cpg-mssr";
                        reg = <0 0xe6150000 0 0x1000>;
                                     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 407>;
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 407>;
                };
 
                                          "ch12", "ch13", "ch14";
                        clocks = <&cpg CPG_MOD 219>;
                        clock-names = "fck";
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 219>;
                        #dma-cells = <1>;
                        dma-channels = <15>;
                                          "ch12", "ch13", "ch14";
                        clocks = <&cpg CPG_MOD 218>;
                        clock-names = "fck";
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 218>;
                        #dma-cells = <1>;
                        dma-channels = <15>;
                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 812>;
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 812>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
                               <&dmac1 0x29>, <&dmac1 0x2a>;
                        dma-names = "tx", "rx", "tx", "rx";
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 721>;
                        status = "disabled";
                };
                        dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
                               <&dmac1 0x2d>, <&dmac1 0x2e>;
                        dma-names = "tx", "rx", "tx", "rx";
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 720>;
                        status = "disabled";
                };
                        dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
                               <&dmac1 0x2b>, <&dmac1 0x2c>;
                        dma-names = "tx", "rx", "tx", "rx";
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 719>;
                        status = "disabled";
                };
                        dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
                               <&dmac1 0x2f>, <&dmac1 0x30>;
                        dma-names = "tx", "rx", "tx", "rx";
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 718>;
                        status = "disabled";
                };
                        dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
                               <&dmac1 0xfb>, <&dmac1 0xfc>;
                        dma-names = "tx", "rx", "tx", "rx";
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 715>;
                        status = "disabled";
                };
                        dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
                               <&dmac1 0xfd>, <&dmac1 0xfe>;
                        dma-names = "tx", "rx", "tx", "rx";
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 714>;
                        status = "disabled";
                };
                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
                        clocks = <&cpg CPG_MOD 408>;
                        clock-names = "clk";
-                       power-domains = <&sysc 32>;
+                       power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                        resets = <&cpg 408>;
                };
 
index 1bce16cc6b209e63f808b6d2190a573c071b30fc..05db0ccad7a6b745f172d78288d7a77a4a4a873c 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for Renesas r8a7778
+ * Device Tree Source for the R-Car M1A (R8A77781) SoC
  *
  * Copyright (C) 2013  Renesas Solutions Corp.
  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
index 6b997bc016ee8a9e989a38ce476bb1c4f62d9f26..3bc133d9489c61374120d60752ec6755c4c75a71 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for Renesas r8a7779
+ * Device Tree Source for the R-Car H1 (R8A77790) SoC
  *
  * Copyright (C) 2013 Renesas Solutions Corp.
  * Copyright (C) 2013 Simon Horman
 
        sata: sata@fc600000 {
                compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
-               reg = <0xfc600000 0x2000>;
+               reg = <0xfc600000 0x200000>;
                interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp1_clks R8A7779_CLK_SATA>;
                power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
index a13a92c2664507ee49d1ef8d0b3f5d80dbeffc5d..629da4cee1b971d6259317313f0f683103e1fe83 100644 (file)
                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                interrupt-controller;
 
+               onkey {
+                       compatible = "dlg,da9063-onkey";
+               };
+
                rtc {
                        compatible = "dlg,da9063-rtc";
                };
index 0925bdca438feedaa8ee956f8109fcca75dbbe1f..52a757f47bf08f57f4d2895b5735d03d74ea73f9 100644 (file)
                sata0: sata@ee300000 {
                        compatible = "renesas,sata-r8a7790",
                                     "renesas,rcar-gen2-sata";
-                       reg = <0 0xee300000 0 0x2000>;
+                       reg = <0 0xee300000 0 0x200000>;
                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 815>;
                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                sata1: sata@ee500000 {
                        compatible = "renesas,sata-r8a7790",
                                     "renesas,rcar-gen2-sata";
-                       reg = <0 0xee500000 0 0x2000>;
+                       reg = <0 0xee500000 0 0x200000>;
                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 814>;
                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
index 991ac6feedd5beb6123f7a12f98c8799d89f9565..25b6a99dd87a22c64519187e3cd10555330706ed 100644 (file)
                sata0: sata@ee300000 {
                        compatible = "renesas,sata-r8a7791",
                                     "renesas,rcar-gen2-sata";
-                       reg = <0 0xee300000 0 0x2000>;
+                       reg = <0 0xee300000 0 0x200000>;
                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 815>;
                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                sata1: sata@ee500000 {
                        compatible = "renesas,sata-r8a7791",
                                     "renesas,rcar-gen2-sata";
-                       reg = <0 0xee500000 0 0x2000>;
+                       reg = <0 0xee500000 0 0x200000>;
                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 814>;
                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
index 63a978ec81cc09f0a4d989fff7171d893ba07387..52d16a260db0b60577741f7334c6937ba17efff2 100644 (file)
                du: display@feb00000 {
                        compatible = "renesas,du-r8a7792";
                        reg = <0 0xfeb00000 0 0x40000>;
-                       reg-names = "du";
                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 724>,
index 6b2f3a4fd13d646c35e48fc46a7efa31ab42035e..f51601af89a2f4d5324e891a85944a6d57d2b074 100644 (file)
        status = "okay";
 };
 
+&cpu0 {
+       cpu0-supply = <&vdd_dvfs>;
+};
+
 &rwdt {
        timeout-sec = <60>;
        status = "okay";
                        compatible = "dlg,da9063-watchdog";
                };
        };
+
+       vdd_dvfs: regulator@68 {
+               compatible = "dlg,da9210";
+               reg = <0x68>;
+               interrupt-parent = <&irqc0>;
+               interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+               regulator-min-microvolt = <1000000>;
+               regulator-max-microvolt = <1000000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
 };
 
 &i2c4 {
index daec965889d3e5fe18e764daaf77758e24aacd0c..60e91ebfa65dc5b3d76cd28218b51aa4fceb8c17 100644 (file)
        clock-frequency = <400000>;
 };
 
+&i2c7 {
+       status = "okay";
+       clock-frequency = <100000>;
+
+       pmic@58 {
+               compatible = "dlg,da9063";
+               reg = <0x58>;
+               interrupt-parent = <&gpio3>;
+               interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-controller;
+
+               onkey {
+                       compatible = "dlg,da9063-onkey";
+               };
+
+               rtc {
+                       compatible = "dlg,da9063-rtc";
+               };
+
+               wdt {
+                       compatible = "dlg,da9063-watchdog";
+               };
+       };
+};
+
 &mmcif0 {
        pinctrl-0 = <&mmcif0_pins>;
        pinctrl-names = "default";
index ea2ca4bdaf1c129c3932644a45bce1145ebabfb6..886135a273cb6f2cbdfb0e8204704603d0f94f5c 100644 (file)
                du: display@feb00000 {
                        compatible = "renesas,du-r8a7794";
                        reg = <0 0xfeb00000 0 0x40000>;
-                       reg-names = "du";
                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
index afe29c95a006e8fa12d0ed66f5948e8ac1a17262..3e45375b79aa9c0dfb553b5653c0a3040504793c 100644 (file)
@@ -7,6 +7,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a06g032-sysctrl.h>
 
 / {
        compatible = "renesas,r9a06g032";
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
                        reg = <0>;
-                       clocks = <&sysctrl 84>;
+                       clocks = <&sysctrl R9A06G032_CLK_A7MP>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
                        reg = <1>;
-                       clocks = <&sysctrl 84>;
+                       clocks = <&sysctrl R9A06G032_CLK_A7MP>;
                        enable-method = "renesas,r9a06g032-smp";
                        cpu-release-addr = <0 0x4000c204>;
                };
@@ -82,7 +83,7 @@
                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&sysctrl 146>;
+                       clocks = <&sysctrl R9A06G032_CLK_UART0>;
                        clock-names = "baudclk";
                        status = "disabled";
                };