Add second TSC speed regular expression
authorReto Buerki <reet@codelabs.ch>
Tue, 12 Sep 2017 19:35:08 +0000 (21:35 +0200)
committerReto Buerki <reet@codelabs.ch>
Tue, 12 Sep 2017 19:46:41 +0000 (21:46 +0200)
Also look for the 'tsc: Detected <speed> processor' string if the
refined TSC clocksource regex search fails.

data/creator/processorcreator/dmesg
data/creator/processorcreator/dmesg_nokey
data/creator/processorcreator/dmesg_tsc_detected [new file with mode: 0644]
src/creator.py
test/test_creator.py

index 639d9be..9fa3945 100644 (file)
 [    0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
 [    0.000000] hpet clockevent registered
 [    0.000000] tsc: Fast TSC calibration using PIT
-[    0.004000] tsc: Detected 3192.667 MHz processor
 [    0.000002] Calibrating delay loop (skipped), value calculated using timer frequency.. 6385.33 BogoMIPS (lpj=12770668)
 [    0.000004] pid_max: default: 32768 minimum: 301
 [    0.000024] Security Framework initialized
index 848fa61..34e32fa 100644 (file)
 [    0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
 [    0.000000] hpet clockevent registered
 [    0.000000] tsc: Fast TSC calibration using PIT
-[    0.004000] tsc: Detected 3192.667 MHz processor
 [    0.000002] Calibrating delay loop (skipped), value calculated using timer frequency.. 6385.33 BogoMIPS (lpj=12770668)
 [    0.000004] pid_max: default: 32768 minimum: 301
 [    0.000024] Security Framework initialized
diff --git a/data/creator/processorcreator/dmesg_tsc_detected b/data/creator/processorcreator/dmesg_tsc_detected
new file mode 100644 (file)
index 0000000..292e7dd
--- /dev/null
@@ -0,0 +1,10 @@
+[    0.000000] console [tty0] enabled
+[    0.000000] allocated 33554432 bytes of page_cgroup
+[    0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
+[    0.000000] hpet clockevent registered
+[    0.000000] tsc: Fast TSC calibration using PIT
+[    0.004000] tsc: Detected 3192.667 MHz processor
+[    0.000002] Calibrating delay loop (skipped), value calculated using timer frequency.. 6385.33 BogoMIPS (lpj=12770668)
+[    0.000004] pid_max: default: 32768 minimum: 301
+[    0.000024] Security Framework initialized
+[    0.000039] AppArmor: AppArmor initialized
index 88f4139..e02f8f1 100644 (file)
@@ -78,24 +78,29 @@ class ProcessorCreator():
 
     def getSpeed(self, dmesgpath):
         "Gets speed value from dmesg"
-        regex = re.compile(r'.*Refined TSC clocksource calibration: '
-                           '(?P<speed>.*)')
+        regs = [re.compile(r'.*Refined TSC clocksource calibration: '
+                           '(?P<speed>.*)'),
+                re.compile(r'.*tsc: Detected (?P<speed>.*) processor')]
+
         result = 0
         try:
             data = extractor.extractData(dmesgpath)
-            match = regex.search(data)
-            if match is None:
-                message.addError("Could not find refined TSC clocksource "
-                                 "calibration results in: %s\n" % dmesgpath +
-                                 "Processor speed not found.")
-            result = util.getSpeedValue(match.group("speed"),
-                                        PROCESSOR_SPEED_KEYWORDS)
         except IOError:
             errstr = ("Could not read file: %s\n" % dmesgpath +
                       "Processor speed not found.")
             message.addError(errstr)
-        else:
-            return result
+
+        for regex in regs:
+            match = regex.search(data)
+            if match is not None:
+                result = util.getSpeedValue(match.group("speed"),
+                                            PROCESSOR_SPEED_KEYWORDS)
+                break
+
+        if not result:
+            message.addError("Could not find TSC speed in: %s\n" % dmesgpath)
+
+        return result
 
     def getVmxTimerRate(self, msrpaths, offset, vmxbitsize):
         # check for MSR
index 41035e0..3a8b16f 100644 (file)
@@ -107,10 +107,12 @@ class TestProcessorCreator:
 
     def test_getSpeed(self):
         dmesgloc = os.path.join(self.testdir, "dmesg")
+        dmesgloc2 = os.path.join(self.testdir, "dmesg_tsc_detected")
         dmesg_nokey = os.path.join(self.testdir, "dmesg_nokey")
         invalidloc = os.path.join(self.testdir, "invalidlocdmesg")
         KEY = "Refined TSC clocksource calibration"
         assert self.procreator.getSpeed(dmesgloc) == 3192.746
+        assert self.procreator.getSpeed(dmesgloc2) == 3192.667
         with pytest.raises(customExceptions.ForceQuit):
             self.procreator.getSpeed(invalidloc)
         with pytest.raises(customExceptions.ForceQuit):